JPH11177409A - Level shift circuit, signal driver and display device using the same, and semiconductor device - Google Patents

Abstract

(57) [Abstract] (with correction) [PROBLEMS] To reliably and quickly operate even when a switching element having a small on-current such as a TFT and a low threshold rise is used or an input signal driven by a low voltage is input. Level shift. A switching element connected in series between a high-potential-side supply terminal and a low-potential-side supply terminal.
1 and switching elements p2 and n2 also connected in parallel to the input signals In1 and In2 having voltage amplitudes corresponding to different power supply voltages and opposite phases to output signals Out1 and Out2 at different levels. Convert to
A transmitting means C1 for transmitting a signal corresponding to a change in the input signal In1 to one output terminal 31 having the same phase;
And a transmission means C2 for transmitting a signal corresponding to the change of the signal No. 2 to the other output terminal 30.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a level shift circuit using a transistor, a signal driver and a display device using the same, and a semiconductor device.

[0002]

2. Description of the Related Art As a level shift circuit, first and second input signals having voltage amplitudes corresponding to a first power supply voltage and opposite phases to each other are adapted to correspond to a second power supply voltage. 1st and 2nd having the same voltage amplitude
Is known.

FIG. 7 shows PMOS transistors p1 and p2.
FIG. 4 is a circuit diagram showing an example in which such a level shift circuit is configured using NMOS transistors n1 and n2. In this level shift circuit, when the first and second input signals In1 and In2 having opposite phases corresponding to the first power supply voltage (for example, 0 V and 5 V) are input to a pair of input terminals, the pair of output terminals are connected to the pair of output terminals. First and second output signals O corresponding to second power supply voltages (for example, 0 V and 10 V)
out1 and Out2 are output. Note that the pair of power supply terminals have a low potential VL on the NMOS transistor side,
The second power supply voltage is applied with the OS transistor side at the high potential VH.

When this level shift circuit is formed of a normal CMOS, and a signal corresponding to the first power supply voltage is input to In1 and In2 as an input signal, the level shift is performed according to the second power supply voltage. Output signals Out1 and Ou
t2 can be obtained.

However, as in the case where this level shift circuit is provided as a part of a drive circuit on a glass substrate constituting a liquid crystal display panel, a TFT (thin film transistor) is used.
, The ON current of each transistor is small,
When the threshold rise is bad or when the first power supply voltage is considerably lower than the second power supply voltage, the level-shifted signals Out1 and Out2 are In1 and In2.
In some cases, there is a problem that the inversion is not performed corresponding to the inversion of 2, or a long time is required until the inversion occurs.

The applicant of the present invention has previously conducted a prior art search (Patris) of the Japan Patent Information Organization (JAPIO).
The prior art was searched using a search formula: "(level * shifter) * (capacitance + capacitor)", and a search result of 20 hits was obtained. From this result, a technique for solving the above problem could not be found.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to use a switching element having a small on-current such as a TFT and having a low threshold rise, It is an object of the present invention to provide a level shift circuit which can surely perform a level shift even when a voltage input signal is input and has a high operation speed, a driving circuit, a display device, and a semiconductor device using the same.

[0008]

According to a first aspect of the present invention, there is provided a level shift circuit for receiving a first input signal and a second input signal having opposite phases corresponding to a first power supply voltage. A first conductive type first terminal connected in series between an input terminal and a second input terminal, and a high potential side supply terminal and a low potential side supply terminal of a second power supply voltage different from the first power supply voltage. A third switching element of the first conductivity type connected in series between the first switching element and the second switching element of the second conductivity type, and a high potential side supply terminal and a low potential side supply terminal of the second power supply voltage; A switching circuit formed by connecting an element and a fourth switching element of the second conductivity type in parallel, a connection portion between the first and second switching elements, and a control electrode of the third switching element. And the first output signal A second output terminal connected to a first output terminal to be output, a connection portion of the third and fourth switching elements, and a control electrode of the first switching element to output a second output signal; And the first input terminal is
The second input terminal is connected to a control electrode of the second switching element, and the second input terminal is connected to a control electrode of the fourth switching element, and the first input terminal is connected to the first and second input terminals. And a level shift circuit for converting a second input signal into the first and second output signals corresponding to the second power supply voltage, wherein the signal corresponds to a change in the signal input to the first input terminal. Is output to the second output terminal via the first transmission means, and a signal corresponding to a change in the signal input to the second input terminal is output to the first output terminal via the second transmission means. It is characterized by.

According to the first aspect of the present invention, a signal corresponding to a change in the first input signal is transmitted to the second output terminal, so that the second input signal corresponds to the rising (falling) of the first input signal. The output signal rises (falls). Further, since the signal corresponding to the change of the second input signal is transmitted to the first output terminal, the first output signal rises (falls) in response to the rising (falling) of the first input signal. Therefore, in addition to the operation of the conventional level shifter, due to these effects, a level shift circuit which has a fast response speed to the inversion of the first and second input signals and can perform the level shift reliably.

According to a second aspect, in the level shift circuit according to the first aspect, the first transmitting means is a capacitor connected between the first input terminal and the second output terminal. The second transmission means is a capacitor connected between the second input terminal and the first output terminal.

According to the second aspect of the present invention, since the first and second transmission means are capacitors, the level shift circuit can be easily formed.

According to a third aspect of the present invention, in the level shift circuit according to the first or second aspect of the present invention, between the high potential side supply terminal of the second power supply voltage and the first and third switching elements. And a resistance element is inserted therein.

According to the third aspect of the present invention, since the high potential side of the second power supply voltage is connected through the resistance element connected to the first switching element, the second power supply voltage inputted to the second switching element is connected. When one input signal becomes H level and the second switching element is turned on, the current flowing through the first switching element is limited, and the switching of the first output signal to L level can be performed quickly. Similarly, since the high-potential side of the second power supply voltage is connected via the resistance element connected to the third switching element,
The switching of the second output signal to the L level when the second input signal input to the switching element is at the H level can be performed quickly. As a result, a level shift circuit having a high response speed is obtained.

According to a fourth aspect of the present invention, in the level shift circuit according to the first or second aspect of the present invention, the first conductive type of the first conductivity type is inserted into a connection between the first switching element and the second switching element. A fifth switching element, and a sixth switching element of a first conductivity type inserted into a connection portion between the third switching element and the fourth switching element, wherein the first input terminal is The fifth output terminal is connected to a control electrode of the fifth switching device, the first output terminal is connected to a connection portion between the fifth switching device and the second switching device, and the second input terminal is connected to a control terminal of the sixth switching device. Connected to the electrode, the second
The output terminal is connected to a connection between the sixth switching element and the fourth switching element.

According to the fourth aspect of the present invention, the fifth switching element is connected to the first switching element and the second switching element.
The switching element is inserted, and the first input signal is connected to the control electrode of the fifth switching element.
The input signal becomes H level, and the fifth switching element is turned off at the same time as the second switching element is turned on. Therefore, when the first input signal goes high, the first output signal quickly goes low. Similarly, the sixth switching element is inserted at the connection between the third switching element and the fourth switching element, and the second input signal is connected to the control electrode of the sixth switching element. When the second input signal goes high, it quickly goes low. As a result, a level shift circuit that operates quickly and reliably is obtained.

According to a fifth aspect of the present invention, there is provided a level shift circuit, comprising:
A first input terminal and a second input terminal to which an input signal and a second input signal are input, and a high potential side supply terminal and a low potential side supply terminal of a second power supply voltage different from the first power supply voltage. A first switching element of the first conductivity type and a second switching element of the second conductivity type connected in series between the high-potential supply terminal and the low-potential supply terminal of the second power supply voltage; A third switching element of the first conductivity type and a fourth switching element of the second conductivity type connected to
A switching circuit connected in parallel, a connection portion of the first and second switching elements, and a control electrode of the third and fourth switching elements, for outputting a first output signal; A first output terminal, a connection portion between the third and fourth switching elements, and a second output terminal connected to the control electrodes of the first and second switching elements and outputting a second output signal. The first and second input signals input to the first and second input terminals are connected to the second input terminal.
A level shift circuit that converts the signal into a first and a second output signal corresponding to a power supply voltage of a first input terminal, wherein the first shift terminal transmits a signal corresponding to a change in a signal input to a first input terminal to the first output terminal. And a second transmitting means for transmitting a signal corresponding to a change in the signal input to the second input terminal to the second output terminal.

According to the level shift circuit of the present invention, the first output signal having the same phase as the first input signal and having a different voltage level, and the second output having the same phase as the second input signal and having a different voltage level. Signal. In addition, the level shift circuit can make the ground levels of the first and second input signals different from those of the first and second output signals.

According to a sixth aspect of the present invention, in any one of the first to fifth aspects, the first to fourth switching elements are TFTs each having a channel formed in a non-single-crystal semiconductor layer.

According to the sixth aspect of the invention, the first to fourth switching elements are TFTs each having a channel formed in a non-single-crystal semiconductor layer. In spite of being a transistor having a lower switching speed, the level shift circuit has a higher switching speed and operates reliably.

According to a seventh aspect of the present invention, there is provided a signal driver, comprising: a latch circuit for holding an image data signal; and a shift register circuit for outputting a sample pulse for transmitting the image data signal to the latch circuit. 7. The level shift circuit according to claim 1, wherein the level of the image data signal output from the latch circuit is shifted to a voltage corresponding to a predetermined power supply voltage. And an output unit that converts the converted image data signal into an analog signal and outputs it with a predetermined power capacity.

According to the seventh aspect of the present invention, a signal driver having a level shift circuit having the above-described functions and effects can be obtained.

The display device according to the invention described in claim 8 is:
A signal electrode group, a scan electrode group, a display unit including a display element arranged near each intersection of the signal electrode group and the scan electrode group, and a scan driver that drives the scan electrode group; A signal driver according to claim 7 for driving a signal electrode group.

According to the eighth aspect of the present invention, it is possible to obtain a display device including a signal driver including a level shift circuit having the above-described operation and effect.

According to a ninth aspect of the present invention, there is provided a semiconductor device forming the level shift circuit according to the sixth aspect, wherein each of the TFTs includes a source formed on the non-single-crystal semiconductor layer. And a drain, a gate insulating film, and a gate electrode, wherein the first and second transmission means are provided with a first conductive layer formed in the same layer as the non-single-crystal semiconductor layer, and the same as the gate electrode. It is a capacitor formed by sandwiching a first insulating layer formed in the same layer as the gate insulating film between the second conductive layer formed in the layer and the second conductive layer.

According to the ninth aspect of the present invention, since it is not necessary to form a separate layer for forming the first and second transmission means, it is configured to include the first and second transmission means. A semiconductor device having a level shift circuit can be easily formed.

In general, a gate insulating film is thinner than other insulating films, so that a large-capacity capacitor can be easily formed.

According to a tenth aspect of the present invention, there is provided a semiconductor device forming the level shift circuit according to the sixth aspect, wherein each of the TFTs includes a source formed on the non-single-crystal semiconductor layer. And a drain, a gate insulating film, a gate electrode, a first interlayer insulating film, and a wiring layer, wherein the first and second transmitting means are formed of a second conductive layer formed in the same layer as the gate electrode. A capacitor formed by sandwiching a second insulating layer formed in the same layer as the first interlayer insulating film between a layer and a third conductive layer formed in the same layer as the wiring layer. Features.

According to the tenth aspect of the present invention, since it is not necessary to form a separate layer for forming the first and second transmitting means, the first and second transmitting means are included. A semiconductor device having a level shift circuit can be easily formed.

According to a eleventh aspect of the present invention, in the semiconductor device according to the sixth aspect, each of the switching elements forming the level shift circuit according to the sixth aspect of the present invention and a second interlayer insulating film formed above the switching elements. A semiconductor device including a transparent electrode for a liquid crystal element to be formed, wherein each of the TFTs includes a source and a drain formed in the non-single-crystal semiconductor layer, a gate insulating film, a gate electrode; A first interlayer insulating film and a wiring layer;
The transmitting means is formed in the same layer as the second interlayer insulating film between a third conductive layer formed in the same layer as the wiring layer and a fourth conductive layer formed in the same layer as the transparent electrode. A capacitor formed with the third insulating layer formed therebetween.

According to the eleventh aspect of the present invention, since it is not necessary to form a separate layer for forming the first and second transmission means, it is configured to include the first and second transmission means. A semiconductor device having a level shift circuit can be easily formed.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below more specifically with reference to the drawings.

First Embodiment <Overall Configuration of Display Device> FIG. 1 is a block diagram showing a configuration of a liquid crystal display device as a display device according to a first embodiment of the present invention. As shown in this figure, the liquid crystal display device of the present embodiment includes an image information output source 74, an image information processing circuit 76, a scanning driver 80, a signal driver 82, a liquid crystal display panel 86 as a display unit, a clock circuit 70, and a power supply. The circuit 72 is included.

The image information output source 74 includes a memory such as a ROM and a RAM, a tuning circuit for synchronizing and outputting a video signal, and the like. Is output.

The image information processing circuit 76 includes a clock circuit 7
Process the image information based on the clock signal from 0,
It outputs image data, scan data, and control signals.
The display information processing circuit 76 can include, for example, an amplification circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, a clamp circuit, and the like.

The signal driver 82 receives image data and control signals from the image information processing circuit, and outputs a signal voltage to the signal electrodes of the display unit, and includes a level shift circuit.

The scanning driver 80 is used for the image information processing circuit 7.
The scan data and the control signal are received from 6 and a scan voltage is output to the scan electrode of the liquid crystal display panel.

The liquid crystal display panel 86 as a display section has a plurality of signal electrodes 87 as a group of signal electrodes, a plurality of scanning electrodes 88 as a group of scanning electrodes intersecting with the plurality of signal electrodes 87, and the signal electrode 87.
A liquid crystal element (not shown), which is a display element, is disposed at each intersection area between the scan driver 88 and the scan driver 88, and displays an image by driving the signal driver 82 and the scan driver 80. In this embodiment, the signal driver 82 and the scanning driver 80 are formed on a glass substrate constituting a part of the liquid crystal display panel 86 by using a thin film transistor (TFT) manufacturing technique.

The clock circuit 70 supplies a clock signal to each of the above circuits.

The power supply circuit 72 generates each voltage including the second power supply voltage for driving the above-described level shift circuit,
Power is supplied to each of the above circuits.

<Signal Driver> FIG. 2 shows a signal driver 8 used in a liquid crystal display device as a display device of the present embodiment.
FIG. As shown in this figure, the signal driver 82 of the present embodiment includes a shift register circuit 60, a digital wiring 62, a latch circuit 64, a level shift circuit 10,
And an output unit 66.

A plurality of shift register circuits 60 are provided corresponding to the number of signal electrodes 87 of the liquid crystal display panel 86, and the shift register circuits 60 transmit data signals corresponding to each signal electrode 87 of the liquid crystal display panel 86 from the digital wiring 62 transmitting image data signals. The sampling pulse indicating the timing of capturing
4

The digital wiring 62 is connected to a liquid crystal display panel 86
And a wiring for transmitting a digital signal corresponding to the signal level of each signal electrode 87 at a predetermined timing, and has a number of wirings D0, D1, D2 and D3 corresponding to the number of bits. In the case of the present embodiment, an example corresponding to 4 bits is shown,
Digital wiring having a number of lines corresponding to the number of bits according to the display specifications of the liquid crystal display device can be provided.

In the latch circuit 64, a number corresponding to the number of bits of the digital wiring 62 is provided for each signal electrode 87 of the liquid crystal display panel 86, and wirings D0, D1, D2, and D3 of each bit of the digital wiring 62 are provided. Corresponding latch circuit 64
It is connected to the. The latch circuit 64 captures and holds the data on the digital wiring 62 at a timing corresponding to the sampling pulse output from the shift register circuit 60.

The level shift circuit 10 has a number corresponding to the number of bits of the digital wiring 62 corresponding to each signal electrode 87 of the liquid crystal display panel. The signal output from the corresponding latch circuit 64 is input to the level shift circuit 10. In FIG. 2, the input and output to each level shift circuit 10 are shown by a single line, respectively. However, normally, a pair of signals having phases opposite to each other are input from the corresponding latch circuit 64. A pair of signals having phases opposite to each other are output to the output unit 66 from each level shift circuit.

The output section 66 receives the output from the plurality of level shift circuits 10 corresponding to each bit of the digital image data signal for each signal electrode 87 of the liquid crystal display panel 86, and outputs each signal electrode 87 of the liquid crystal display panel 86. Is synthesized, and the signal is input to each signal electrode 87 of the liquid crystal display panel 86 which is a display unit.

<Level Shift Circuit> FIG. 3 is a circuit diagram of the level shift circuit 10 of the present embodiment used for the signal driver 82 described above.

In the level shift circuit 10 of the present embodiment, the first input signal In1 and the second input signal In2, which are logic pulse signals of opposite phases corresponding to a first power supply voltage, for example, (0 V, 5 V), When input to the first input terminal 26 and the second input terminal 27, the second power supply voltage, for example, (0
V, 10V), the first output signal Out1 and the second output signal Out being logic pulse signals of opposite phases to each other.
2 is output to the first output terminal 30 and the second output terminal 31.

In this level shift circuit 10, as shown in FIG. 3, a PMOS transistor p1 as a first switching element and an NMOS transistor n1 as a second switching element are connected in series, and are a third switching element. The PMOS transistor p2 and the NMOS transistor n2, which is the fourth switching element, are connected in series, and the serially connected MOS transistors are connected in parallel. Also, PM
The junction between the OS transistor p1 and the NMOS transistor n1 and the gate that is the control electrode of the PMOS transistor p2 are connected to the first output terminal 30. The junction between the PMOS transistor p2 and the NMOS transistor n2 and the gate as the control electrode of the PMOS transistor p1 are connected to the second output terminal 31. The gate of the NMOS transistor n1 is connected to the first input terminal 26, and the NMOS transistor n1
The second gate is connected to the second input terminal 27. Further, the first input terminal 26 and the second output terminal 31 are connected via a capacitor C1 which is a first transmission means, and the second input terminal 27 and the first output terminal 30 are connected to a capacitor which is a second transmission means. They are connected via C2.

The high potential supply terminal 42 to which the high potential side VH of the second power supply voltage is connected is connected to each of the PMOS transistors p1 and p2, and the low potential side VL to which the low potential side VL of the second power supply voltage is connected. Potential side supply terminal 43 is NMOS
It is connected to each of the transistors n1 and n2.

FIG. 4 shows the level shift circuit 1 of the present embodiment.
A schematic timing chart showing the relationship between the first and second input signals In1 and In2 and the first and second output signals Out1 and Out2, and the MOS transistors p1 and n1 corresponding to each section of the timing chart. , P
2 and a table showing ON / OFF states of n2. In the figure, ON of each of the MOS transistors p1, n1, p2, and n2 is indicated by ○, and OFF is indicated by X.

Here, the level shift circuit 1 of the present embodiment
0 will be described with reference to FIG.

First, 0V, which is L (low) corresponding to the first power supply voltage, is input to the first input terminal 26 as the first input signal In1, and H (H) of the first power supply voltage is input as the second input signal In2. In the state where 5V (high) is input to the second input terminal 27, that is, in the section shown as A in FIG.
When 5 V is input to the gate of the MOS transistor n2 and n
2 is turned on, and Out2 goes low. Since Out2 is input to the gate of the PMOS transistor p1, p1 is turned on. Further, the signal n of L is input to the gate as the first input signal In1.
Since 1 is off, Out1 becomes the second power supply voltage H of 10 V, that is, VH.

Next, the first and second input signals In1, I
The signal level of n2 is inverted, and In1 becomes the first power supply voltage H (5 V), and In2 becomes L (0 V). This I
The inversion of the signal levels of n1 and In2 occurs through a transition section exaggeratedly shown in FIG. Therefore, the first and second output signals Out1 and Out2 are also inverted through the corresponding transition sections. That is, I
When the voltage of n1 rises and exceeds the threshold voltage Vthn of n1, n1 is turned on, and the voltage of Out1 starts to decrease (section B in FIG. 4). And the voltage of Out1 is p2
When the voltage becomes lower than the threshold voltage Vthp, p2 turns on, and Out2 starts to increase (section C in FIG. 4). Out
2, the inversion of Out1 and Out2 is completed (the latter half of the section D in FIG. 4).

Thereafter, when the signal levels of the first input signal In1 and the second input signal In2 are inverted again, In1, Ou
t1, n1, p1 and In2, Out2, n
2 and p2 are interchanged, but the signal levels of the first output signal Out1 and the second output signal Out2 are inverted in the same manner as described above (sections E, F, and F2 in FIG. 4).
A).

As described above, when the first input signal In1 and the second input signal In2 are inverted, the completion of the inversion of the first output signal Out1 or the second output signal Out2 which rises to the H level is the latest.

However, the level shift circuit 1 of the present embodiment
0, the first input terminal 26 and the second
Since the output terminal 31 is connected by the capacitor C1, and the second input terminal 27 and the first output terminal 30 are similarly connected by the capacitor C2, the voltage change corresponding to the voltage change of the first input signal In1 immediately occurs. Second output terminal 31
And the voltage change corresponding to the voltage change of the second input signal In2 is immediately transmitted to the first output terminal 30. for that reason,
The second output signal Out having the same phase as the first input signal In1
2 and the first output signal Out1 having the same phase as the second input signal In2.

The first input signal In1 is a capacitor C
1, the signal is also input to the gate of the PMOS transistor p1, which is the first switching element, so that when the first input signal In1 is inverted from L level to H level,
The turning off of p1 is promoted, and the inversion of the first output signal Out1 at which the potential is not determined to the L level is promoted due to the inquiry of p1 and n1 until the turning off of p1. Further, p2, whose first output signal Out1 is input to the gate, is turned on when Out1 goes to the L level. Therefore, if the timing at which Out1 goes to the L level is advanced, the on of p2 is also hastened. , Out2 H
Reversal to the level is also promoted. Further, since the second input signal In2 is input to the gate of p2 via the capacitor C2, this also promotes the turning on of p2, and
The inversion of ut2 to the H level is also promoted.

Next, when In2 changes from L level to H level and In1 inverts from H level to L level,
In1 and In2, p1 and p2, n1 and n2, C1 and C
2, and the respective relationships between Out1 and Out2 are interchanged. However, as in the case described above, due to the presence of C1 and C2, the first output signals Out1 and Out1 corresponding to the inversion of the first input signal In1 and the second input signal In2. The inversion timing of the second output signal Out2 is advanced.

FIG. 5 shows the level shift circuit 1 of the present embodiment.
0 is formed as a semiconductor device using a TFT in which a channel is formed in a non-single-crystal layer such as polysilicon or amorphous silicon.
4 shows the results obtained by using a simulation program to determine the relationship between the first output signal and the second output signals Out1 and Out2. Although the second input signal In2 is not shown in this figure, a signal having the same phase as that of In1 and having the opposite phase is used. In this simulation, each transistor p
1, n1, p2, and n2 have a channel width and channel length of 5 μm, and the first and second transmission means C1 and C2 have a channel width of 10 μm.
This is the result when 0 fF is set. Also, assuming the reality, signals from the buffer are given to In1 and In2, and therefore, there is waveform distortion due to delay.

As described above, the level shift circuit 10 of the present embodiment uses the TFT having a low switching speed with a channel formed in a non-single-crystal layer as the switching elements p1, n1, p2, and n2. 1 input signal In
The level shift circuit 10 in which the first output signal Out1 and the second output signal Out2 are inverted quickly and reliably in response to the inversion of the first and second input signals In2.

<Semiconductor Device> The level shift circuit 10 of the present embodiment is formed as a semiconductor device 90 shown in a schematic cross-sectional view in FIG. 6, that is, a semiconductor device 90 having a MOS transistor as a switching element and a capacitor. Can be.

The semiconductor device 90 of the present embodiment is used for a liquid crystal display panel 86 driven by an active matrix, and has a TFT (Thin Film Transistor) formed on an insulating substrate 91 made of glass, a polymer film or the like.
tor) 18 and a transparent electrode 89 are formed as a thin film.

The TFT 18 of the semiconductor device 90 has the structure shown in FIG.
As shown in FIG. 1, a non-single-crystal semiconductor layer 1 made of polysilicon, amorphous silicon, or the like is used.
7, a source 19 or a drain 20 formed by doping impurities with a source 1 of the non-single-crystal semiconductor layer 17
A channel 21 formed between the drain 9 and the drain 20;
A gate insulating film 22 formed of an oxide film or the like, a gate electrode 23 formed of tantalum or the like, a first interlayer insulating film 24 located above them and formed of an oxide film or the like, and formed of aluminum or the like; Wiring layer 25.

The transparent electrode 89 of this semiconductor device 90
A second layer made of an oxide film or the like is formed above the wiring layer 25 of the FT 18.
An ITO (Indium Tin) is provided with an interlayer insulating film 29 interposed therebetween.
Oxide) or the like.

As described above, in order to configure the level shift circuit 10 of the present embodiment, not only the MOS transistors p1, n1, p2, and n2, which are the switching elements formed as the TFT 18, but also the capacitor C
1, C2 is also required. Semiconductor device 90 of the present embodiment
Is a semiconductor device in which the capacitors C1 and C2 are formed in the vicinity of the TFT 18 by using the conductive layer and the insulating layer formed on the same layer as the conductive layer and the insulating film for forming the TFT 18 and the transparent electrode 89. Is formed as That is, as shown as A, B and C in FIG. 6, the capacitors C1 and C2 can be formed in at least the following three types of patterns by combining these conductive layers and insulating layers.

As shown in FIG. 6A, the first pattern includes a first conductive layer 92 which is a conductive layer formed by doping a large amount of impurities in the same layer as the non-single-crystal semiconductor layer 17;
A second conductive layer 94, which is a conductive layer formed in the same layer as the gate electrode 23, is used as a pair of capacitor electrodes, and a first insulating layer 93, which is an insulating layer formed in the same layer as the gate insulating film 22, is used as a dielectric layer. To form a capacitor. In this case, the first insulating layer 93 which is a dielectric layer
Is relatively thin, like the gate insulating film 22, so that a large-capacity capacitor can be easily formed.

The second pattern is, as shown in FIG. 6B, a second conductive layer 94 which is a conductive layer formed on the same layer as the gate electrode 23, and a conductive layer formed on the same layer as the wiring layer 25. The third conductive layer 96 is used as a pair of capacitor electrodes, and a capacitor is formed using a second insulating layer, which is an insulating layer formed in the same layer as the first interlayer insulating film 24, as a dielectric layer.

The third pattern includes a third conductive layer 96 which is a conductive layer formed on the same layer as the wiring layer 25 and a conductive layer formed on the same layer as the transparent electrode 89 as shown as C in FIG. Is used as a pair of capacitor electrodes, and a third insulating layer 97, which is an insulating layer formed in the same layer as the second interlayer insulating film 29, is used as a dielectric layer to form a capacitor. .

Although not shown, capacitors C1,
C2 is not limited to the above, and the first conductive layer 92, the second conductive layer 9
A pair other than the above may be formed from the fourth, third conductive layer 96, and the fourth conductive layer 98, and another capacitor may be formed with an insulating layer interposed therebetween. A stacked capacitor can be formed using a combination of electrodes.

As described above, according to the present embodiment, since it is not necessary to form a separate layer for forming the first and second transmission means C1 and C2, the first and second transmission means C
The semiconductor device 90 having the level shift circuit 10 including 1 and C2 can be easily formed.

[First Comparative Example] FIG. 7 is a circuit diagram of a level shift circuit according to the present comparative example, which is shown in the column of "Background Art and Problems to be Solved by the Invention". This level shift circuit, except for the absence of C1 and C2,
This is the same as the level shift circuit 10 of the first embodiment shown in FIG.

Each of the MOS transistors p1, n1, p2, and n2 of the level shift circuit of the comparative example is a first TFT as a TFT.
The first input signal In1 and the first and second output signals Out1 and Out2 when formed in the same manner as in the embodiment.
8A and 8B show simulation results of the relationship with
Shown in In this figure, the second input signal In2 is not shown, but is a signal of the same level in phase opposite to that of In1.
As shown in FIGS. 8A and 8B, Out1 and Out2 remain at 0 V despite the fact that In1 repeats inversion at a voltage amplitude corresponding to the first power supply voltage (0 V, 5 V).
Alternatively, only slightly fluctuating from 10 V, the H level is 10 V and the L level is 0 corresponding to the second power supply voltage.
Inversion with V has not occurred. As described above, when a level shift circuit as shown in FIG. 7, that is, a level shift circuit different from the level shift circuit of the first embodiment only in the point that C1 and C2 are not provided is formed by TFT, the level shift circuit is used It turns out that it may not work.

[Second Embodiment] The display device of the present embodiment,
The signal driver and the semiconductor device are different from the display device, the signal driver 82, and the semiconductor device 90 of the first embodiment in that a circuit described below is used as a level shift circuit. Other points are the same as in the first embodiment, and a description thereof will be omitted.

FIG. 9 shows the level shift circuit 3 of this embodiment.
8 is a circuit diagram of FIG. As is clear from this figure, in the level shift circuit 38 of the present embodiment, the PMOS transistor p1 as the first switching element is connected to the high-potential supply terminal 42 of the power supply voltage via the resistor R1 connected to the source. The third embodiment is different from the level shift circuit of the first embodiment in that a PMOS transistor p2, which is a third switching element, is connected to a high potential side supply terminal 42 of a power supply via a resistor R2 connected to its source. The other parts are the same as those of the level shift circuit 10 of the first embodiment, and therefore, are denoted by the same reference numerals as those of the first embodiment, and description thereof will be omitted.

In the level shift circuit 38 of the present embodiment, since the resistor R1 is inserted between the high-potential-side supply terminal 42 of the second power supply voltage and the PMOS transistor p1, p
The current flow into 1 is limited by R1. First
As shown in FIG.
When n1 is inverted from L to H, that is, in transition sections B and C, both p1 and n1 are turned on, and the level shift circuit 38 of the present embodiment is in an unstable state. Is restricted, and the first output signal Out1 becomes L level earlier, so that the first and second output signals Out1 and Out2 corresponding to the inversion of the first and second input signals In1 and In2 can be hastened earlier. it can.

Similarly, the level shift circuit 3 of the present embodiment
In No. 8, since the resistor R2 is inserted between the high-potential-side supply terminal 42 of the second power supply voltage and p2, the flow of current into p2 is limited by R2. In the level shift circuit 10 of the first embodiment, as shown in FIG.
When In2 is inverted from L to H, transition sections E and F
In this case, an unstable state occurs in which both p2 and n2 are turned on. However, in the level shift circuit 38 of the present embodiment, the current flowing into p2 is limited by this R2,
Since Out2 quickly becomes L, In1, In2
Of the Out1 and Out2 corresponding to the inversion of.

FIGS. 10A and 10B show the relationship between In1, Out1, and Out2 when the level shift circuit 38 of the present embodiment is formed as a TFT semiconductor device.
9 shows a result obtained by using a simulation program. Although In2 is not shown in FIG.
A signal of the same level in phase opposite to that of 1 is used. In addition,
In this simulation, the channel width and channel length of each MOS transistor are set to 5 μm, and C1 and C2
Is set to 100 fF.

As described above, the level shift circuit 38 of the present embodiment is a level shift circuit 38 having a high response speed to the inversion of the first and second input signals In1 and In2. Further, since C1 and C2 are provided as in the case of the level shift circuit 10 of the first embodiment, a level at which the transistors p1, n1, p2, and n2 operate reliably even when the semiconductor device is formed of a TFT. It becomes a shift circuit.

[Second Comparative Example] FIG. 11 is a circuit diagram of a level shift circuit according to this comparative example. This level shift circuit is the same as the level shift circuit 38 of the second embodiment shown in FIG. 9 except that C1 and C2 are not provided.

The first input signal In1 when the transistors p1, n1, p2, and n2 of the level shift circuit of the comparative example are formed as TFTs in the same manner as in the first embodiment.
FIG. 12A and FIG. 12B show simulation results showing the relationship between the first and second output signals Out1 and Out2.
Shown in In this figure, the second input signal In2 is not shown, but it is a signal having the same level as that of In1 in the opposite phase.
As shown in FIGS. 12A and 12B, Out1 and Out2 remain at 0 despite the fact that In1 repeats inversion at a voltage amplitude corresponding to the first power supply voltage (0 V, 5 V).
With only a slight variation from V or 10 V, the inversion between the H level of 10 V and the L level of 0 V corresponding to the second power supply voltage does not occur. As described above, when the level shift circuit of this comparative example, which is different from the level shift circuit 38 shown in FIG. It can be seen that the shift circuit may not function.

[Third Embodiment] The display device of the present embodiment,
The signal driver and the semiconductor device are different from the display device, the signal driver 82, and the semiconductor device 90 of the first embodiment in that a circuit described below is used as a level shift circuit. The other points are the same as those of the first embodiment, and a description thereof will be omitted.

FIG. 13 is a circuit diagram of the level shift circuit 48 of the present embodiment. Level shift circuit 4 of the present embodiment
8 is that the fifth switching element p1a is inserted between the PMOS transistor p1 as the first switching element and the NMOS transistor n1 as the second switching element, and the gate thereof is connected to the first input terminal 26. And that a PMOS transistor p2a is inserted between the PMOS transistor p2 as the third switching element and the NMOS transistor n2 as the fourth switching element, and the gate thereof is connected to the second input terminal 27. This is different from the level shift circuit 10 of the first embodiment. The other parts are the same as those of the level shift circuit 10 of the first embodiment, and therefore, are denoted by the same reference numerals and description thereof is omitted.

The level shift circuit 48 according to the present embodiment is configured such that p
1a is inserted between p1 and n1, and the first input terminal 26 is also connected to the gate of p1a.
When the input signal In1 is inverted from L level to H level,
At the same time when n1 turns on, p1a turns off. Therefore, as shown in FIG. 4 used for describing the first embodiment,
In transition sections B and C, which occur as In1 is inverted from the L level to the H level, both p1 and n1 are turned on, and the state in which the output voltage of the first output signal Out1 becomes unstable is as follows. In the present embodiment,
Out1 is turned off by turning off the inserted p1a.
1 and almost no, and In1 goes from L level to H level and n1 turns on almost simultaneously with Out.
1 is an L level for quick switching. Also,
Since the first input terminal 26 and the second output terminal 31 are coupled by C1, the voltage of Out2 is also raised with the inversion of In1 from the L level to the H level, and the Lout of Out2 is increased.
Inversion from the level to the H level is also promoted.

Similarly, the level shift circuit 4 of this embodiment
8, p2a is inserted between p2 and n2,
Since the second input terminal 27 is also connected to the gate of 2a, when In2 is inverted from L level to H level, O2
Since ut2 is cut off from p2 by p2a, O
ut2 is quickly inverted to the L level. Further, since the second input terminal 27 and the first output terminal 30 are coupled by C2, the inversion of Out1 from the L level to the H level is promoted with the inversion of the In2 from the L level to the H level. Is done.

FIGS. 14A and 14B show that the level shift circuit 48 of the present embodiment is connected to each of the switching elements p1 and p1.
a, n1, p2, p2a, n2, a TFT having a channel width and channel length of 5 μm, and a first input signal In1 when formed as a semiconductor device in which the first and second transmission means C1, C2 are 10 fF; It is a result obtained by a simulation of a relationship between the first and second output signals Out1 and Out2.

As described above, since the level shift circuit 48 of the present embodiment can perform rapid switching by the added fifth and sixth switching elements p1a and p2a, the semiconductor device in which each switching element is a TFT. Therefore, the level shift circuit can operate reliably and quickly even if the above-mentioned condition is satisfied.

[Third Comparative Example] FIG. 15 is a circuit diagram of a level shift circuit according to this comparative example. This level shift circuit is similar to the level shift circuit 48 of the third embodiment shown in FIG. 13 except that the first and second transmission means C1 and C2 are not provided.
Is the same as

The first input signal In1 when the level shift circuit of this comparative example is formed as a semiconductor device in which each of the switching elements p1, p1a, n1, p2, p2a, and n2 is a TFT similar to the third embodiment. And the first and second
FIGS. 16A and 16B show the results of a simulation of the relationship between the output signals Out1 and Out2.
Although the second input signal In2 is not shown in FIG.
2 is input as a signal of the same level in phase opposite to that of In1. As shown in this figure, the first and second output signals Out1 and Out1, although In1 repeats inversion with a voltage amplitude corresponding to the first power supply voltage (0V, 5V).
Out2 only slightly varies from 0V or 10V,
Inversion between the H level (10 V) and the L level (0 V) corresponding to the second power supply voltage does not occur. That is, FIG.
The level shift circuit 48 of the third embodiment shown in FIG.
FIGS. 16A and 16B show that when the level shift circuit of the present comparative example, which is different only in that the second transfer means C1 and C2 are not provided, is formed of a TFT, it may not function as the level shift circuit. Indicates.

[Fourth Embodiment] The display device of the present embodiment,
The signal driver and the semiconductor device are different from the display device, the signal driver 82, and the semiconductor device 90 of the first embodiment in that a circuit described below is used as a level shift circuit. The other points are the same as those of the first embodiment, and a description thereof will be omitted.

FIG. 17 is a circuit diagram showing the level shift circuit 54 of the present embodiment. This level shift circuit 54
As in the case of the level shift circuit 10 of the first embodiment, a PMOS transistor p1 as a first switching element and an NMOS transistor n1 as a second switching element are connected in series, and a PMOS as a third switching element. The transistor p2 and the NMOS transistor n2, which is the fourth switching element, are connected in series, and the serially connected MOS transistors are connected in parallel. The high potential side supply terminal 42 of the second power supply voltage is connected to the PMOS transistor p.
1 and p2, and the low potential side supply terminal 43 of the second power supply voltage is connected to each of the NMOS transistors n1 and n2.

The junction between the PMOS transistor p1 and the NMOS transistor n1 and the respective gates serving as control electrodes of the PMOS transistor p2 and the NMOS transistor n2 are connected to the first output terminal 30.
Then, the junction between the PMOS transistor p2 and the NMOS transistor n2 and the PMOS transistor p1
And the respective gates serving as control electrodes of the NMOS transistor n1 are connected to the second output terminal 31. Further, the first output terminal 30 is connected to one end of a capacitor C1 serving as a first transmission unit, and the other end of the capacitor C1 is a terminal to which the first input signal In1 is input. The second output terminal 31 is connected to one end of a capacitor C2, which is a second transmitting means, and the other end of the capacitor C2 is connected to the second output terminal.
This is a terminal to which the input signal In2 is input.

In the case of the present embodiment, the first input signal In1 is input to the first output terminal 30 via the capacitor C1,
Since the second input signal In2 is input to the second output terminal 31 via the capacitor C2, the first and second input signals I2
Only signals corresponding to changes in n1 and In2 are input to the first and second output terminals 30 and 31. Therefore, the first
The DC levels of the second input signals In1 and In2 do not affect the response of the level shift circuit 54 of the present embodiment. FIG. 18 shows the level shift circuit 54 of the present embodiment.
1 is an example of a first input signal In1 input to the first input terminal. Note that I
In2 having the same phase and the opposite phase to n1 is also input to the level shift circuit 54 at the same time.

FIG. 19 shows a first output signal Ou of the level shift circuit 54 of this embodiment corresponding to the input signal In1.
It is an example of t1. It should be noted that the same level of O
ut2 is simultaneously output from the level shift circuit 54 of the present embodiment. The output potentials of Out1 and Out2 correspond to the high potential side VH and the low potential side VL of the second power supply voltage. In this example, the H level is 5V,
The L level is -5V. Also, in the level shift circuit of the present embodiment, unlike the above embodiments, In1 and Out1, and In2 and Out2 have the same phase.

FIG. 20 shows a modification in which the level shift circuit 54 of this embodiment is driven by a second power supply voltage of 10 V on the high potential side and 0 V on the low potential side.
And when the second input signals In1 and In2 are applied,
The output of the first output signal Out1 is shown. Ou
Out2, which is in the opposite phase to t1 and at the same level, is simultaneously output from the level shift circuit 54 of the present embodiment.

FIG. 21 is a modified example in which the level shift circuit 54 of the present embodiment is driven by the second power supply voltage of 11 V on the high potential side and 1 V on the low potential side. The output of the first output signal Out1 when the first and second input signals In1 and In2 are applied is shown.

As described above, in the level shift circuit 54 of the present embodiment, the potential on the low potential side and / or the high potential side is different from the first power supply voltage based on the first and second input signals. By using the second power supply voltage, the first
The first and second output voltages Out1 and O2 have completely different voltage ranges from the first and second input voltages In1 and In2.
ut2 can be obtained.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments.
Various modifications can be made within the scope of the present invention or within the equivalent scope of the claims.

For example, in each of the above-described embodiments, an example in which an enhancement type TFT is used as each switching element has been described. However, a depletion type TFT or another FET is used.
The present invention can also be applied by using.

The liquid crystal display panel as a display unit is not limited to an active matrix liquid crystal display panel using a three-terminal switching element represented by a TFT or a two-terminal switching element represented by an MIM in terms of a driving method. , A simple matrix liquid crystal display panel without a switching element in the panel itself, a static drive liquid crystal display panel, and TN type, STN
Various types of liquid crystal display panels such as a liquid crystal display panel of a shape, a guest host type, a phase transition type, and a ferroelectric type can be used.

Further, in each of the above embodiments, an example in which a liquid crystal display panel is used as a display unit has been described. However, the display unit may be a plasma display panel, an FED (Field Emission Disp.
lay) panel or the like.

In each of the above embodiments, an example in which the level shift circuit is used for the signal driver of the liquid crystal display device has been described. However, the level shift circuit can be used for the scan driver of the liquid crystal display device. The present invention can be used not only for a liquid crystal display device but also for various other digital circuits.

[0102]

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a display device of the present invention.

FIG. 2 is a configuration diagram schematically showing a signal driver of the present invention.

FIG. 3 is a circuit diagram of a level shift circuit according to the first embodiment.

FIG. 4 is a schematic timing chart illustrating an operation of the level shift circuit according to the first embodiment.

5A and 5B are graphs showing simulation results of input / output signals when the level shift circuit of the first embodiment is formed as a predetermined semiconductor device. FIG. 5A shows an output signal, and FIG. Indicates an input signal.

FIG. 6 is a schematic sectional view showing a part of the semiconductor device of the present invention.

FIG. 7 is a circuit diagram of a level shift circuit according to a first comparative example.

FIGS. 8A and 8B are graphs showing simulation results of input / output signals when the level shift circuit of the first comparative example is formed as a predetermined semiconductor device, wherein FIG. 8A shows an output signal, and FIG. Indicates an input signal.

FIG. 9 is a circuit diagram of a level shift circuit according to a second embodiment.

FIGS. 10A and 10B are graphs showing simulation results of input / output signals when the level shift circuit of the second embodiment is formed as a predetermined semiconductor device, wherein FIG. 10A shows an output signal, and FIG. Indicates an input signal.

FIG. 11 is a circuit diagram of a level shift circuit according to a second comparative example.

12A and 12B are graphs showing simulation results of input / output signals when the level shift circuit of the second comparative example is formed as a predetermined semiconductor device. FIG. 12A shows an output signal, and FIG. Indicates an input signal.

FIG. 13 is a circuit diagram of a level shift circuit according to a third embodiment.

FIGS. 14A and 14B are graphs showing simulation results of input / output signals when the level shift circuit of the third embodiment is formed as a predetermined semiconductor device, wherein FIG. 14A shows an output signal and FIG. Indicates an input signal.

FIG. 15 is a circuit diagram of a level shift circuit according to a third comparative example.

FIGS. 16A and 16B are graphs showing simulation results of input / output signals when the level shift circuit of the third comparative example is formed as a predetermined semiconductor device. FIG. 16A shows an output signal, and FIG. Indicates an input signal.

FIG. 17 is a circuit diagram of a level shift circuit according to a fourth embodiment.

FIG. 18 is an example of a first input signal to the level shift circuit of the fourth embodiment.

FIG. 19 is an example of a first output signal to the level shift circuit of the fourth embodiment.

FIG. 20 is an example of a first output signal to the level shift circuit of the fourth embodiment.

FIG. 21 is an example of a first output signal to the level shift circuit of the fourth embodiment.

[Explanation of symbols]

10, 38, 48, 54 Level shift circuit 17 Non-single-crystal semiconductor layer 18 TFT 19 Source 20 Drain 21 Channel 22 Gate insulating film 23 Gate electrode 24 First interlayer insulating film 25 Wiring layer 26 First input terminal 27 Second input terminal Reference Signs List 29 second interlayer insulating film 30 first output terminal 31 second output terminal 42 high-potential-side supply terminal of second power supply voltage 43 low-potential-side supply terminal of second power supply voltage 60 shift register circuit 64 latch circuit 66 output unit 80 scanning Driver 82 Signal driver 86 Liquid crystal display panel (display unit) 87 Signal electrode 88 Scan electrode 89 Transparent electrode 90 Semiconductor device 91 Insulating substrate 92 First conductive layer 93 First insulating layer 94 Second conductive layer 95 Second insulating layer 96 First Third conductive layer 97 Third insulating layer 98 Fourth conductive layer C1 Capacitor (first transmission means) C2 Capacitor Pita (second transmission means) p1 PMOS transistor (first switching element) n1 NMOS transistor (second switching element) p2 PMOS transistor (third switching element) n2 NMOS transistor (fourth switching element) P1a PMOS transistor (fifth switching element) Element) P1b PMOS transistor (sixth switching element) R1, R2 resistance element

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H03K 5/02

Claims (11)

[Claims] 1. A first input terminal and a second input terminal to which a first input signal and a second input signal having phases opposite to each other corresponding to a first power supply voltage are input, and different from the first power supply voltage. A first conductive type first switching element and a second conductive type second switching element connected in series between a high potential side supply terminal and a low potential side supply terminal of a second power supply voltage; The third switching element of the first conductivity type and the fourth switching element of the second conductivity type connected in series between the high potential side supply terminal and the low potential side supply terminal of the power supply voltage are connected in parallel. A switching circuit formed by: connecting the first and second switching elements;
A first output terminal connected to a control electrode of the switching element and outputting a first output signal; a connection part of the third and fourth switching elements;
A second output terminal connected to a control electrode of the switching element and outputting a second output signal, wherein the first input terminal is connected to a control electrode of the second switching element; The second input terminal is connected to a control electrode of the fourth switching element, and the first and second input signals input to the first and second input terminals correspond to the second power supply voltage. A level shift circuit that converts the signal into a first output signal and a second output signal, wherein a signal corresponding to a change in a signal input to the first input terminal is output to the second output terminal via a first transmission unit. A level shift circuit that outputs a signal corresponding to a change in a signal input to the second input terminal to the first output terminal via a second transmission unit. 2. The device according to claim 1, wherein the first transmitting unit is a capacitor connected between the first input terminal and the second output terminal, and wherein the second transmitting unit is connected to the second input terminal. A level shift circuit comprising a capacitor connected between a terminal and the first output terminal. 3. The device according to claim 1, wherein a resistance element is inserted between the high potential side supply terminal of the second power supply voltage and the first and third switching elements. Level shift circuit. 4. The switching device according to claim 1, wherein a fifth switching element of a first conductivity type inserted into a connection portion between the first switching element and the second switching element; and a third switching element. A sixth switching element of a first conductivity type inserted into a connection portion with the fourth switching element; and the first input terminal is connected to a control electrode of the fifth switching element. The first output terminal is connected to a connection between the fifth switching element and the second switching element, the second input terminal is connected to a control electrode of the sixth switching element, and the second output terminal is A level shift circuit connected to a connection between the sixth switching element and the fourth switching element. 5. A first input terminal and a second input terminal to which a first input signal and a second input signal having phases opposite to each other corresponding to a first power supply voltage are input, and different from the first power supply voltage. A first conductive type first switching element and a second conductive type second switching element connected in series between a high potential side supply terminal and a low potential side supply terminal of a second power supply voltage; A third switching element of the first conductivity type and a fourth switching element of the second conductivity type connected in series between the high potential supply terminal and the low potential supply terminal of the power supply voltage are connected in parallel. A formed switching circuit, a first output terminal connected to a connection portion of the first and second switching elements, and a control electrode of the third and fourth switching elements and outputting a first output signal; The third and fourth switching elements And a second output terminal connected to the control electrode of the first and second switching elements and configured to output a second output signal. A level shift circuit for converting the first and second input signals to the first and second output signals corresponding to the second power supply voltage, wherein the level shift circuit is adapted to detect a change in a signal input to a first input terminal. A first transmission unit that transmits a corresponding signal to the first output terminal; and a second transmission unit that transmits a signal corresponding to a change in the signal input to the second input terminal to the second output terminal. A level shift circuit characterized by the above. 6. The level shift circuit according to claim 1, wherein the first to fourth switching elements are TFTs each having a channel formed in a non-single-crystal semiconductor layer. 7. A latch circuit for holding an image data signal, a shift register circuit for outputting a sample pulse for transmitting the image data signal to the latch circuit, and the image data output from the latch circuit. The level shift circuit according to any one of claims 1 to 6, wherein the signal is level-shifted to a voltage corresponding to a predetermined power supply voltage, and an image data signal output from the level shift circuit is converted into an analog signal. And an output unit for outputting with a power capacity of: 8. A display unit comprising a signal electrode group, a scan electrode group, a display element arranged near each intersection of the signal electrode group and the scan electrode group, and driving the scan electrode group. A display device comprising: a scan driver; and the signal driver according to claim 7, which drives the signal electrode group. 9. The semiconductor device forming the level shift circuit according to claim 6, wherein each of the TFTs includes a source and a drain formed in the non-single-crystal semiconductor layer, a gate insulating film, and a gate electrode. Wherein the first and second transmitting means comprise: a first conductive layer formed in the same layer as the non-single-crystal semiconductor layer; and a second conductive layer formed in the same layer as the gate electrode. A semiconductor device comprising a capacitor formed with a first insulating layer formed in the same layer as the gate insulating film interposed therebetween. 10. The semiconductor device forming the level shift circuit according to claim 6, wherein each of the TFTs includes a source and a drain formed in the non-single-crystal semiconductor layer, a gate insulating film, and a gate electrode. , A first interlayer insulating film, and a wiring layer, wherein the first and second transmission means are formed in the same layer as the wiring layer, and the second conductive layer is formed in the same layer as the gate electrode. A semiconductor device comprising a capacitor formed by sandwiching a second insulating layer formed in the same layer as the first interlayer insulating film between the third conductive layer and the third conductive layer. 11. A switching element forming the level shift circuit according to claim 6, and a transparent electrode for a liquid crystal element formed on the switching element with a second interlayer insulating film interposed therebetween. A semiconductor device, wherein each of the TFTs includes a source and a drain formed in the non-single-crystal semiconductor layer, a gate insulating film, a gate electrode, a first interlayer insulating film, and a wiring layer. The first and second transmission means may include a second conductive layer formed between the third conductive layer formed on the same layer as the wiring layer and a fourth conductive layer formed on the same layer as the transparent electrode.
A semiconductor device characterized by being a capacitor formed by sandwiching a third insulating layer formed in the same layer as an interlayer insulating film.