200834504 ’九、發明說明： 【發明所屬之技術領域】 本發明係關於一種移位暫存器及採用該移位暫存器之 液晶顯示裝置。 【先前技術】 目前薄膜電晶體（Thin Film Transistor，TFT)液晶顯示 β裝置已逐漸成為各種數位產品之標準輸出設備，然，其需 要設計適當的驅動電路以保證其穩定工作。 通常’液晶顯不裝置的驅動電路包括一貧料驅動電路 及一掃描驅動電路。資料驅動電路用於控制每一像素單元 之顯示輝度，掃描驅動電路則用於控制薄膜電晶體之導通 與截止。二驅動電路均應用移位暫存器作為核心電路單 元。通常，移位暫存器係由複數移位暫存單元串聯而成， 且前一移位暫存單元之輸出訊號為後一移位暫存單元之輸 •入訊號。 請參閱圖1，係一種先前技術移位暫存器之移位暫存 單元之電路圖。該移位暫存單元100包括一第一時鐘反相 電路110、一換流電路120及一第二時鐘反相電路130。該 移位暫存單元 100之各電路均由 PMOS(P-channel Metal-Oxide Semiconductor，P溝道金屬氧化物半導體）型 電晶體組成，每一 PM0S型電晶體均包括一閘極、一源極 及/没極。 該苐一時鐘反相電路110包括一第^一電晶體Ml、一 200834504 第二電晶體M2、一第三電晶體M3、一第四電晶體M4、 一第一輸出端V01及一第二輸出端V02。該第一電晶體 ΜΓ之閘極接收該移位暫存單元100之前一移位暫存單元 之輸出訊號VS，其源極接收來自外部電路之高電平訊號 VDD，其汲極連接至該第二電晶體M2之源極。該第二電 晶體M2之閘極及其汲極接收來自外部電路之低電平訊號 VSS。該第三電晶體M3及該第四電晶體Μ4之閘極均接收 來自外部電路之反相時鐘訊號0它，二者之汲極分別作為該 第一時鐘反相電路110之第一輸出端V01及第二輸出端 V02,且該第三電晶體M3之源極連接至該第一電晶體Ml 之汲極，該第四電晶體M4之源極連接至該第一電晶體Ml 之閘極。 該換流電路120包括一第五電晶體M5、一第六電晶 體M6及一訊號輸出端VO。該第五電晶體M5之閘極連接 至該第一輸出端V01，其源極接收來自外部電路之高電平 訊號VDD，其汲極連接至該第六電晶體M6之源極。該第 六電晶體M6之閘極連接至該第二輸出端V02，其汲極接 收來自外部電路之低電平訊號VSS，其源極係該移位暫存 單元100之訊號輸出端VO。 該第二時鐘反相電路130包括一第七電晶體M7、一 第八電晶體M8、——第九電晶體M9及一第十電晶體M10。 該第七電晶體M7之閘極連接至該訊號輸出端VO,其源極 接收來自外部電路之高電平訊號VDD，其汲極連接至該第 八電晶體M8之源極。該第八電晶體M8之閘極及其汲極 均接收來自外部電路之低電平訊號VSS。該第九電晶體 200834504 • M9之源極連接至該第一輸出端VOl，其閘極接收來自外 部電路之時鐘訊號CK，其汲極連接至該第七電晶體M7 之汲極。該第十電晶體之閘極接收外部電路之時鐘訊號 CK，其源極連接至該第二輸出端V02,其汲極連接至該訊 號輸出端VO。 請一併參閱圖2,係該移位暫存單元100之工作時序 圖。在ΤΊ時間内，該前一移位暫存單元之輸出訊號VS由 高電平跳變為低電平，反相時鐘訊號CK由低電平跳變為高 •電平，則使該第三電晶體M3及該第四電晶體M4截止， 進而使該第一時鐘反相電路110斷開。而該時鐘訊號CK 由高電平跳變為低電平，使該第九電晶體M9及該第十電 晶體M10導通，進而使該第二時鐘反相電路130導通，而 該訊號輸出端VO初始狀態之高電平經該第十電晶體 M10，使該第六電晶體M6截止，而該第八電晶體M8輸出 之低電平經由該第九電晶體M9，使該第五電晶體M5導 通，進而使其源極之南電平訊號VDD輸出至該訊號輸出 鲁端VO，故該訊號輸出端VO保持高電平輸出。 在T2時間内，該反相時鐘訊號CK由高電平跳變為低 電平，則使該第三電晶體M3及該第四電晶體M4導通， 進而使該第一時鐘反相電路110導通。而該時鐘訊號CK 由低電平跳變為高電平，則使該第九電晶體M9及該第十 電晶體M10截止，進而使該第二時鐘反相電路130斷開。 該輸入訊號VS由高電平跳變為低電平，則使該第一電晶 體Ml導通，其源極之高電平VDD經該第三電晶體M3截 止該第五電晶體M5,且該輸入訊號VS之低電平經該第四 9 200834504 ' 電晶體M4導通該第六電晶體M6，使該訊號輸出端VO輸 出低電平。 在T 3時間内’該反相時鐘訊號CK由低電平跳變為雨 電平，則使該第三電晶體M3及該第四電晶體M4截止， 進而使該第一時鐘反相電路110斷開。而該時鐘訊號CK 由高電平跳變為低電平，使該第九電晶體M9及該第十電 晶體M10導通，進而使該第二時鐘反相電路130導通。該 訊號輸出端VO之低電平導通該第七電晶體M7,其源極之 春高電平經該第九電晶體M9截止該第五電晶體M5。同時， 該訊號輸出端VO之低電平亦經該第十電晶體M10導通該 第六電晶體M6,該第六電晶體M6之汲極低電平使該訊號 輸出端VO保持低電平輸出。 在T4時間内，該反相時鐘訊號0它由高電平跳變為低 電平，則使該第三電晶體M3及該第四電晶體Μ4導通， 進而使該第一時鐘反相電路110導通。而該時鐘訊號CK 由低電平跳變為高電平，使該第九電晶體Μ9及該第十電 •晶體Μ10截止，進而使該第二時鐘反相電路120斷開。輸 入訊號VS之高電平經該第四電晶體Μ4截止該第六電晶 體Μ6,而該第二電晶體M2之汲極低電平經該第三電晶體 M3導通該第五電晶體Μ5 ’使其源極之南電平輸出至該訊 號輸出端VO,使該訊號輸出端VO之輸出由低電平跳變為 高電平。 該移位暫存器的各移位暫存單元100所用電晶體數量 較多，且各訊號走線的繞線較複雜，故該移位暫存器的電 路結構較複雜。 200834504 .料’該移位暫存器可應用於液晶顯示裝置 數位電子產品中。例如液晶顯示裝置的 = 描驅動電路需要該移位暫存器實現列掃描或二路= 能。然，該移位暫存器的電路結構較複雜，容 =擾，故㈣該移位暫存器作為資料驅 掃ς動 =液晶顯示裝置在進行列掃描或行掃描時=口 亦容易相互干擾。 谷1唬間 【發明内容】 有鑑於此，提供 必要。 種電路結構簡單之移位暫存器實為 要 另’提供-種可避免訊號干擾之液晶顯示裝置亦為必 二種移位暫存器，其包括複數移位暫存單元，每一移 外部電路的時鐘訊號、反相時鐘訊號、前 暫存早70之輸出訊號及前一級移位暫存單元 相輸出訊號控制。每一移位暫存單元包括一上拉電路、一 :拉：路、一第一輸出電路、一第二輸出電路及一反相電 ，該上拉電路、下拉電路及該第一輸出電路呈有一公丘 =點，該上拉電路為該公共節點提供高電平訊號，該下ς 八路，該公共節點提供低電平訊號。該第—輪出電路在該 =共節點的控制下輸出時鐘訊號，該第二輸出電路在該反 。目時鐘訊號的控制下輸出低電平訊號，該反相電路將第一 或第二輸出電路的輸出訊號反相後輸出 種液晶顯示裝置，其包括一液晶顯示面板 資料 11 200834504 驅動電路及一掃描驅動電路，該資料驅動電路為該液晶領 =面，提供資料訊號，該掃描驅動電路為該液晶顯示面板 提供掃描訊號，該資料驅動電路及該掃描驅動電路分別包 括一移位暫存器以控制資料訊號與掃描訊號之輸出時序。 該移位暫存器包括複數移位暫存單元，每一移位暫存單元 均=外部電路的時鐘訊號、反相時鐘訊號、_一級移位暫 存單元之輸出訊號及前一級移位暫存單元之反相輸出訊號 控，，每一移位暫存單元包括一上拉電路、一下拉電路二 :第一輸出電路、一第二輸出電路及一反相電路。該上拉 電路、下拉電路及該第一輸出電路具有一公共節點，該上 拉，路為該公共節點提供高電平訊號，該下拉電路為該公 共即點提供低電平訊號，該第一輸出電路在該公共節點的 控制下輸出時鐘訊號，該第二輸出電路在該反相時鐘訊號 的控制下輸出低電平訊號，該反相電路將第一或第二輸出b 電路的輸出訊號反相後輸出。 ij 與先丽技術相比，本發明移位暫存器的每一移位暫存 :凡由六顆電晶體構成，且沒有複雜的繞線，故該移位暫 存器的電路結構簡單，從而可避免不必要雜訊干擾發生。 同時，因電晶體數量較少，在生產中的錯誤機率也相應較 低’從而可以提高產品的良率。 由於該移位暫存器的電路結構較簡單，因此可避免不 ^要雜訊干擾發生。使㈣移位暫存器之掃㈣動電路及 動電路在進行行掃描或列掃描時，其各輸出訊號間 效果0產生訊號干擾，從而提高了該液晶顯示褒置的顯示 12 200834504 【實施方式】 請參閱圖3,其係本發明移位暫存器較佳實施方式之 結構示意圖。該移位暫存器20包括複數結構相同之移位暫 存單元200，該複數移位暫存單元200依次串聯。每一移 位暫存單元200包括一時鐘訊號輸入端TS、一反相時鐘訊 號輸入端TSB、一第一輸入端VIN1、一第二輸入端VIN2、 一輸出端VOUT、一反相輸出端VOUTB、一高電平輸入端 _ VH及一低電平輸入端VL。每一移位暫存單元200之時鐘 訊號輸入端TS接收外部電路（圖未示）之時鐘輸入訊號 CK，其反相時鐘訊號輸入端TSB接收外部電路（圖未示） 之反相時鐘輸入訊號CKB，其高電平輸入端VH接收外部 電路（圖未示）之高電平訊號VDD，其低電平輸入端VL接 收外部電路（圖未示）之低電平訊號VSS。其第一輸入端 VIN1電連接至前一級移位暫存單元200之輸出端VOUT， 其第二輸入端VIN2電連接前一級移位暫存單元200之反 鲁相輸出端VOUTB，其輸出端VOUT電連接至後一級移位 暫存單元200之第一輸入端VIN1，其反相輸出端VOUTB 電連接至後一級移位暫存單元200之第二輸入端VIN2。即 前一級移位暫存單元200之輸出訊號為後一級移位暫存單 元200之第一輸入訊號，前一級移位暫存單元200之反相 輸出訊號為後一級移位暫存單元200之第二輸入訊號，且 每一移位暫存單元200同時由外部電路的時鐘訊號CK、 反相時鐘訊號CKB、高電平訊號VDD及低電平訊號VSS 控制。 13 200834504 " 請參閱圖4，其係圖3之移位暫存單元之電路示意圖。 該移位暫存單元200包括一上拉電路31、一下拉電路32、 一第一輸出電路33、——第二輸出電路34、一緩衝器35及 一反相器36，該缓衝器35係由二反相器串接而成，主要 用於保持該移位暫存單元200之輸出波形，避免輸出波形 失真。該上拉電路31、下拉電路32及該第一輸出電路33 具有一公共節點P，該上拉電路31為該公共節點P提供高 電平訊號，該下拉電路32為該公共節點P提供低電平訊 ⑩號。該上拉電路31受該第一輸入端¥謂1控制，該下拉電 路32受該第二輸入端VIN2及該公共節點P控制。該第一 輸出電路33在該公共節點P的控制下輸出時鐘訊號CK至 該缓衝器35,該第二輸出電路34在該反相時鐘訊號CKB 的控制下輸出低電平訊號VSS至該缓衝器，該缓衝器將接 收的時鐘訊號CK或低電平訊號VSS傳送至該輸出端 VOUT。該反相器36將輸出端VOUT的訊號反相後輸入至 該反相輸出端VOUTB。 ⑩ 該上拉電路31包括一第一電晶體Ml，該第一電晶體[Technical Field] The present invention relates to a shift register and a liquid crystal display device using the shift register. [Prior Art] At present, Thin Film Transistor (TFT) liquid crystal display β devices have gradually become standard output devices for various digital products. However, it is necessary to design an appropriate driving circuit to ensure stable operation. Generally, the driving circuit of the liquid crystal display device includes a lean driving circuit and a scan driving circuit. The data driving circuit is used to control the display luminance of each pixel unit, and the scanning driving circuit is used to control the on and off of the thin film transistor. Both drive circuits use a shift register as the core circuit unit. Generally, the shift register is formed by connecting a plurality of shift register units in series, and the output signal of the previous shift register unit is the input signal of the latter shift register unit. Please refer to FIG. 1, which is a circuit diagram of a shift register unit of a prior art shift register. The shift register unit 100 includes a first clock inversion circuit 110, a converter circuit 120, and a second clock inverting circuit 130. Each circuit of the shift register unit 100 is composed of a PMOS (P-channel Metal-Oxide Semiconductor) type transistor, and each PMOS transistor includes a gate and a source. And / no. The clock-inverting circuit 110 includes a first transistor M1, a 200834504 second transistor M2, a third transistor M3, a fourth transistor M4, a first output terminal V01, and a second output. End V02. The gate of the first transistor receives the output signal VS of the shift register unit before the shift register unit 100, and the source receives the high level signal VDD from the external circuit, and the drain thereof is connected to the first The source of the second transistor M2. The gate of the second transistor M2 and its drain receive a low level signal VSS from an external circuit. The gates of the third transistor M3 and the fourth transistor 接收4 receive the inverted clock signal 0 from the external circuit, and the drains of the two are respectively used as the first output terminal V01 of the first clocked inverter circuit 110. And a second output terminal V02, and the source of the third transistor M3 is connected to the drain of the first transistor M1, and the source of the fourth transistor M4 is connected to the gate of the first transistor M1. The converter circuit 120 includes a fifth transistor M5, a sixth transistor M6 and a signal output terminal VO. The gate of the fifth transistor M5 is connected to the first output terminal V01, the source thereof receives the high level signal VDD from the external circuit, and the drain thereof is connected to the source of the sixth transistor M6. The gate of the sixth transistor M6 is connected to the second output terminal V02, and the drain terminal receives the low level signal VSS from the external circuit, and the source thereof is the signal output terminal VO of the shift register unit 100. The second clock inverting circuit 130 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The gate of the seventh transistor M7 is connected to the signal output terminal VO, the source thereof receives the high level signal VDD from the external circuit, and the drain thereof is connected to the source of the eighth transistor M8. The gate of the eighth transistor M8 and its drain receive a low level signal VSS from an external circuit. The ninth transistor 200834504 • The source of M9 is connected to the first output terminal VO1, the gate thereof receives the clock signal CK from the external circuit, and the drain thereof is connected to the drain of the seventh transistor M7. The gate of the tenth transistor receives the clock signal CK of the external circuit, the source of which is connected to the second output terminal V02, and the drain of which is connected to the signal output terminal VO. Please refer to FIG. 2 together, which is a working sequence diagram of the shift register unit 100. During the ΤΊ time, the output signal VS of the previous shift register unit is changed from a high level to a low level, and the inverted clock signal CK is changed from a low level to a high level to make the third The transistor M3 and the fourth transistor M4 are turned off, and the first clocked inverter circuit 110 is turned off. The clock signal CK is changed from a high level to a low level, so that the ninth transistor M9 and the tenth transistor M10 are turned on, and the second clock inverting circuit 130 is turned on, and the signal output terminal VO is turned on. The sixth level of the initial state is passed through the tenth transistor M10, and the sixth transistor M6 is turned off, and the low level of the output of the eighth transistor M8 is passed through the ninth transistor M9 to make the fifth transistor M5. Turning on, and then outputting the south level signal VDD of the source to the signal output terminal VO, the signal output terminal VO maintains a high level output. During the time T2, the inverted clock signal CK is changed from a high level to a low level, and the third transistor M3 and the fourth transistor M4 are turned on, thereby turning on the first clock inverting circuit 110. . When the clock signal CK is changed from a low level to a high level, the ninth transistor M9 and the tenth transistor M10 are turned off, and the second clocked inverter circuit 130 is turned off. When the input signal VS is changed from a high level to a low level, the first transistor M1 is turned on, and the source high level VDD is turned off by the third transistor M3 to the fifth transistor M5, and the The low level of the input signal VS is turned on by the fourth 9 200834504' transistor M4 to turn on the sixth transistor M6, so that the signal output terminal VO outputs a low level. When the inverted clock signal CK is changed from a low level to a rain level in the T 3 time, the third transistor M3 and the fourth transistor M4 are turned off, and the first clock inverting circuit 110 is further caused. disconnect. The clock signal CK is switched from a high level to a low level to turn on the ninth transistor M9 and the tenth transistor M10, thereby turning on the second clock inverting circuit 130. The low level of the signal output terminal VO turns on the seventh transistor M7, and the source of the spring high level is turned off by the ninth transistor M9 to the fifth transistor M5. At the same time, the low level of the signal output terminal VO is also turned on by the tenth transistor M10 to the sixth transistor M6, and the drain level of the sixth transistor M6 keeps the signal output terminal VO low level output. . During the period of T4, the inverted clock signal 0 transitions from a high level to a low level, and the third transistor M3 and the fourth transistor Μ4 are turned on, thereby causing the first clock inverting circuit 110 to be turned on. Turn on. The clock signal CK is changed from a low level to a high level to turn off the ninth transistor Μ9 and the tenth transistor Μ10, thereby turning off the second clock inverting circuit 120. The high level of the input signal VS is turned off by the fourth transistor Μ4, and the second low level of the second transistor M2 is turned on by the third transistor M3. The south level of the source is output to the signal output terminal VO, so that the output of the signal output terminal VO changes from a low level to a high level. The shift register unit 100 of the shift register has a large number of transistors, and the winding of each signal trace is complicated, so the circuit structure of the shift register is complicated. 200834504. The shift register can be applied to digital electronic products of liquid crystal display devices. For example, the = drive circuit of the liquid crystal display device requires the shift register to implement column scan or two-way = energy. However, the circuit structure of the shift register is complicated, and the capacity is disturbed. Therefore, (4) the shift register is used as the data sweeping = = the liquid crystal display device is easy to interfere with each other when performing column scan or line scan. .谷一唬间 [Summary content] In view of this, it is necessary. A simple circuit shifting register is actually provided. A liquid crystal display device that avoids signal interference is also a necessary type of shift register, which includes a plurality of shift register units, each shifting externally. The clock signal of the circuit, the inverted clock signal, the output signal of the pre-staged early 70, and the phase output signal control of the previous stage shift register unit. Each of the shift register units includes a pull-up circuit, a pull-up circuit, a first output circuit, a second output circuit, and an inverting power, and the pull-up circuit, the pull-down circuit, and the first output circuit are There is a common hill = point, the pull-up circuit provides a high level signal for the common node, and the lower node provides a low level signal. The first-round circuit outputs a clock signal under the control of the = common node, and the second output circuit is in the opposite direction. The low-level signal is output under the control of the clock signal, and the inverter circuit inverts the output signal of the first or second output circuit to output a liquid crystal display device, which includes a liquid crystal display panel data 11 200834504 driving circuit and a scan a driving circuit, wherein the data driving circuit provides a data signal for the liquid crystal collar, the scanning driving circuit provides a scanning signal for the liquid crystal display panel, and the data driving circuit and the scanning driving circuit respectively comprise a shift register for controlling Output timing of data signals and scan signals. The shift register includes a plurality of shift register units, and each shift register unit is a clock signal of an external circuit, an inverted clock signal, an output signal of the first stage shift register unit, and a shift of the previous stage. The inverting output signal of the memory unit is controlled, and each shift register unit comprises a pull-up circuit and a pull-down circuit 2: a first output circuit, a second output circuit and an inverting circuit. The pull-up circuit, the pull-down circuit and the first output circuit have a common node, and the pull-up circuit provides a high-level signal for the common node, and the pull-down circuit provides a low-level signal for the common point, the first The output circuit outputs a clock signal under the control of the common node, and the second output circuit outputs a low level signal under the control of the inverted clock signal, and the inverter circuit reverses the output signal of the first or second output b circuit Phase output. Compared with the Xianli technology, each shift register of the shift register of the present invention is composed of six transistors and has no complicated winding, so the circuit structure of the shift register is simple. This avoids unnecessary noise interference. At the same time, due to the small number of transistors, the probability of error in production is correspondingly low, which can increase the yield of the product. Since the circuit structure of the shift register is relatively simple, it is possible to avoid the occurrence of noise interference. When the sweeping (four) moving circuit and the moving circuit of the (4) shift register are subjected to line scanning or column scanning, the effect 0 between the output signals generates signal interference, thereby improving the display of the liquid crystal display device 12 200834504 [Embodiment] Please refer to FIG. 3 , which is a schematic structural diagram of a preferred embodiment of the shift register of the present invention. The shift register 20 includes a plurality of shift register units 200 having the same structure, and the plurality of shift register units 200 are sequentially connected in series. Each shift register unit 200 includes a clock signal input terminal TS, an inverted clock signal input terminal TSB, a first input terminal VIN1, a second input terminal VIN2, an output terminal VOUT, and an inverting output terminal VOUTB. A high level input terminal _VH and a low level input terminal VL. The clock signal input terminal TS of each shift register unit 200 receives the clock input signal CK of an external circuit (not shown), and the inverted clock signal input terminal TSB receives the inverted clock input signal of an external circuit (not shown). CKB, its high-level input terminal VH receives the high-level signal VDD of an external circuit (not shown), and its low-level input terminal VL receives the low-level signal VSS of an external circuit (not shown). The first input terminal VIN1 is electrically connected to the output terminal VOUT of the previous stage shift register unit 200, and the second input terminal VIN2 is electrically connected to the anti-rule phase output terminal VOUTB of the previous stage shift register unit 200, and the output terminal thereof is VOUT. The first input terminal VIN1 of the rear stage shift register unit 200 is electrically connected, and the inverting output terminal VOUTB is electrically connected to the second input terminal VIN2 of the subsequent stage shift register unit 200. That is, the output signal of the shift register unit 200 of the previous stage is the first input signal of the shift register unit 200 of the subsequent stage, and the inverted output signal of the shift register unit 200 of the previous stage is the shift register unit 200 of the subsequent stage. The second input signal, and each shift register unit 200 is simultaneously controlled by the external circuit clock signal CK, the inverted clock signal CKB, the high level signal VDD and the low level signal VSS. 13 200834504 " Please refer to FIG. 4 , which is a circuit diagram of the shift register unit of FIG. 3 . The shift register unit 200 includes a pull-up circuit 31, a pull-down circuit 32, a first output circuit 33, a second output circuit 34, a buffer 35, and an inverter 36. The buffer 35 The two inverters are serially connected, and are mainly used to maintain the output waveform of the shift temporary storage unit 200 to avoid distortion of the output waveform. The pull-up circuit 31, the pull-down circuit 32 and the first output circuit 33 have a common node P, and the pull-up circuit 31 provides a high level signal for the common node P, and the pull-down circuit 32 provides low power for the common node P. Pingxun No. 10. The pull-up circuit 31 is controlled by the first input terminal, and the pull-down circuit 32 is controlled by the second input terminal VIN2 and the common node P. The first output circuit 33 outputs a clock signal CK to the buffer 35 under the control of the common node P, and the second output circuit 34 outputs a low level signal VSS under the control of the inverted clock signal CKB. The buffer transmits the received clock signal CK or low level signal VSS to the output terminal VOUT. The inverter 36 inverts the signal of the output terminal VOUT and inputs it to the inverting output terminal VOUTB. 10 The pull-up circuit 31 includes a first transistor M1, the first transistor
Ml係NMOS型電晶體。該第一電晶體Ml的閘極電連接 該第一輸入端VIN1，其源極電連接該高電平輸入端VH， 其汲極電連接該公共節點P。 該下拉電路32包括一第二電晶體M2、一第三電晶體 M3及一第四電晶體M4，該第二、第三、第四電晶體M2、 M3、M4均係NMOS型電晶體。該第二電晶體M2的閘極 電連接該第二輸入端VIN2,其源極電連接該公共節點P， 其汲極電連接該第三電晶體M3的源極。該第三電晶體M3 14 200834504 的閘極電連接該第四電晶體Μ 4的源極’其没極電連接該 低電平輸入端VL。該第四電晶體Μ4的閘極電連接該公共 節點Ρ，其汲極電連接該反相時鐘訊號輸入端TSB。 該第一輸出電路33包括一第五電晶體Μ5，該第五電 晶體Μ5係NMOS型電晶體。該第五電晶體Μ5的閘極電 連接該公共節點Ρ，其源極電連接該時鐘訊號輸入端TS， 其汲極電連接該缓衝器35。 該第二輸出電路34包括一第六電晶體]^6，該第六電 籲晶體Μ6係NMOS型電晶體。該第六電晶體Μ6的閘極電 連接該反相時鐘訊號輸入端TSB，其源極電連接該緩衝 器，其汲極電連接該低電平輸入端VL。 請一併參閱圖5，其係圖3中移位暫存器20之時序示 意圖。用η表示某一級移位暫存單元200，則其前一級用 η-1表示。 在Τ1時間内，對於第η級移位暫存單元200，第一輸 入端VIN1接收第η-1級輸出訊號V01為高電平，則第一 鲁電晶體Ml導通，該公共節點Ρ被上拉為高電平。該第二 輸入端VIN2接收第η-1級反相輸出訊號Ϋ5Ϊ為低電平，則 該第二電晶體M2截止。因該公共節點Ρ為高電平，則第 五電晶體Μ5導通。此時該反相時鐘訊號為南電平’則第 六電晶體Μ 6導通。此時該時鐘訊號C Κ為低電平’故該 缓衝器35接收到的訊號為低電平，該輸出端VOUT的輸 出訊號V02為低電平。 在Τ2時間内，對於第η級移位暫存單元200，第一輸 入端VIN1接收第η-1級輸出訊號V01為低電平，則第一 15 200834504 — 電晶體Ml截止，該公共節點P繼續保持為高電平。第二 輸入端VIN2接收第n-1級反相輸出訊號Ϋδϊ為高電平，則 該第二電晶體M2導通。因該公共節點Ρ為高電平，則第 五電晶體Μ5導通。因該公共節點Ρ為高電平，則第四電 晶體Μ4導通，反相時鐘訊號CKB通過該第四電晶體Μ4 控制該第三電晶體M3，此時該反相時鐘訊號CKB為低電 平，則第三電晶體M3截止，該第六電晶體Μ6也截止。 時鐘訊號CK分別通過該第五電晶體Μ5輸入至該缓衝器 _ 35，此時該時鐘訊號CK為高電平，故輸出端VOUT的輸 出訊號V02為高電平。 在Τ3時間内，對於第η級移位暫存單元200，第一輸 入端VIN1接收第η-1級輸出訊號V01為低電平，則第一 電晶體Ml截止，該公共節點Ρ繼續保持為高電平。第二 輸入端VIN2接收弟η -1級反相輸出訊號V01為焉電平’則 該第二電晶體M2導通。因該公共節點Ρ為高電平，則第 四電晶體Μ4導通，反相時鐘訊號CKB通過該第四電晶體 零Μ4控制該第三電晶體M3，此時該反相時鐘訊號CKB為 高電平，則第三電晶體M3導通，公共節點Ρ被下拉為低 電平，則第五電晶體Μ5截止。因爲此時該反相時鐘訊號 CKB為高電平，則第六電晶體Μ6導通，低電平訊號通過 該第六電晶體Μ6輸入至該緩衝器35，故輸出端VOUT的 輸出訊號V02為低電平。 在Τ4時間内，對於第η級移位暫存單元200，第一輸 入端VIN1接收第η-1級輸出訊號V01為低電平，則第一 電晶體Ml截止，該公共節點Ρ繼續保持為低電平，則第 16 200834504 ，四電晶體M4截止、第五電晶體M5截止。此時該反相時 鐘訊號CKB為低電平，則第六電晶體M6截止，故輸出端 VOUT的輸出訊號V02保持為低電平。 與先前技術相比，本發明移位暫存器20的每一移位暫 存單元200由六顆電晶體構成，且沒有複雜的繞線，故該 移位暫存器20的電路結構簡單，從而可避免不必要雜訊干 擾發生。同時，因電晶體數量較少，在生産中的錯誤機率 也相應較低，從而可以提高產品的良率。 ® 每一移位暫存單元200的反相器36也可用一反相電路 代替。 該移位暫存器20可用於液晶顯示裝置以及其他數位 電子產品中。請參閱圖6,其係一採用上述移位暫存器之 液晶顯示裝置之結構示意圖。該液晶顯示裝置2包括一液 晶顯不面板21、*^貢料驅動電路2 2及*^掃描驅動電路2 3 ^ 該資料驅動電路22及該掃描驅動電路23分別藉由複數數 據線與複數掃描線與該液晶顯示面板21連接。該液晶顯示 m 面板21包括一上基板（圖未示）、一下基板（圖未示）及一夾 持於上基板與下基板間之液晶層（圖未示），且於該下基板 鄰近液晶層一側設置有一用於控制液晶分子扭轉狀態之薄 膜電晶體陣列（圖未示）。該資料驅動電路22及該掃描驅動 電路23分別包括一上述移位暫存器20。該掃描驅動電路 23在該移位暫存器20的控制下依序輸出高電平訊號至該 複數掃描線，以逐列控制該薄膜電晶體矩陣之導通與關斷 狀態。該資料驅動電路22依序輸出資料訊號至該液晶顯示 面板21，以控制其顯示畫面變化。該掃描驅動電路23及 17 200834504 該二料驅動電路22皆利用該移位暫存器2〇控制掃描訊號 與資料訊號之輸出時序，從而實現晝面顯示。 、由於該移位暫存器20的電路結構較簡單，因此可避免 不必要雜訊干擾發生。使用該移位暫存器2〇之掃描驅動電 及資料驅動電路22在進行行掃描或列掃描時，其各 =訊號間亦不會產生訊號干擾，從而提高了該液晶顯示 衣置2的顯示效果。Ml is an NMOS type transistor. The gate of the first transistor M1 is electrically connected to the first input terminal VIN1, the source thereof is electrically connected to the high-level input terminal VH, and the drain is electrically connected to the common node P. The pull-down circuit 32 includes a second transistor M2, a third transistor M3, and a fourth transistor M4. The second, third, and fourth transistors M2, M3, and M4 are all NMOS type transistors. The gate of the second transistor M2 is electrically connected to the second input terminal VIN2, the source thereof is electrically connected to the common node P, and the drain thereof is electrically connected to the source of the third transistor M3. The gate of the third transistor M3 14 200834504 is electrically connected to the source of the fourth transistor ’ 4 which is not electrically connected to the low level input terminal VL. The gate of the fourth transistor 电4 is electrically connected to the common node 汲, and the drain is electrically connected to the inverted clock signal input terminal TSB. The first output circuit 33 includes a fifth transistor Μ5, which is an NMOS type transistor. The gate of the fifth transistor Μ5 is electrically connected to the common node Ρ, and its source is electrically connected to the clock signal input terminal TS, and its drain is electrically connected to the buffer 35. The second output circuit 34 includes a sixth transistor, which is an NMOS type transistor. The gate of the sixth transistor 电6 is electrically connected to the inverted clock signal input terminal TSB, the source thereof is electrically connected to the buffer, and the drain is electrically connected to the low level input terminal VL. Please refer to FIG. 5 together, which is a timing diagram of the shift register 20 in FIG. When a certain stage shift register unit 200 is represented by η, the previous stage is represented by η-1. During the first time, for the nth stage shift register unit 200, the first input terminal VIN1 receives the n-1th stage output signal V01 to be at a high level, then the first Lu crystal M1 is turned on, and the common node is turned on. Pulled high. The second input terminal VIN2 receives the n-1th inverted output signal Ϋ5Ϊ to be low, and the second transistor M2 is turned off. Since the common node is high, the fifth transistor Μ5 is turned on. At this time, the inverted clock signal is at the south level, and the sixth transistor Μ 6 is turned on. At this time, the clock signal C Κ is low level ′ so that the signal received by the buffer 35 is low level, and the output signal V02 of the output terminal VOUT is low level. In the Τ2 time, for the nth stage shift register unit 200, the first input terminal VIN1 receives the n-1th stage output signal V01 to be low level, then the first 15 200834504 - the transistor M1 is turned off, the common node P Continue to stay high. The second input terminal VIN2 receives the n-1th inverted output signal Ϋδϊ to be at a high level, and the second transistor M2 is turned on. Since the common node is high, the fifth transistor Μ5 is turned on. Because the common node is high, the fourth transistor Μ4 is turned on, and the inverted clock signal CKB controls the third transistor M3 through the fourth transistor ,4, and the inverted clock signal CKB is at a low level. Then, the third transistor M3 is turned off, and the sixth transistor Μ6 is also turned off. The clock signal CK is input to the buffer _35 through the fifth transistor Μ5. At this time, the clock signal CK is at a high level, so the output signal V02 of the output terminal VOUT is at a high level. In the Τ3 time, for the nth stage shift register unit 200, the first input terminal VIN1 receives the n-1th stage output signal V01 to be low level, then the first transistor M1 is turned off, and the common node Ρ continues to remain as High level. The second input terminal VIN2 receives the η -1 stage inverted output signal V01 at the 焉 level ', and the second transistor M2 is turned on. Because the common node is high, the fourth transistor Μ4 is turned on, and the inverted clock signal CKB controls the third transistor M3 through the fourth transistor Μ4, and the inverted clock signal CKB is high. If the third transistor M3 is turned on and the common node Ρ is pulled down to the low level, the fifth transistor Μ5 is turned off. Because the inverted clock signal CKB is at a high level, the sixth transistor Μ6 is turned on, and the low level signal is input to the buffer 35 through the sixth transistor Μ6, so the output signal V02 of the output terminal VOUT is low. Level. In the Τ4 time, for the nth stage shift register unit 200, the first input terminal VIN1 receives the n-1th stage output signal V01 to be low level, then the first transistor M1 is turned off, and the common node Ρ continues to remain as Low level, then 16th 200834504, the fourth transistor M4 is cut off, and the fifth transistor M5 is turned off. At this time, the inverted clock signal CKB is at a low level, and the sixth transistor M6 is turned off, so that the output signal V02 of the output terminal VOUT is kept at a low level. Compared with the prior art, each shift register unit 200 of the shift register 20 of the present invention is composed of six transistors, and has no complicated winding, so the circuit structure of the shift register 20 is simple. This avoids unnecessary noise interference. At the same time, due to the small number of transistors, the probability of error in production is also relatively low, which can improve the yield of the product. The inverter 36 of each shift register unit 200 can also be replaced by an inverter circuit. The shift register 20 can be used in liquid crystal display devices as well as other digital electronic products. Please refer to FIG. 6, which is a schematic structural diagram of a liquid crystal display device using the above shift register. The liquid crystal display device 2 includes a liquid crystal display panel 21, a tributary drive circuit 2 2, and a scan drive circuit 2 3 . The data drive circuit 22 and the scan drive circuit 23 respectively perform a plurality of data lines and a plurality of scans. A wire is connected to the liquid crystal display panel 21. The liquid crystal display m panel 21 includes an upper substrate (not shown), a lower substrate (not shown), and a liquid crystal layer (not shown) sandwiched between the upper substrate and the lower substrate, and the liquid crystal layer adjacent to the lower substrate A thin film transistor array (not shown) for controlling the twist state of the liquid crystal molecules is disposed on one side of the layer. The data driving circuit 22 and the scan driving circuit 23 respectively include a shift register 20 as described above. The scan driving circuit 23 sequentially outputs a high level signal to the complex scan line under the control of the shift register 20 to control the on and off states of the thin film transistor matrix column by column. The data driving circuit 22 sequentially outputs data signals to the liquid crystal display panel 21 to control display screen changes. The scan driving circuit 23 and 17 200834504 both use the shift register 2 to control the output timing of the scan signal and the data signal, thereby realizing the face display. Since the circuit structure of the shift register 20 is relatively simple, unnecessary noise interference can be avoided. When the scan driving power and the data driving circuit 22 of the shift register 2 are used for row scanning or column scanning, signal interference is not generated between each signal, thereby improving the display of the liquid crystal display device 2. effect.
，上所述’本創作確已符合發明|利之要件，麦依法 ★出申請專利。惟’以上所述者僅係本發明之較佳實施方 i枯ί發明之範圍並不以上述實施方式爲限，舉凡熟習本 之人士援依本發明之精神所作之等 白應涵蓋於以下申請專利範圍内。 史 L圖式簡單說明】 種先前技術移位暫存單元之電路示意圖。 圖 ，圖！中移位暫存單元所在移位暫存器之時序示音 圖4=Γ月移位暫存ί較佳實施方式之結構示意圖二 了之移位暫存單元之電路示意圖。 二5係圖1中移位暫存器之時序示意圖。 Θ 6係本發明液晶顯示I置較佳實施方^之結構示意圖 【主要元件符號說明】 18 200834504 ^ 液晶顯示裝置 2 移位暫存器 20 液晶顯不面板 21 貧料驅動電路 22 掃描驅動電路 23 上拉電路 31 下拉電路 32 第一輸出電路 33 第二輸出電路 34 缓衝器 35 反相器 36 移位暫存單元 200 19, described above, 'this creation has indeed met the invention|profit element, Mai law ★ apply for a patent. However, the above description is only for the preferred embodiment of the present invention. The scope of the invention is not limited to the above embodiments, and the equivalents of those skilled in the art in light of the spirit of the present invention should be included in the following application. Within the scope of the patent. A brief description of the circuit of the prior art shift register unit. Figure, figure! The timing of the shift register of the medium shift register unit is shown in Fig. 4 = the monthly shift temporary storage ί is a schematic diagram of the structure of the preferred embodiment. Figure 2 is a timing diagram of the shift register in Figure 1. Θ 6 is a schematic diagram of the structure of the liquid crystal display I of the present invention. [Main component symbol description] 18 200834504 ^ Liquid crystal display device 2 Shift register 20 Liquid crystal display panel 21 Poor driving circuit 22 Scan driving circuit 23 Pull-up circuit 31 pull-down circuit 32 first output circuit 33 second output circuit 34 buffer 35 inverter 36 shift register unit 200 19