CN114005398B - Gate driving circuit - Google Patents
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- CN114005398B CN114005398B CN202111336796.4A CN202111336796A CN114005398B CN 114005398 B CN114005398 B CN 114005398B CN 202111336796 A CN202111336796 A CN 202111336796A CN 114005398 B CN114005398 B CN 114005398B
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- 230000002457 bidirectional effect Effects 0.000 claims abstract description 23
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- 229910003437 indium oxide Inorganic materials 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
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- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
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- JAONJTDQXUSBGG-UHFFFAOYSA-N dialuminum;dizinc;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Al+3].[Al+3].[Zn+2].[Zn+2] JAONJTDQXUSBGG-UHFFFAOYSA-N 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
Description
技术领域Technical field
本发明为一种利用双向传输电路、第一电路、第二电路和第三电路产生显示面板所需的扫描信号且实现双向低频操作的栅极驱动电路。The invention is a gate drive circuit that utilizes a bidirectional transmission circuit, a first circuit, a second circuit and a third circuit to generate scanning signals required by a display panel and realize bidirectional low-frequency operation.
背景技术Background technique
近来，栅极驱动电路(Gate Drive On Array,GOA)技术兴起，将面板左右两侧的栅极驱动电路设计制作于玻璃基板上，可大幅减少面板驱动器的使用数量，达到超窄边框设计。栅极驱动电路目前已应用于手机、电脑、平板或大型显示器，显然栅极驱动电路技术已成为主流趋势。Recently, gate drive circuit (Gate Drive On Array, GOA) technology has emerged. The gate drive circuits on the left and right sides of the panel are designed and manufactured on the glass substrate, which can significantly reduce the number of panel drivers used and achieve ultra-narrow frame design. Gate drive circuits are currently used in mobile phones, computers, tablets or large displays. It is obvious that gate drive circuit technology has become a mainstream trend.
根据不同显示面板的数据线驱动器的位置，栅极驱动电路需要顺向或反向输出，现有的栅极驱动电路若需同时具有双向输出的功能，则需设计额外的电路去达成双向输出的功能，增加电路布局所需的面积。According to the position of the data line driver of different display panels, the gate drive circuit needs to output in forward or reverse direction. If the existing gate drive circuit needs to have the function of bidirectional output at the same time, additional circuits need to be designed to achieve bidirectional output. function, increasing the area required for circuit layout.
综观前所述，本发明的发明者思索并设计一种栅极驱动电路，以期针对现有技术的缺失加以改善，进而增进产业上的实施利用。In summary, the inventor of the present invention thought about and designed a gate driving circuit in order to improve the shortcomings of the existing technology and thereby enhance industrial implementation and utilization.
发明内容Contents of the invention
有鉴于上述现有技术的问题，本发明的目的在于提供一种栅极驱动电路，通过双向传输电路、第一电路、第二电路和第三电路，提供双向低频操作的功能，无须额外电路辅助即能达成双向低频操作。In view of the above-mentioned problems of the prior art, the object of the present invention is to provide a gate drive circuit that provides a bidirectional low-frequency operation function through a bidirectional transmission circuit, a first circuit, a second circuit and a third circuit without the need for additional circuit assistance. That is, bidirectional low-frequency operation can be achieved.
基于上述目的，本发明提供一种栅极驱动电路，其包括双向传输电路、第一电路、第二电路和第三电路。双向传输电路包括第一晶体管和第二晶体管，第一晶体管的控制端耦接前一级第一信号线，第二晶体管的控制端耦接后一级第一信号线，第一晶体管和第二晶体管的第一端分别耦接第一传输信号线和第二传输信号线，第一晶体管和第二晶体管的第二端耦接第一节点。第一电路耦接第一节点和输出端，第一电路耦接第一时脉线、本级第一信号线、本级第二信号线和电压线。第二电路耦接输出端，第二电路耦接第一时脉线、第二时脉线、本级第一信号线及电压线。第三电路耦接第一节点及第二节点，第三电路耦接第一时脉线、第二时脉线、本级第二信号线及电压线。Based on the above objectives, the present invention provides a gate driving circuit, which includes a bidirectional transmission circuit, a first circuit, a second circuit and a third circuit. The bidirectional transmission circuit includes a first transistor and a second transistor. The control terminal of the first transistor is coupled to the first signal line of the previous stage. The control terminal of the second transistor is coupled to the first signal line of the subsequent stage. The first transistor and the second The first end of the transistor is coupled to the first transmission signal line and the second transmission signal line respectively, and the second end of the first transistor and the second transistor is coupled to the first node. The first circuit is coupled to the first node and the output terminal, and the first circuit is coupled to the first clock line, the first signal line of this stage, the second signal line of this stage and the voltage line. The second circuit is coupled to the output terminal, and the second circuit is coupled to the first clock line, the second clock line, the first signal line and the voltage line of this stage. The third circuit is coupled to the first node and the second node, and the third circuit is coupled to the first clock line, the second clock line, the second signal line and the voltage line of this stage.
在本发明的实施例中，第一电路包括第三晶体管、第四晶体管、第五晶体管以及第一电容，电压线包括第一电压线、第二电压线，第三晶体管的控制端耦接本级第二信号线，第三晶体管的第一端耦接第一电压线，第三晶体管的第二端耦接第一节点，第四晶体管的第一端耦接第一时脉线，第四晶体管的控制端耦接第一节点，第四晶体管的第二端耦接第二节点，第一电容设置于第二节点和第一节点之间，第二节点耦接本级第一信号线，第五晶体管的第一端耦接第二电压线，第五晶体管的控制端耦接第二节点，第五晶体管的第二端耦接输出端。In the embodiment of the present invention, the first circuit includes a third transistor, a fourth transistor, a fifth transistor and a first capacitor, the voltage line includes a first voltage line and a second voltage line, and the control end of the third transistor is coupled to the The first terminal of the third transistor is coupled to the first voltage line, the second terminal of the third transistor is coupled to the first node, the first terminal of the fourth transistor is coupled to the first clock line, and the first terminal of the fourth transistor is coupled to the first clock line. The control terminal of the transistor is coupled to the first node, the second terminal of the fourth transistor is coupled to the second node, the first capacitor is disposed between the second node and the first node, and the second node is coupled to the first signal line of this stage, The first terminal of the fifth transistor is coupled to the second voltage line, the control terminal of the fifth transistor is coupled to the second node, and the second terminal of the fifth transistor is coupled to the output terminal.
在本发明的实施例中，第二电路包括第六晶体管、第七晶体管、第八晶体管、第九晶体管以及第二电容，第六晶体管的第一端和控制端互相耦接，第六晶体管的第二端耦接第三节点，第六晶体管的第一端和第七晶体管的第一端耦接第四节点，第七晶体管的控制端耦接第二时脉线，第七晶体管的第二端耦接第二电压线，第二电容的一端耦接第四节点，第二电容的另一端耦接第一时脉线，第八晶体管的第一端耦接第一电压线，第八晶体管的控制端耦接本级第一信号线，第八晶体管的第二端耦接第三节点，第九晶体管的第一端耦接输出端，第九晶体管的控制端耦接第三节点，第九晶体管的第二端耦接第三时脉线。In an embodiment of the present invention, the second circuit includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a second capacitor. The first terminal and the control terminal of the sixth transistor are coupled to each other. The second terminal is coupled to the third node, the first terminal of the sixth transistor and the first terminal of the seventh transistor are coupled to the fourth node, the control terminal of the seventh transistor is coupled to the second clock line, and the second terminal of the seventh transistor is coupled to the fourth node. The terminal is coupled to the second voltage line, one terminal of the second capacitor is coupled to the fourth node, the other terminal of the second capacitor is coupled to the first clock line, the first terminal of the eighth transistor is coupled to the first voltage line, and the eighth transistor The control end of the ninth transistor is coupled to the first signal line of this stage, the second end of the eighth transistor is coupled to the third node, the first end of the ninth transistor is coupled to the output end, the control end of the ninth transistor is coupled to the third node, The second terminal of the nine transistors is coupled to the third clock line.
在本发明的实施例中，第三电路包括第十晶体管、第十一晶体管、第十二晶体管以及第三电容，第十晶体管的第一端耦接第二节点，第十晶体管的控制端耦接第二时脉线，第十晶体管的第二端耦接第一电压线，第十一晶体管的第一端耦接第二节点，第十一晶体管的第二端耦接第一电压线，第十一晶体管的控制端耦接本级第二信号线，第十二晶体管的第一端耦接本级第二信号线，第十二晶体管的控制端耦接第一节点，第十二晶体管的第二端耦接第一电压线，第三电容的一端耦接本级第二信号线，第三电容的另一端耦接第一时脉线。In the embodiment of the present invention, the third circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor and a third capacitor. The first terminal of the tenth transistor is coupled to the second node, and the control terminal of the tenth transistor is coupled to the second node. connected to the second clock line, the second terminal of the tenth transistor is coupled to the first voltage line, the first terminal of the eleventh transistor is coupled to the second node, and the second terminal of the eleventh transistor is coupled to the first voltage line, The control terminal of the eleventh transistor is coupled to the second signal line of this stage, the first terminal of the twelfth transistor is coupled to the second signal line of this stage, the control terminal of the twelfth transistor is coupled to the first node, the twelfth transistor The second end of the third capacitor is coupled to the first voltage line, one end of the third capacitor is coupled to the second signal line of this stage, and the other end of the third capacitor is coupled to the first clock line.
在本发明的实施例中，第一晶体管、第二晶体管、第三晶体管、第四晶体管、第六晶体管、第七晶体管、第八晶体管、第十晶体管、第十一晶体管和第十二晶体管N型晶体管，第五晶体管和第九晶体管为P型晶体管。In embodiments of the present invention, the first, second, third, fourth, sixth, seventh, eighth, tenth, eleventh and twelfth transistors N type transistor, the fifth transistor and the ninth transistor are P-type transistors.
在本发明的实施例中，在第一时间，前一级第一信号线传输前一级第一信号使第一晶体管导通，后一级第一信号线传输后一级第一信号线使第二晶体管关闭，本级第一信号线传输本级第一信号使第八晶体管关闭，第三时脉信号线传输第三时脉信号，第九晶体管关闭，本级第二信号线传输本级第二信号使第三晶体管和第十一晶体管关闭，第二时脉信号线传输第二时脉信号使第七晶体管和第十晶体管导通，第三节点的电压大于第四节点的电压，使第六晶体管关闭，第一节点的电压使第四晶体管导通，本级第一信号使第五晶体管导通，第一节点的电压使第十二晶体管导通。In the embodiment of the present invention, at the first time, the first signal line of the previous stage transmits the first signal of the previous stage to turn on the first transistor, and the first signal line of the subsequent stage transmits the first signal line of the subsequent stage to turn on the first transistor. The second transistor is turned off, the first signal line of this level transmits the first signal of this level, causing the eighth transistor to turn off, the third clock signal line transmits the third clock signal, the ninth transistor is turned off, and the second signal line of this level transmits this level The second signal turns off the third transistor and the eleventh transistor. The second clock signal line transmits the second clock signal to turn on the seventh transistor and the tenth transistor. The voltage of the third node is greater than the voltage of the fourth node, so that The sixth transistor is turned off, the voltage of the first node turns on the fourth transistor, the first signal of this stage turns on the fifth transistor, and the voltage of the first node turns on the twelfth transistor.
在本发明的实施例中，在第二时间，前一级第一信号使第一晶体管关闭，后一级第一信号使第二晶体管关闭，本级第一信号使第八晶体管导通，第九晶体管导通，本级第二信号使第三晶体管和第十一晶体管关闭，第二时脉信号使第七晶体管和第十晶体管关闭，第三节点的电压小于第四节点的电压，使第六晶体管导通，第一节点的电压使第四晶体管导通，第五晶体管关闭，第一节点的电压使第十二晶体管导通。In the embodiment of the present invention, at the second time, the first signal of the previous stage turns off the first transistor, the first signal of the next stage turns off the second transistor, the first signal of this stage turns on the eighth transistor, and the first signal of the next stage turns on the eighth transistor. The nine transistors are turned on, the second signal of this stage turns off the third transistor and the eleventh transistor, the second clock signal turns off the seventh transistor and the tenth transistor, the voltage of the third node is less than the voltage of the fourth node, so that the The six transistors are turned on, the voltage at the first node turns on the fourth transistor, the fifth transistor is turned off, and the voltage at the first node turns on the twelfth transistor.
在本发明的实施例中，在第三时间，前一级第一信号使第一晶体管关闭，后一级第一信号使第二晶体管导通，本级第一信号使第八晶体管关闭，第三时脉信号使第九晶体管导通，本级第二信号使第三晶体管和第十一晶体管关闭，第二时脉信号使第七晶体管和第十晶体管导通，第三节点的电压小于第四节点的电压，使第六晶体管导通，第一节点的电压使第四晶体管关闭，本级第一信号使第五晶体管导通，第一节点的电压和第一电压相等，使第十二晶体管关闭。In the embodiment of the present invention, at the third time, the first signal of the previous stage turns off the first transistor, the first signal of the next stage turns on the second transistor, the first signal of this stage turns off the eighth transistor, and the first signal of the current stage turns off the eighth transistor. The third clock signal turns on the ninth transistor, the second signal of this stage turns off the third transistor and the eleventh transistor, the second clock signal turns on the seventh transistor and the tenth transistor, and the voltage of the third node is less than the The voltage of the fourth node turns on the sixth transistor, the voltage of the first node turns off the fourth transistor, the first signal of this stage turns on the fifth transistor, and the voltage of the first node is equal to the first voltage, making the twelfth transistor turn on. The transistor is off.
在本发明的实施例中，在第四时间，前一级第一信号使第一晶体管关闭，后一级第一信号使第二晶体管关闭，本级第一信号使第八晶体管关闭，第九晶体管关闭，本级第二信号使第三晶体管和第十一晶体管导通，第二时脉信号使第七晶体管和第十晶体管关闭，第三节点的电压小于第四节点的电压，使第六晶体管导通，第一节点的电压小于第二节点的电压，使第四晶体管关闭，本级第一信号使第五晶体管导通，第一节点的电压和第一电压相等，使第十二晶体管关闭。In the embodiment of the present invention, at the fourth time, the first signal of the previous stage turns off the first transistor, the first signal of the next stage turns off the second transistor, the first signal of this stage turns off the eighth transistor, and the ninth transistor turns off. The transistor is turned off, the second signal of this stage turns on the third transistor and the eleventh transistor, the second clock signal turns off the seventh transistor and the tenth transistor, the voltage of the third node is less than the voltage of the fourth node, causing the sixth The transistor is turned on, the voltage of the first node is less than the voltage of the second node, turning the fourth transistor off, the first signal of this stage turns on the fifth transistor, the voltage of the first node is equal to the first voltage, turning the twelfth transistor closure.
在本发明的实施例中，第一电路包括第三晶体管、第四晶体管、第五晶体管以及第一电容，电压线包括第一电压线、第二电压线以及第三电压线，第三晶体管的控制端耦接本级第二信号线，第三晶体管的第一端耦接第一电压线，第三晶体管的第二端耦接第一节点，第四晶体管的第一端耦接第一时脉线，第四晶体管的控制端耦接第一节点，第四晶体管的第二端耦接第二节点，第一电容位于第二节点和第一节点之间，第二节点耦接本级第一信号线，第五晶体管的第一端耦接第三电压线，第五晶体管的控制端耦接第一节点，第五晶体管的第二端耦接输出端。In an embodiment of the present invention, the first circuit includes a third transistor, a fourth transistor, a fifth transistor and a first capacitor, the voltage line includes a first voltage line, a second voltage line and a third voltage line, and the third transistor The control terminal is coupled to the second signal line of this stage, the first terminal of the third transistor is coupled to the first voltage line, the second terminal of the third transistor is coupled to the first node, and the first terminal of the fourth transistor is coupled to the first time pulse line, the control terminal of the fourth transistor is coupled to the first node, the second terminal of the fourth transistor is coupled to the second node, the first capacitor is located between the second node and the first node, and the second node is coupled to the second node of this stage. A signal line, the first terminal of the fifth transistor is coupled to the third voltage line, the control terminal of the fifth transistor is coupled to the first node, and the second terminal of the fifth transistor is coupled to the output terminal.
在本发明的实施例中，第二电路包括第六晶体管、第七晶体管、第八晶体管、第九晶体管以及第二电容，第六晶体管的第一端耦接第三电压线，第六晶体管的控制端耦接本级第一信号线，第六晶体管的第二端耦接第三节点，第七晶体管的第一端耦接第二电压线，第七晶体管的控制端耦接第二时脉线，第七晶体管的第二端耦接第三节点，第二电容的一端耦接第三节点，第二电容的另一端耦接第一时脉线，第八晶体管的第一端耦接输出端，第八晶体管的控制端耦接第三节点，第八晶体管的第二端耦接第一时脉线，第九晶体管的第一端耦接输出端，第九晶体管的控制端耦接第二时脉线，第九晶体管的第二端耦接第三电压线。In the embodiment of the present invention, the second circuit includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a second capacitor. The first end of the sixth transistor is coupled to the third voltage line, and the first end of the sixth transistor is coupled to the third voltage line. The control terminal is coupled to the first signal line of this stage, the second terminal of the sixth transistor is coupled to the third node, the first terminal of the seventh transistor is coupled to the second voltage line, and the control terminal of the seventh transistor is coupled to the second clock line, the second end of the seventh transistor is coupled to the third node, one end of the second capacitor is coupled to the third node, the other end of the second capacitor is coupled to the first clock line, and the first end of the eighth transistor is coupled to the output terminal, the control terminal of the eighth transistor is coupled to the third node, the second terminal of the eighth transistor is coupled to the first clock line, the first terminal of the ninth transistor is coupled to the output terminal, and the control terminal of the ninth transistor is coupled to the third node. The second clock line and the second terminal of the ninth transistor are coupled to the third voltage line.
在本发明的实施例中，第三电路包括第十晶体管、第十一晶体管、第十二晶体管以及第三电容，第十晶体管的第一端耦接第二节点，第十晶体管的控制端耦接第二时脉线，第十晶体管的第二端耦接第一电压线，第十一晶体管的第一端耦接第二节点，第十一晶体管的第二端耦接第一电压线，第十一晶体管的控制端耦接本级第二信号线，第十二晶体管的第一端耦接本级第二信号线，第十二晶体管的控制端耦接第一节点，第十二晶体管的第二端耦接第一电压线，第三电容的一端耦接本级第二信号线，第三电容的另一端耦接第一时脉线。In the embodiment of the present invention, the third circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor and a third capacitor. The first terminal of the tenth transistor is coupled to the second node, and the control terminal of the tenth transistor is coupled to the second node. connected to the second clock line, the second terminal of the tenth transistor is coupled to the first voltage line, the first terminal of the eleventh transistor is coupled to the second node, and the second terminal of the eleventh transistor is coupled to the first voltage line, The control terminal of the eleventh transistor is coupled to the second signal line of this stage, the first terminal of the twelfth transistor is coupled to the second signal line of this stage, the control terminal of the twelfth transistor is coupled to the first node, the twelfth transistor The second end of the third capacitor is coupled to the first voltage line, one end of the third capacitor is coupled to the second signal line of this stage, and the other end of the third capacitor is coupled to the first clock line.
在本发明的实施例中，第一晶体管、第二晶体管、第三晶体管、第四晶体管、第六晶体管、第七晶体管、第九晶体管、第十晶体管、第十一晶体管和第十二晶体管为N型晶体管，第五晶体管和第八晶体管为P型晶体管。In an embodiment of the present invention, the first, second, third, fourth, sixth, seventh, ninth, tenth, eleventh and twelfth transistors are N-type transistors, the fifth transistor and the eighth transistor are P-type transistors.
在本发明的实施例中，在第一时间，前一级第一信号线传输前一级第一信号使第一晶体管导通，后一级第一信号传输线传输后一级第一信号使第二晶体管关闭，本级第一信号线传输本级第一信号使第六晶体管关闭，本级第二信号线传输本级第二信号使第三晶体管和第十一晶体管关闭，第一节点的电压使第四晶体管导通，第五晶体管关闭，第二时脉信号线传输第二时脉信号使第七晶体管、第九晶体管和第十晶体管导通，第八晶体管关闭，第一节点的电压使第十二晶体管导通。In the embodiment of the present invention, at the first time, the first signal line of the previous stage transmits the first signal of the previous stage to turn on the first transistor, and the first signal transmission line of the subsequent stage transmits the first signal of the latter stage to turn on the first transistor. The second transistor is turned off. The first signal line of this level transmits the first signal of this level to turn off the sixth transistor. The second signal line of this level transmits the second signal of this level so that the third transistor and the eleventh transistor are turned off. The voltage of the first node The fourth transistor is turned on, the fifth transistor is turned off, the second clock signal line transmits the second clock signal, the seventh transistor, the ninth transistor and the tenth transistor are turned on, the eighth transistor is turned off, and the voltage of the first node causes The twelfth transistor is turned on.
在本发明的实施例中，在第二时间，前一级第一信号使第一晶体管关闭，后一级第一信号使第二晶体管关闭，本级第一信号使第六晶体管导通，本级第二信号使第三晶体管和第十一晶体管关闭，第一节点的电压使第四晶体管导通，第五晶体管关闭，第二时脉信号使第七晶体管、第九晶体管和第十晶体管关闭，第八晶体管导通，第一节点的电压使第十二晶体管导通。In the embodiment of the present invention, at the second time, the first signal of the previous stage turns off the first transistor, the first signal of the next stage turns off the second transistor, the first signal of this stage turns on the sixth transistor, and the first signal of this stage turns on the sixth transistor. The second signal turns off the third transistor and the eleventh transistor. The voltage of the first node turns on the fourth transistor and turns off the fifth transistor. The second clock signal turns off the seventh, ninth and tenth transistors. , the eighth transistor is turned on, and the voltage of the first node turns on the twelfth transistor.
在本发明的实施例中，在第三时间，前一级第一信号使第一晶体管关闭，后一级第一信号使第二晶体管导通，本级第一信号使第六晶体管关闭，本级第二信号使第三晶体管和第十一晶体管关闭，第四晶体管关闭，第五晶体管导通，第二时脉信号使第七晶体管、第九晶体管和第十晶体管导通，第八晶体管关闭，使第十二晶体管关闭。In the embodiment of the present invention, at the third time, the first signal of the previous stage turns off the first transistor, the first signal of the next stage turns on the second transistor, and the first signal of this stage turns off the sixth transistor. The second signal turns off the third transistor and the eleventh transistor, turns off the fourth transistor, and turns on the fifth transistor. The second clock signal turns on the seventh, ninth, and tenth transistors, and turns off the eighth transistor. , causing the twelfth transistor to turn off.
在本发明的实施例中，在第四时间，前一级第一信号使第一晶体管关闭，后一级第一信号使第二晶体管关闭，本级第一信号使第六晶体管关闭，本级第二信号使第三晶体管和第十一晶体管导通，第四晶体管关闭，第一节点的电压使第五晶体管导通，第二时脉信号使第七晶体管、第九晶体管和第十晶体管关闭，第八晶体管关闭，第一节点的电压为第一电压，使第十二晶体管关闭。In the embodiment of the present invention, at the fourth time, the first signal of the previous stage turns off the first transistor, the first signal of the next stage turns off the second transistor, the first signal of this stage turns off the sixth transistor, and the first signal of this stage turns off the sixth transistor. The second signal turns on the third transistor and the eleventh transistor, turns off the fourth transistor, the voltage of the first node turns on the fifth transistor, and the second clock signal turns off the seventh, ninth and tenth transistors. , the eighth transistor is turned off, and the voltage of the first node is the first voltage, causing the twelfth transistor to turn off.
承上所述，本发明的栅极驱动电路，提供双向低频操作的功能及显示面板所需的扫描信号，无须额外电路辅助即能达成双向低频操作。As mentioned above, the gate drive circuit of the present invention provides the function of bidirectional low-frequency operation and the scanning signal required by the display panel, and can achieve bidirectional low-frequency operation without the need for additional circuit assistance.
附图说明Description of the drawings
图1为本发明的栅极驱动电路的第一实施例的配置图。FIG. 1 is a configuration diagram of the first embodiment of the gate driving circuit of the present invention.
图2A为本发明的栅极驱动电路的第一实施例于第一时间的示意图。FIG. 2A is a schematic diagram of the first embodiment of the gate driving circuit of the present invention at a first time.
图2B为本发明的栅极驱动电路的第一实施例于第一时间的信号波形图。FIG. 2B is a signal waveform diagram at the first time of the first embodiment of the gate driving circuit of the present invention.
图3A为本发明的栅极驱动电路的第一实施例于第二时间的示意图。FIG. 3A is a schematic diagram of the first embodiment of the gate driving circuit of the present invention at a second time.
图3B本发明的栅极驱动电路的第一实施例于第二时间的信号波形图。3B is a signal waveform diagram at the second time of the first embodiment of the gate driving circuit of the present invention.
图4A为本发明的栅极驱动电路的第一实施例于第三时间的示意图。FIG. 4A is a schematic diagram of the first embodiment of the gate driving circuit of the present invention at a third time.
图4B为本发明的栅极驱动电路的第一实施例于第三时间的信号波形图。FIG. 4B is a signal waveform diagram at the third time of the first embodiment of the gate driving circuit of the present invention.
图5A为本发明的栅极驱动电路的第一实施例于第四时间的示意图。FIG. 5A is a schematic diagram of the first embodiment of the gate driving circuit of the present invention at the fourth time.
图5B为本发明的栅极驱动电路的第一实施例于第四时间的信号波形图。FIG. 5B is a signal waveform diagram at the fourth time of the first embodiment of the gate driving circuit of the present invention.
图6为本发明的栅极驱动电路的第二实施例的配置图。FIG. 6 is a configuration diagram of the second embodiment of the gate driving circuit of the present invention.
图7A为本发明的栅极驱动电路的第二实施例于第一时间的示意图。FIG. 7A is a schematic diagram of the second embodiment of the gate driving circuit of the present invention at the first time.
图7B为本发明的栅极驱动电路的第二实施例于第一时间的信号波形图。FIG. 7B is a signal waveform diagram at the first time of the second embodiment of the gate driving circuit of the present invention.
图8A为本发明的栅极驱动电路的第二实施例于第二时间的示意图。FIG. 8A is a schematic diagram of the second embodiment of the gate driving circuit of the present invention at a second time.
图8B为本发明的栅极驱动电路的第二实施例于第二时间的信号波形图。FIG. 8B is a signal waveform diagram at the second time of the second embodiment of the gate driving circuit of the present invention.
图9A为本发明的栅极驱动电路的第二实施例于第三时间的示意图。FIG. 9A is a schematic diagram of the second embodiment of the gate driving circuit of the present invention at the third time.
图9B为本发明的栅极驱动电路的第二实施例于第三时间的信号波形图。FIG. 9B is a signal waveform diagram at the third time of the second embodiment of the gate driving circuit of the present invention.
图10A为本发明的栅极驱动电路的第二实施例于第四时间的示意图。FIG. 10A is a schematic diagram of the second embodiment of the gate driving circuit of the present invention at the fourth time.
图10B为本发明的栅极驱动电路的第二实施例于第四时间的信号波形图。FIG. 10B is a signal waveform diagram at the fourth time of the second embodiment of the gate driving circuit of the present invention.
其中，附图标记：Among them, the reference signs are:
10,20:双向传输电路10,20: Bidirectional transmission circuit
11,21:第一电路11,21: First circuit
12,22:第二电路12,22: Second circuit
13,23:第三电路13,23:Third circuit
B[n]:第四节点的电压信号B[n]: voltage signal of the fourth node
C1:第一电容C1: first capacitor
C2:第二电容C2: second capacitor
C3:第三电容C3: The third capacitor
C[n]:本级第一信号线C[n]: The first signal line of this level
C[n-1]:前一级第一信号线C[n-1]: The first signal line of the previous stage
C[n+1]:后一级第一信号线C[n+1]: The first signal line of the next stage
CK:第一时脉线CK: first clock line
D2U:第二传输信号线D2U: second transmission signal line
G[n]:输出端的电压信号G[n]: voltage signal at the output end
K[n]:本级第二信号线K[n]: The second signal line of this level
N1:第一节点N1: first node
N2:第二节点N2: second node
N3:第三节点N3: The third node
N4:第四节点N4: fourth node
P[n]:第三节点的电压信号P[n]: Voltage signal of the third node
P1:第一时间P1: The first time
P2:第二时间P2: Second time
P3:第三时间P3: The third time
P4:第四时间P4: The fourth time
Q[n]:第一节点的电压信号Q[n]: voltage signal of the first node
T1:第一晶体管T1: first transistor
T2:第二晶体管T2: The second transistor
T3:第三晶体管T3: The third transistor
T4:第四晶体管T4: The fourth transistor
T5:第五晶体管T5: fifth transistor
T6A,T6B:第六晶体管T6A, T6B: sixth transistor
T7A,T7B:第七晶体管T7A, T7B: seventh transistor
T8A,T8B:第八晶体管T8A, T8B: The eighth transistor
T9A,T9B:第九晶体管T9A, T9B: ninth transistor
T10:第十晶体管T10: tenth transistor
T11:第十一晶体管T11: The eleventh transistor
T12:第十二晶体管T12: Twelfth transistor
U2D:第一传输信号线U2D: the first transmission signal line
VB,Vp,Vk,VQ:电压V B ,V p ,V k ,V Q : voltage
VGL:第一电压V GL : first voltage
VGH:第二电压V GH : Second voltage
VL:第三电压V L : third voltage
VTH_T1:第一晶体管的临界电压V TH_T1 : critical voltage of the first transistor
VTH_T7:第六晶体管的临界电压V TH_T7 : Critical voltage of the sixth transistor
VTH_T7:第七晶体管的临界电压V TH_T7 : critical voltage of the seventh transistor
XCK:第二时脉线XCK: Second clock line
XCKL:第三时脉线XCKL: third clock line
具体实施方式Detailed ways
本发明的优点、特征以及达到的技术方法将参照例示性实施例及所附图式进行更详细地描述而更容易理解，且本发明可以不同形式来实现，故不应被理解仅限于此处所陈述的实施例，相反地，对所属技术领域具有通常知识者而言，所提供的实施例将使本揭露更加透彻与全面且完整地传达本发明的范畴，且本发明将仅为所附加的申请专利范围所定义。The advantages, features and technical methods achieved by the present invention will be described in more detail with reference to the exemplary embodiments and accompanying drawings to be more easily understood. The present invention can be implemented in different forms and should not be understood to be limited to what is described here. Rather, these embodiments will be provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those of ordinary skill in the art, and the present invention will be disclosed only as an appended defined by the scope of the patent application.
应当理解的是，尽管术语“第一”、“第二”等在本发明中可用于描述各种元件、部件、区域、层及/或部分，但是这些元件、部件、区域、层及/或部分不应受这些术语的限制。这些术语仅用于将一个元件、部件、区域、层及/或部分与另一个元件、部件、区域、层及/或部分区分开。因此，下文讨论的“第一元件”、“第一部件”、“第一区域”、“第一层”及/或“第一部分”可以被称为“第二元件”、“第二部件”、“第二区域”、“第二层”及/或“第二部分”，而不悖离本发明的精神和教示。It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or Sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer and/or section from another element, component, region, layer and/or section. Thus, a "first element", "first component", "first region", "first layer" and/or "first section" discussed below could be termed a "second element", "second component" , "second region", "second layer" and/or "second part" without departing from the spirit and teachings of the present invention.
另外，术语“包括”及/或“包含”指所述特征、区域、整体、步骤、操作、元件及/或部件的存在，但不排除一个或多个其他特征、区域、整体、步骤、操作、元件、部件及/或其组合的存在或添加。In addition, the terms "comprises" and/or "comprises" refer to the presence of stated features, regions, integers, steps, operations, elements and/or parts, but do not exclude the presence of one or more other features, regions, integers, steps, operations , elements, parts and/or combinations thereof.
除非另有定义，本发明所使用的所有术语(包括技术和科学术语)具有与本发明所属技术领域的普通技术人员通常理解的相同含义。将进一步理解的是，诸如在通常使用的字典中定义的那些术语应当被解释为具有与它们在相关技术和本发明的上下文中的含义一致的定义，并且将不被解释为理想化或过度正式的意义，除非本文中明确地这样定义。Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed to have definitions consistent with their meanings in the context of the relevant technology and the present invention, and are not to be construed as idealistic or overly formal meaning unless expressly so defined herein.
请参阅图1，其为本发明的栅极驱动电路的第一实施例的配置图。如图1所示，本发明的栅极驱动电路，其包括双向传输电路10、第一电路11、第二电路12和第三电路13。双向传输电路10包括第一晶体管T1和第二晶体管T2，第一晶体管T1的控制端耦接前一级第一信号线C[n-1]，第二晶体管T2的控制端耦接后一级第一信号线C[n+1]，第一晶体管T1和第二晶体管T2的第一端分别耦接第一传输信号线U2D和第二传输信号线D2U，第一晶体管T1和第二晶体管T2的第二端耦接第一节点N1。第一电路11耦接第一节点N1和输出端，第一电路11耦接第一时脉线CK、本级第一信号线C[n]、本级第二信号线K[n]和电压线。第二电路12耦接输出端，第二电路12耦接第一时脉线CK、第二时脉线XCK、第三时脉信号线XCKL、本级第一信号线C[n]及电压线。第三电路13耦接第一节点N1及第二节点N2，第三电路13耦接第一时脉线CK、第二时脉线XCK、本级第二信号线K[n]及电压线。Please refer to FIG. 1 , which is a configuration diagram of a gate driving circuit according to a first embodiment of the present invention. As shown in FIG. 1 , the gate driving circuit of the present invention includes a bidirectional transmission circuit 10 , a first circuit 11 , a second circuit 12 and a third circuit 13 . The bidirectional transmission circuit 10 includes a first transistor T1 and a second transistor T2. The control terminal of the first transistor T1 is coupled to the first signal line C[n-1] of the previous stage, and the control terminal of the second transistor T2 is coupled to the subsequent stage. The first signal line C[n+1], the first ends of the first transistor T1 and the second transistor T2 are respectively coupled to the first transmission signal line U2D and the second transmission signal line D2U, the first transistor T1 and the second transistor T2 The second end of is coupled to the first node N1. The first circuit 11 is coupled to the first node N1 and the output terminal. The first circuit 11 is coupled to the first clock line CK, the first signal line C[n] of this stage, the second signal line K[n] of this stage and the voltage. Wire. The second circuit 12 is coupled to the output terminal. The second circuit 12 is coupled to the first clock line CK, the second clock line XCK, the third clock signal line XCKL, the first signal line C[n] of this stage and the voltage line. . The third circuit 13 is coupled to the first node N1 and the second node N2. The third circuit 13 is coupled to the first clock line CK, the second clock line XCK, the second signal line K[n] of this stage and the voltage line.
在第一实施例中，第一电路11包括第三晶体管T3、第四晶体管T4、第五晶体管T5以及第一电容C1，第二电路12包括第六晶体管T6A、第七晶体管T7A、第八晶体管T8A、第九晶体管T9A以及第二电容C2，第三电路13包括第十晶体管T10、第十一晶体管T11、第十二晶体管T12以及第三电容C3。第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第六晶体管T6A、第七晶体管T7A、第八晶体管T8A、第十晶体管T10、第十一晶体管T11和第十二晶体管T12为N型晶体管，第五晶体管T5和第九晶体管T9A为P型晶体管。In the first embodiment, the first circuit 11 includes a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a first capacitor C1, and the second circuit 12 includes a sixth transistor T6A, a seventh transistor T7A, an eighth transistor T8A, the ninth transistor T9A and the second capacitor C2. The third circuit 13 includes the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12 and the third capacitor C3. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6A, the seventh transistor T7A, the eighth transistor T8A, the tenth transistor T10, the eleventh transistor T11 and the twelfth transistor T12 is an N-type transistor, and the fifth transistor T5 and the ninth transistor T9A are P-type transistors.
N型晶体管的材料可包括氧化铟锡(Indium Tin Oxide,ITO)、氧化锌(ZnO)、氧化铝镓铟锡(AlGaInSnO)、氧化铝锌(Aluminium-doped Zinc Oxide,AZO)、氧化锡(SnO2)、氧化铟(In2O3)或氧化铟镓锌(Indium Gallium Zinc Oxide,IGZO)，通过前述材料能防止内部节点电压在输出信号时受漏电影响输出；P型晶体管的材料可包括多晶硅或低温多晶硅(Low Temperature Poly-silicon,LTPS)，通过前述材料能减少布局面积。Materials for N-type transistors may include indium tin oxide (ITO), zinc oxide (ZnO), aluminum gallium indium tin oxide (AlGaInSnO), aluminum zinc oxide (Aluminium-doped Zinc Oxide, AZO), tin oxide (SnO2) ), indium oxide (In2O3) or indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO). The aforementioned materials can prevent the internal node voltage from being affected by leakage when outputting signals; the material of the P-type transistor can include polysilicon or low-temperature polysilicon ( Low Temperature Poly-silicon (LTPS), the layout area can be reduced through the aforementioned materials.
其中，电压线包括第一电压线和第二电压线，第一电压线提供第一电压VGL，第二电压线提供第二电压VGH。The voltage line includes a first voltage line and a second voltage line. The first voltage line provides the first voltage V GL , and the second voltage line provides the second voltage V GH .
在第一实施例中，第三晶体管T3的控制端耦接本级第二信号线K[n]，第三晶体管T3的第一端耦接第一电压线，第三晶体管T3的第二端耦接第一节点N1，第四晶体管T4的第一端耦接第一时脉线CK，第四晶体管T4的控制端耦接第一节点N1，第四晶体管T4的第二端耦接第二节点N2，第一电容C1设置于第二节点N2和第一节点N1之间，第二节点N2耦接本级第一信号线C[n]，第五晶体管T5的第一端耦接第二电压线，第五晶体管T5的控制端耦接第二节点N2，第五晶体管T5的第二端耦接输出端。换句话说，第三晶体管T3的第二端、第四晶体管T4的控制端和第一电容C1的一端互相连接，第四晶体管T4的第二端、第五晶体管T5的控制端和第一电容C1的另一端互相连接，第三晶体管T3的第二端、第一晶体管T1的第二端和第二晶体管T2的第二端互相连接。In the first embodiment, the control terminal of the third transistor T3 is coupled to the second signal line K[n] of the current stage, the first terminal of the third transistor T3 is coupled to the first voltage line, and the second terminal of the third transistor T3 Coupled to the first node N1, a first terminal of the fourth transistor T4 is coupled to the first clock line CK, a control terminal of the fourth transistor T4 is coupled to the first node N1, and a second terminal of the fourth transistor T4 is coupled to the second clock line CK. Node N2, the first capacitor C1 is disposed between the second node N2 and the first node N1, the second node N2 is coupled to the first signal line C[n] of this stage, and the first end of the fifth transistor T5 is coupled to the second The voltage line, the control terminal of the fifth transistor T5 is coupled to the second node N2, and the second terminal of the fifth transistor T5 is coupled to the output terminal. In other words, the second terminal of the third transistor T3, the control terminal of the fourth transistor T4 and one terminal of the first capacitor C1 are connected to each other, and the second terminal of the fourth transistor T4, the control terminal of the fifth transistor T5 and the first capacitor C1 are connected to each other. The other end of C1 is connected to each other, and the second end of the third transistor T3, the second end of the first transistor T1, and the second end of the second transistor T2 are connected to each other.
第六晶体管T6A的第一端和控制端互相耦接，第六晶体管T6A的第二端耦接第三节点N3，第六晶体管T6A的第一端和第七晶体管T7A的第一端耦接第四节点N4，第七晶体管T7A的控制端耦接第二时脉线XCK，第七晶体管T7A的第二端耦接第二电压线，第二电容C2的一端耦接第四节点N4，第二电容C2的另一端耦接第一时脉线CK，第八晶体管T8A的第一端耦接第一电压线，第八晶体管T8A的控制端耦接本级第一信号线C[n]，第八晶体管T8A的第二端耦接第三节点N3，第九晶体管T9A的第一端耦接输出端，第九晶体管T9A的控制端耦接第三节点N3，第九晶体管T9A的第二端耦接第三时脉线XCKL。换句话说，第六晶体管T6A的控制端、第七晶体管T7A的第一端和第二电容C2的一端互相连接，第八晶体管T8A的第二端、第六晶体管T6A的第二端和第九晶体管T9A的控制端互相连接。The first terminal and the control terminal of the sixth transistor T6A are coupled to each other, the second terminal of the sixth transistor T6A is coupled to the third node N3, the first terminal of the sixth transistor T6A and the first terminal of the seventh transistor T7A are coupled to the third node N3. Four nodes N4, the control end of the seventh transistor T7A is coupled to the second clock line XCK, the second end of the seventh transistor T7A is coupled to the second voltage line, one end of the second capacitor C2 is coupled to the fourth node N4, the second The other end of the capacitor C2 is coupled to the first clock line CK, the first end of the eighth transistor T8A is coupled to the first voltage line, and the control end of the eighth transistor T8A is coupled to the first signal line C[n] of this stage. The second terminal of the eight transistor T8A is coupled to the third node N3, the first terminal of the ninth transistor T9A is coupled to the output terminal, the control terminal of the ninth transistor T9A is coupled to the third node N3, and the second terminal of the ninth transistor T9A is coupled to the output terminal. Connect to the third clock line XCKL. In other words, the control terminal of the sixth transistor T6A, the first terminal of the seventh transistor T7A and one terminal of the second capacitor C2 are connected to each other, and the second terminal of the eighth transistor T8A, the second terminal of the sixth transistor T6A and the ninth terminal are connected to each other. The control terminals of transistors T9A are connected to each other.
第十晶体管T10的第一端耦接第二节点N2，第十晶体管T10的控制端耦接第二时脉线XCK，第十晶体管T10的第二端耦接第一电压线，第十一晶体管T11的第一端耦接第二节点N2，第十一晶体管T11的第二端耦接第一电压线，第十一晶体管T11的控制端耦接本级第二信号线K[n]，第十二晶体管T12的第一端耦接本级第二信号线K[n]，第十二晶体管T12的控制端耦接第一节点N1，第十二晶体管T12的第二端耦接第一电压线，第三电容C3的一端耦接本级第二信号线K[n]，第三电容C3的另一端耦接第一时脉线CK。换句话说，第十晶体管T10的第一端和第十一晶体管T11的第一端互相连接，第十一晶体管T11的控制端、第十二晶体管T12的第一端和第三电容C3的一端互相连接。The first terminal of the tenth transistor T10 is coupled to the second node N2, the control terminal of the tenth transistor T10 is coupled to the second clock line XCK, the second terminal of the tenth transistor T10 is coupled to the first voltage line, and the eleventh transistor The first terminal of T11 is coupled to the second node N2, the second terminal of the eleventh transistor T11 is coupled to the first voltage line, and the control terminal of the eleventh transistor T11 is coupled to the second signal line K[n] of this stage. The first terminal of the twelfth transistor T12 is coupled to the second signal line K[n] of this stage, the control terminal of the twelfth transistor T12 is coupled to the first node N1, and the second terminal of the twelfth transistor T12 is coupled to the first voltage. line, one end of the third capacitor C3 is coupled to the second signal line K[n] of this stage, and the other end of the third capacitor C3 is coupled to the first clock line CK. In other words, the first terminal of the tenth transistor T10 and the first terminal of the eleventh transistor T11 are connected to each other, the control terminal of the eleventh transistor T11, the first terminal of the twelfth transistor T12 and one terminal of the third capacitor C3 Connect to each other.
请参阅图2A和图2B，其为本发明的栅极驱动电路的第一实施例于第一时间的示意图以及本发明的栅极驱动电路的第一实施例于第一时间的信号波形图。如图2A和图2B所示，在第一时间P1，前一级第一信号线C[n-1]传输前一级第一信号(此时其电压为第二电压VGH)使第一晶体管T1导通，后一级第一信号线C[n+1]传输后一级第一信号(此时其电压为第一电压VGL)使第二晶体管T2关闭，第一节点N1的电压信号Q[n]的电压值为VGH-VTH_T1(VTH_T1为第一晶体管T1的临界电压)，第一节点N1的电压信号Q[n]使第四晶体管T4和第十二晶体管T12导通，本级第一信号线C[n]传输本级第一信号(此时其电压为第一电压VGL)使第八晶体管T8A关闭，本级第一信号线C[n]传输本级第一信号至第四晶体管T4的第二端和第五晶体管T5的控制端，第三节点N3的电压信号P[n]的电压值仍维持在电压Vp，第三时脉信号线XCKL传输第三时脉信号(此时其电压为第二电压VGH)，第九晶体管T9A的第二端和控制端的电压差并未大于第九晶体管T9A的临界电压，使第九晶体管T9A关闭，本级第二信号线K[n]传输本级第二信号(此时其电压为第一电压VGL)使第三晶体管T3和第十一晶体管T11关闭。Please refer to FIG. 2A and FIG. 2B , which are schematic diagrams of the first embodiment of the gate driving circuit of the present invention at a first time and a signal waveform diagram of the first embodiment of the gate driving circuit of the present invention at a first time. As shown in Figure 2A and Figure 2B, at the first time P1, the first signal line C[n-1] of the previous stage transmits the first signal of the previous stage (its voltage is the second voltage V GH at this time) so that the first signal line C[n-1] of the previous stage transmits the first signal of the previous stage. The transistor T1 is turned on, and the first signal line C[n+1] of the subsequent stage transmits the first signal of the subsequent stage (its voltage is the first voltage V GL at this time), causing the second transistor T2 to turn off, and the voltage of the first node N1 The voltage value of the signal Q[n] is V GH -V TH_T1 (V TH_T1 is the critical voltage of the first transistor T1). The voltage signal Q[n] of the first node N1 causes the fourth transistor T4 and the twelfth transistor T12 to conduct. pass, the first signal line C[n] of this level transmits the first signal of this level (its voltage is the first voltage V GL at this time), causing the eighth transistor T8A to turn off, and the first signal line C[n] of this level transmits the first signal of this level The first signal is sent to the second terminal of the fourth transistor T4 and the control terminal of the fifth transistor T5. The voltage value of the voltage signal P[n] of the third node N3 is still maintained at the voltage V p . The third clock signal line XCKL transmits In the third clock signal (the voltage of which is the second voltage V GH at this time), the voltage difference between the second terminal and the control terminal of the ninth transistor T9A is not greater than the critical voltage of the ninth transistor T9A, causing the ninth transistor T9A to turn off. The second signal line K[n] of the stage transmits the second signal of the stage (its voltage is the first voltage V GL at this time), causing the third transistor T3 and the eleventh transistor T11 to turn off.
第二时脉信号线XCK传输第二时脉信号(此时其电压为第二电压VGH)使第七晶体管T7A和第十晶体管T10导通，第四节点N4的电压信号B[n]的电压值为VGL-VTH_T7(VTH_T7为第七晶体管T7A的临界电压)，第三节点N3的电压信号P[n]的电压值大于第四节点N4的电压信号B[n]的电压值，使第六晶体管T6A关闭，本级第一信号(此时其电压为第一电压VGL)输入至第五晶体管T5的控制端，第五晶体管T5的第二端和控制端的电压差大于第五晶体管T5的临界电压，使第五晶体管T5导通，于输出端输出电压信号G[n]，电压信号G[n]的电压值为第二电压VGH。The second clock signal line The voltage value is V GL -V TH_T7 (V TH_T7 is the critical voltage of the seventh transistor T7A). The voltage value of the voltage signal P[n] of the third node N3 is greater than the voltage value of the voltage signal B[n] of the fourth node N4. , causing the sixth transistor T6A to turn off, the first signal of this stage (at this time its voltage is the first voltage V GL ) is input to the control terminal of the fifth transistor T5, and the voltage difference between the second terminal and the control terminal of the fifth transistor T5 is greater than The critical voltage of the fifth transistor T5 causes the fifth transistor T5 to be turned on and output a voltage signal G[n] at the output terminal. The voltage value of the voltage signal G[n] is the second voltage V GH .
请参阅图3A和图3B，其为本发明的栅极驱动电路的第一实施例于第二时间的示意图。如图3A和图3B所示，在第二时间P2，前一级第一信号(此时其电压为第一电压VGL)使第一晶体管T1关闭，后一级第一信号(此时其电压为第一电压VGL)使第二晶体管T2关闭，第一节点N1的电压信号Q[n]的电压值仍维持在电压VQ，第一节点N1的电压信号Q[n]的电压值使第四晶体管T4导通，本级第一信号(此时其电压为第二电压VGH)使第八晶体管T8A导通，第三节点N3的电压信号P[n]的电压值为第一电压VGL，第二时脉信号(此时其电压为第一电压VGL)使第七晶体管T7A和第十晶体管T10关闭，第四节点N4的电压信号B[n]的电压值为VGL+VTH_T6(VTH_T6为第六晶体管T6A的临界电压)。由于本级第一信号的控制端电压为第二电压VGH，使第五晶体管T5的第二端和控制端的电压差并未大于第五晶体管T5的临界电压，第五晶体管T5关闭，输出端的电压信号G[n]的电压值为第一电压VGL。Please refer to FIG. 3A and FIG. 3B , which are schematic diagrams of the first embodiment of the gate driving circuit of the present invention at a second time. As shown in Figure 3A and Figure 3B, at the second time P2, the first signal of the previous stage (at this time its voltage is the first voltage V GL ) turns off the first transistor T1, and the first signal of the subsequent stage (at this time its voltage The voltage is the first voltage V GL ), causing the second transistor T2 to turn off. The voltage value of the voltage signal Q[n] of the first node N1 is still maintained at the voltage V Q . The voltage value of the voltage signal Q[n] of the first node N1 is The fourth transistor T4 is turned on, the first signal of this stage (at this time its voltage is the second voltage V GH ) turns on the eighth transistor T8A, and the voltage value of the voltage signal P[n] of the third node N3 is the first Voltage V GL , the second clock signal (at this time its voltage is the first voltage V GL ) turns off the seventh transistor T7A and the tenth transistor T10 , and the voltage value of the voltage signal B[n] of the fourth node N4 is V GL +V TH_T6 (V TH_T6 is the threshold voltage of the sixth transistor T6A). Since the control terminal voltage of the first signal of this stage is the second voltage V GH , the voltage difference between the second terminal and the control terminal of the fifth transistor T5 is not greater than the critical voltage of the fifth transistor T5. The fifth transistor T5 is turned off, and the output terminal The voltage value of the voltage signal G[n] is the first voltage V GL .
由于第三时脉信号的电压值为第三电压VL，第三电压VL大于第一电压VGL但小于第二电压VGH，第九晶体管T9A的第二端和控制端的电压差大于第九晶体管T9A的临界电压，第九晶体管T9A导通。本级第二信号(此时其电压为第一电压VGL)使第三晶体管T3和第十一晶体管T11关闭，第三节点N3的电压信号P[n]的电压值小于第四节点N4的电压信号B[n]的电压值，使第六晶体管T6A导通，第一节点N1的电压信号Q[n]使第十二晶体管T12导通。Since the voltage value of the third clock signal is the third voltage V L , and the third voltage V L is greater than the first voltage V GL but less than the second voltage V GH , the voltage difference between the second terminal and the control terminal of the ninth transistor T9A is greater than the first voltage V GL . The critical voltage of the ninth transistor T9A, the ninth transistor T9A is turned on. The second signal of this stage (its voltage is the first voltage V GL at this time) turns off the third transistor T3 and the eleventh transistor T11. The voltage value of the voltage signal P[n] of the third node N3 is smaller than that of the fourth node N4. The voltage value of the voltage signal B[n] turns on the sixth transistor T6A, and the voltage signal Q[n] of the first node N1 turns on the twelfth transistor T12.
请参阅图4A和图4B，其为本发明的栅极驱动电路的第一实施例于第三时间的示意图以及本发明的栅极驱动电路的第一实施例于第三时间的信号波形图。如图4A和图4B所示，在第三时间P3，前一级第一信号(此时其电压为第一电压VGL)使第一晶体管T1关闭，后一级第一信号(此时其电压为第二电压VGH)使第二晶体管T2导通，第一节点N1的电压信号Q[n]的电压值为第一电压VGL而使第四晶体管T4和第十二晶体管T12关闭，本级第一信号(此时其电压为第一电压VGL)使第八晶体管T8A关闭，第二时脉信号(此时其电压为第二电压VGH)使第七晶体管T7A和第十晶体管T10导通，第四节点N4的电压信号B[n]的电压值为VGH-VTH_T7(VTH_T7为第七晶体管T7A的临界电压)，第六晶体管T6A因第四节点N4的电压信号B[n]而导通，第三节点N3的电压信号P[n]的电压值为VGH-VTH_T7-VTH_T6(VTH_T6为第六晶体管T6A的临界电压)，第三节点N3的电压小于第四节点N4的电压。Please refer to FIG. 4A and FIG. 4B , which are schematic diagrams of the first embodiment of the gate driving circuit of the present invention at a third time and a signal waveform diagram of the first embodiment of the gate driving circuit of the present invention at a third time. As shown in Figure 4A and Figure 4B, at the third time P3, the first signal of the previous stage (at this time its voltage is the first voltage V GL ) turns off the first transistor T1, and the first signal of the subsequent stage (at this time its voltage The voltage is the second voltage V GH ) to turn on the second transistor T2, and the voltage value of the voltage signal Q[n] at the first node N1 is the first voltage V GL to turn off the fourth transistor T4 and the twelfth transistor T12, The first signal of this stage (at this time its voltage is the first voltage V GL ) turns off the eighth transistor T8A, and the second clock signal (at this time its voltage is the second voltage V GH ) turns off the seventh transistor T7A and the tenth transistor T10 is turned on, and the voltage value of the voltage signal B[n] of the fourth node N4 is V GH -V TH_T7 (V TH_T7 is the critical voltage of the seventh transistor T7A). The sixth transistor T6A is turned on due to the voltage signal B of the fourth node N4. [n] is turned on, the voltage value of the voltage signal P[n] of the third node N3 is V GH -V TH_T7 -V TH_T6 (V TH_T6 is the critical voltage of the sixth transistor T6A), and the voltage of the third node N3 is less than The voltage of the fourth node N4.
由于第三时脉信号的电压值为第二电压VGH和第三节点N3的电压信号P[n]的电压值为VGH-VTH_T7-VTH_T6，第九晶体管T9A的第二端和控制端的电压差大于第九晶体管的临界电压，第九晶体管T9A因而导通。本级第二信号(此时其电压为第一电压VGL)使第三晶体管T3和第十一晶体管T11关闭，本级第一信号的电压为第一电压VGL，使第五晶体管T5的第二端和控制端的电压差大于第五晶体管T5的临界电压，第五晶体管T5导通，于输出端输出电压信号G[n]，电压信号G[n]的电压值为第二电压VGH。Since the voltage value of the third clock signal is the second voltage V GH and the voltage value of the voltage signal P[n] of the third node N3 is V GH -V TH_T7 -V TH_T6 , the second terminal of the ninth transistor T9A and the control The voltage difference between the terminals is greater than the critical voltage of the ninth transistor, so the ninth transistor T9A is turned on. The second signal of this level (the voltage of which is the first voltage V GL at this time) turns off the third transistor T3 and the eleventh transistor T11. The voltage of the first signal of this level is the first voltage V GL , causing the fifth transistor T5 to turn off. The voltage difference between the second terminal and the control terminal is greater than the critical voltage of the fifth transistor T5. The fifth transistor T5 is turned on and outputs a voltage signal G[n] at the output terminal. The voltage value of the voltage signal G[n] is the second voltage V GH .
请参阅图5A和图5B，其为本发明的栅极驱动电路的第一实施例于第四时间的示意图以及本发明的栅极驱动电路的第一实施例于第四时间的信号波形图。如图5A和图5B所示，在第四时间P4，前一级第一信号(此时其电压为第一电压VGL)使第一晶体管T1关闭，后一级第一信号(此时其电压为第一电压VGL)使第二晶体管T2关闭，第一节点N1的电压信号Q[n]的电压值为第一电压VGL而使第四晶体管T4和第十二晶体管T12关闭，本级第一信号使第八晶体管T8A关闭，本级第一信号的电压为第一电压VGL，第一节点N1的电压小于第二节点N2的电压，使第四晶体管T4的控制端和第二端的电压差小于第四晶体管的临界电压，第四晶体管T4关闭，使第五晶体管T5的第二端和控制端的电压差大于第五晶体管T5的临界电压，第五晶体管T5导通，于输出端输出电压信号G[n]，电压信号G[n]的电压值为第二电压VGH。Please refer to FIG. 5A and FIG. 5B , which are schematic diagrams of the first embodiment of the gate driving circuit of the present invention at the fourth time and a signal waveform diagram of the first embodiment of the gate driving circuit of the present invention at the fourth time. As shown in Figure 5A and Figure 5B, at the fourth time P4, the first signal of the previous stage (at this time its voltage is the first voltage V GL ) turns off the first transistor T1, and the first signal of the subsequent stage (at this time its voltage The voltage is the first voltage V GL ), which turns off the second transistor T2. The voltage value of the voltage signal Q[n] at the first node N1 is the first voltage V GL , which turns off the fourth transistor T4 and the twelfth transistor T12. This The first signal of the stage turns off the eighth transistor T8A. The voltage of the first signal of this stage is the first voltage V GL . The voltage of the first node N1 is smaller than the voltage of the second node N2, so that the control terminal of the fourth transistor T4 and the second The voltage difference between the second terminal and the control terminal of the fifth transistor T5 is less than the critical voltage of the fourth transistor, and the fourth transistor T4 is turned off, so that the voltage difference between the second terminal and the control terminal of the fifth transistor T5 is greater than the critical voltage of the fifth transistor T5. The fifth transistor T5 is turned on, and the output terminal A voltage signal G[n] is output, and the voltage value of the voltage signal G[n] is the second voltage V GH .
本级第二信号(此时其电压为电压Vk)使第三晶体管T3和第十一晶体管T11导通，第二时脉信号使第七晶体管T7A和第十晶体管T10关闭，第三节点N3的电压信号P[n]的电压值维持在电压Vp，第四节点N4的电压信号B[n]的电压值为VB，第三节点N3的电压小于第四节点N4的电压，使第六晶体管T6A导通，第九晶体管T9A的第二端和控制端的电压差小于第九晶体管T9A的临界电压，第九晶体管T9A关闭，因为第一节点N1的电压信号Q[n]的电压值为第一电压VGL，使第十二晶体管T12关闭。由于第一时脉信号的第二电压VGH将第二电容C2耦合至VGH-VTH_T7+ΔV，并搭配第六晶体管T6A的二极管连接方式，使第三节点N3的电压信号P[n]的电压值大于第二电压VGH，确保第九晶体管T9A于稳压阶段关闭。The second signal of this stage (the voltage of which is voltage V k at this time) turns on the third transistor T3 and the eleventh transistor T11. The second clock signal turns off the seventh transistor T7A and the tenth transistor T10. The third node N3 The voltage value of the voltage signal P[n] is maintained at the voltage V p , the voltage value of the voltage signal B[n] of the fourth node N4 is V B , and the voltage of the third node N3 is smaller than the voltage of the fourth node N4, so that the voltage value of the fourth node N4 is V B . The sixth transistor T6A is turned on, the voltage difference between the second terminal and the control terminal of the ninth transistor T9A is less than the critical voltage of the ninth transistor T9A, and the ninth transistor T9A is turned off, because the voltage value of the voltage signal Q[n] of the first node N1 is The first voltage V GL turns off the twelfth transistor T12. Since the second voltage V GH of the first clock signal couples the second capacitor C2 to V GH -V TH_T7 +ΔV, and cooperates with the diode connection method of the sixth transistor T6A, the voltage signal P[n] of the third node N3 The voltage value is greater than the second voltage V GH , ensuring that the ninth transistor T9A is turned off during the voltage stabilization stage.
请参阅图6，其为本发明的栅极驱动电路的第二实施例的配置图。如图6所示，本发明的栅极驱动电路，其包括双向传输电路20、第一电路21、第二电路22和第三电路23，双向传输电路20包括第一晶体管T1和第二晶体管T2，第一电路21包括第三晶体管T3、第四晶体管T4、第五晶体管T5以及第一电容C1，第二电路22包括第六晶体管T6B、第七晶体管T7B、第八晶体管T8B、第九晶体管T9B以及第二电容C2，第三电路23包括第十晶体管T10、第十一晶体管T11、第十二晶体管T12以及第三电容C3，第二实施例与第一实施例具有相同的元件，但第二实施例的第一电路21和第二电路22的配置和第一实施例的配置相异，第二实施例的双向传输电路20和第三电路23的配置和第一实施例的配置相同，于此不再重复叙述。Please refer to FIG. 6 , which is a configuration diagram of a gate driving circuit according to a second embodiment of the present invention. As shown in Figure 6, the gate drive circuit of the present invention includes a bidirectional transmission circuit 20, a first circuit 21, a second circuit 22 and a third circuit 23. The bidirectional transmission circuit 20 includes a first transistor T1 and a second transistor T2. , the first circuit 21 includes a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a first capacitor C1, and the second circuit 22 includes a sixth transistor T6B, a seventh transistor T7B, an eighth transistor T8B, and a ninth transistor T9B. and a second capacitor C2. The third circuit 23 includes a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12 and a third capacitor C3. The second embodiment has the same components as the first embodiment, but the second The configurations of the first circuit 21 and the second circuit 22 of the embodiment are different from the configuration of the first embodiment. The configurations of the bidirectional transmission circuit 20 and the third circuit 23 of the second embodiment are the same as those of the first embodiment. This will not be repeated.
在第二实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第六晶体管T6B、第七晶体管T7B、第九晶体管T9B、第十晶体管T10、第十一晶体管T11和第十二晶体管T12为N型晶体管，第五晶体管T5和第八晶体管T8B为P型晶体管。N型晶体管和P型晶体管的材料已于前述段落说明，于此不再重复叙述。电压线包括第一电压线、第二电压线以及第三电压线，第一电压线提供第一电压VGL，第二电压线提供第二电压VGH，第三电压线提供第三电压VL，第三电压VL大于第一电压VGL但小于第二电压VGH。In the second embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6B, the seventh transistor T7B, the ninth transistor T9B, the tenth transistor T10, the eleventh transistor The transistor T11 and the twelfth transistor T12 are N-type transistors, and the fifth transistor T5 and the eighth transistor T8B are P-type transistors. The materials of N-type transistors and P-type transistors have been described in the previous paragraphs and will not be described again here. The voltage lines include a first voltage line, a second voltage line and a third voltage line. The first voltage line provides the first voltage V GL , the second voltage line provides the second voltage V GH , and the third voltage line provides the third voltage V L , the third voltage V L is greater than the first voltage V GL but less than the second voltage V GH .
在第二实施例中，第三晶体管T3的控制端耦接本级第二信号线K[n]，第三晶体管T3的第一端耦接第一电压线，第三晶体管T3的第二端耦接第一节点N1，第四晶体管T4的第一端耦接第一时脉线CK，第四晶体管T4的控制端耦接第一节点N1，第四晶体管T4的第二端耦接第二节点N2，第一电容C1位于第二节点N2和第一节点N1之间，第二节点N2耦接本级第一信号线C[n]，第五晶体管T5的第一端耦接第二电压线，第五晶体管T5的控制端耦接第一节点N1，第五晶体管T5的第二端耦接输出端。换句话说，第一节点N1、第四晶体管T4的控制端和第五晶体管T5的控制端互相连接。In the second embodiment, the control terminal of the third transistor T3 is coupled to the second signal line K[n] of this stage, the first terminal of the third transistor T3 is coupled to the first voltage line, and the second terminal of the third transistor T3 Coupled to the first node N1, a first terminal of the fourth transistor T4 is coupled to the first clock line CK, a control terminal of the fourth transistor T4 is coupled to the first node N1, and a second terminal of the fourth transistor T4 is coupled to the second Node N2, the first capacitor C1 is located between the second node N2 and the first node N1, the second node N2 is coupled to the first signal line C[n] of this stage, and the first end of the fifth transistor T5 is coupled to the second voltage. line, the control terminal of the fifth transistor T5 is coupled to the first node N1, and the second terminal of the fifth transistor T5 is coupled to the output terminal. In other words, the first node N1, the control terminal of the fourth transistor T4, and the control terminal of the fifth transistor T5 are connected to each other.
第六晶体管T6B的第一端耦接第三电压线，第六晶体管T6B的控制端耦接本级第一信号线C[n]，第六晶体管T6B的第二端耦接第三节点，第七晶体管T7B的第一端耦接第二电压线，第七晶体管T7B的控制端耦接第二时脉线XCK，第七晶体管T7B的第二端耦接第三节点N3，第二电容C2的一端耦接第三节点N3，第二电容C2的另一端耦接第一时脉线CK，第八晶体管T8B的第一端耦接输出端，第八晶体管T8B的控制端耦接第三节点N3，第八晶体管T8B的第二端耦接第一时脉线CK，第九晶体管T9B的第一端耦接输出端，第九晶体管T9B的控制端耦接第二时脉线XCK，第九晶体管T9B的第二端耦接第三电压线。换句话说，第六晶体管T6B的第二端和第七晶体管T7B的第二端互相连接，第八晶体管T8B的第一端和第九晶体管T9B的第一端互相连接。The first terminal of the sixth transistor T6B is coupled to the third voltage line, the control terminal of the sixth transistor T6B is coupled to the first signal line C[n] of the current stage, and the second terminal of the sixth transistor T6B is coupled to the third node. The first terminal of the seventh transistor T7B is coupled to the second voltage line, the control terminal of the seventh transistor T7B is coupled to the second clock line XCK, the second terminal of the seventh transistor T7B is coupled to the third node N3, and the second terminal of the second capacitor C2 One end is coupled to the third node N3, the other end of the second capacitor C2 is coupled to the first clock line CK, the first end of the eighth transistor T8B is coupled to the output end, and the control end of the eighth transistor T8B is coupled to the third node N3 , the second terminal of the eighth transistor T8B is coupled to the first clock line CK, the first terminal of the ninth transistor T9B is coupled to the output terminal, the control terminal of the ninth transistor T9B is coupled to the second clock line XCK, and the ninth transistor The second end of T9B is coupled to the third voltage line. In other words, the second terminal of the sixth transistor T6B and the second terminal of the seventh transistor T7B are connected to each other, and the first terminal of the eighth transistor T8B and the first terminal of the ninth transistor T9B are connected to each other.
请参阅图7A和图7B，其为本发明的栅极驱动电路的第二实施例于第一时间的示意图以及本发明的栅极驱动电路的第二实施例于第一时间的信号波形图。如图7A和图7B所示，在第一时间P1，前一级第一信号线C[n-1]传输前一级第一信号(此时其电压为第二电压VGH)使第一晶体管T1导通，后一级第一信号传输线C[n+1]传输后一级第一信号(此时其电压为第一电压VGL)使第二晶体管T2关闭，本级第一信号线C[n]传输本级第一信号(此时其电压为第一电压VGL)至第四晶体管T4和第六晶体管T6B，第六晶体管T6B因而关闭，本级第二信号线K[n]传输本级第二信号(此时其电压为第一电压VGL)使第三晶体管T3和第十一晶体管T11关闭，第一节点N1的电压信号Q[n]的电压值为VGH-VTH_T1(VTH_T1为第一晶体管T1的临界电压)，第一节点N1的电压信号Q[n]造成第四晶体管T4的控制端和第二端的电压差大于第四晶体管T4的临界电压，第四晶体管T4导通，第一节点N1的电压信号Q[n]使第十二晶体管T12导通，由于第五晶体管T5的控制端和第一节点N1连接，第五晶体管T5的控制端的电压为第一节点N1的电压信号Q[n]的电压值，使第五晶体管T5的第二端和控制端的电压差小于第五晶体管T5的临界电压，第五晶体管T5关闭，输出端的电压信号G[n]的电压值为第二电压VGH。Please refer to FIGS. 7A and 7B , which are schematic diagrams of the second embodiment of the gate driving circuit of the present invention at the first time and signal waveform diagrams of the second embodiment of the gate driving circuit of the present invention at the first time. As shown in Figure 7A and Figure 7B, at the first time P1, the first signal line C[n-1] of the previous stage transmits the first signal of the previous stage (its voltage is the second voltage V GH at this time) so that the first signal line C[n-1] of the previous stage transmits the first signal of the previous stage. The transistor T1 is turned on, and the first signal transmission line C[n+1] of the subsequent stage transmits the first signal of the subsequent stage (its voltage is the first voltage V GL at this time), causing the second transistor T2 to turn off, and the first signal line of this stage is turned off. C[n] transmits the first signal of this stage (its voltage is the first voltage V GL at this time) to the fourth transistor T4 and the sixth transistor T6B. The sixth transistor T6B is therefore turned off, and the second signal line K[n] of this stage is Transmitting the second signal of this stage (its voltage is the first voltage V GL at this time) turns off the third transistor T3 and the eleventh transistor T11, and the voltage value of the voltage signal Q[n] of the first node N1 is V GH -V TH_T1 (V TH_T1 is the critical voltage of the first transistor T1). The voltage signal Q[n] of the first node N1 causes the voltage difference between the control terminal and the second terminal of the fourth transistor T4 to be greater than the critical voltage of the fourth transistor T4. The fourth The transistor T4 is turned on, and the voltage signal Q[n] of the first node N1 turns on the twelfth transistor T12. Since the control terminal of the fifth transistor T5 is connected to the first node N1, the voltage of the control terminal of the fifth transistor T5 is The voltage value of the voltage signal Q[n] at a node N1 causes the voltage difference between the second terminal and the control terminal of the fifth transistor T5 to be less than the critical voltage of the fifth transistor T5. The fifth transistor T5 is turned off, and the voltage signal G[n] at the output terminal ] is the second voltage V GH .
第二时脉信号线XCK传输第二时脉信号使第七晶体管T7B、第九晶体管T9B和第十晶体管T10导通，第三节点N3的电压信号P[n]的电压值为VGH-VTH_T7，第八晶体管T8B的控制端的电压为第三节点N3的电压信号P[n]，第八晶体管T8B的第二端和控制端的电压差小于第八晶体管T8B的临界电压，第八晶体管T8B关闭。The second clock signal line XCK transmits the second clock signal to turn on the seventh transistor T7B, the ninth transistor T9B and the tenth transistor T10. The voltage value of the voltage signal P[n] of the third node N3 is V GH -V TH_T7 , the voltage of the control terminal of the eighth transistor T8B is the voltage signal P[n] of the third node N3, the voltage difference between the second terminal of the eighth transistor T8B and the control terminal is less than the critical voltage of the eighth transistor T8B, and the eighth transistor T8B is turned off. .
请参阅图8A和图8B，其为本发明的栅极驱动电路的第二实施例于第二时间的示意图和本发明的栅极驱动电路的第二实施例于第二时间的信号波形图。如图8A和图8B所示，在第二时间P2，前一级第一信号(此时其电压为第一电压VGL)使第一晶体管T1关闭，后一级第一信号(此时其电压为第一电压VGL)使第二晶体管T2关闭，本级第一信号(此时其电压为第二电压VGH)使第六晶体管T6B导通，本级第二信号(此时其电压为第一电压VGL)使第三晶体管T3和第十一晶体管T11关闭，第一节点N1的电压信号Q[n]的电压值为电压VQ(其等于VGH-VTH_T1+ΔV)，第一节点N1的电压信号Q[n]造成第四晶体管T4的控制端和第二端的电压差大于第四晶体管T4的临界电压，第四晶体管T4导通，第一节点N1的电压信号Q[n]传输至第五晶体管T5的控制端，使第五晶体管T5的第二端和控制端的电压差小于第五晶体管T5的临界电压，第五晶体管T5关闭，输出端的电压信号G[n]的电压值为第一电压VGL，第一节点N1的电压信号Q[n]的电压值使第十二晶体管T12导通。Please refer to FIGS. 8A and 8B , which are schematic diagrams of the second embodiment of the gate driving circuit of the present invention at the second time and signal waveform diagrams of the second embodiment of the gate driving circuit of the present invention at the second time. As shown in Figure 8A and Figure 8B, at the second time P2, the first signal of the previous stage (at this time its voltage is the first voltage V GL ) turns off the first transistor T1, and the first signal of the subsequent stage (at this time its voltage The voltage is the first voltage V GL ) to turn off the second transistor T2, the first signal of this level (at this time its voltage is the second voltage V GH ) turns on the sixth transistor T6B, the second signal of this level (at this time its voltage is the first voltage V GL ) to turn off the third transistor T3 and the eleventh transistor T11, and the voltage value of the voltage signal Q[n] of the first node N1 is the voltage V Q (which is equal to V GH -V TH_T1 +ΔV), The voltage signal Q[n] of the first node N1 causes the voltage difference between the control terminal and the second terminal of the fourth transistor T4 to be greater than the critical voltage of the fourth transistor T4. The fourth transistor T4 is turned on, and the voltage signal Q[n] of the first node N1 n] is transmitted to the control terminal of the fifth transistor T5, so that the voltage difference between the second terminal and the control terminal of the fifth transistor T5 is less than the critical voltage of the fifth transistor T5, the fifth transistor T5 is turned off, and the voltage signal G[n] of the output terminal The voltage value is the first voltage V GL , and the voltage value of the voltage signal Q[n] at the first node N1 turns on the twelfth transistor T12.
第二时脉信号(此时其电压为第一电压VGL)使第七晶体管T7B、第九晶体管T9B和第十晶体管T10关闭，第三节点N3的电压信号P[n]的电压值为电压VVL，第三节点N3的电压信号P[n]传输至第八晶体管T8B的控制端，第一时脉信号的电压值为第二电压VGH，第八晶体管T8B的第二端和控制端的电压差大于第八晶体管的临界电压，第八晶体管T8B导通。The second clock signal (the voltage of which is the first voltage V GL at this time) turns off the seventh transistor T7B, the ninth transistor T9B and the tenth transistor T10, and the voltage value of the voltage signal P[n] of the third node N3 is voltage V VL , the voltage signal P[n] of the third node N3 is transmitted to the control terminal of the eighth transistor T8B, the voltage value of the first clock signal is the second voltage V GH , the second terminal of the eighth transistor T8B and the control terminal The voltage difference is greater than the critical voltage of the eighth transistor, and the eighth transistor T8B is turned on.
请参阅图9A和图9B，其为本发明的栅极驱动电路的第二实施例于第三时间的示意图以及本发明的栅极驱动电路的第二实施例于第三时间的信号波形图。如图9A和图9B所示，在第三时间P3，前一级第一信号(此时其电压为第一电压VGL)使第一晶体管T1关闭，后一级第一信号(此时其电压为第二电压VGH)使第二晶体管T2导通，本级第一信号(此时其电压为第一电压VGL)使第六晶体管T6B关闭，本级第二信号(此时其电压为第一电压VGL)使第三晶体管T3和第十一晶体管T11关闭，第一节点N1的电压信号Q[n]的电压值为第一电压VGL，第一节点N1的电压信号Q[n]传输至第四晶体管T4和第五晶体管T5的控制端，第二节点N2的电压为第一电压VGL，本级第一信号的第一电压VGL使第四晶体管T4的控制端电压小于其第二端的电压，第四晶体管T4关闭，第五晶体管T5的第二端和控制端的电压差大于第五晶体管T5的临界电压，第五晶体管T5导通，输出端的电压信号G[n]为第三电压VL，第一节点N1的电压信号Q[n]也传递至第十二晶体管T12的控制端，本级第一信号的第一电压VGL使第十二晶体管T12的控制端电压小于其第二端的电压，第十二晶体管T12关闭。Please refer to FIGS. 9A and 9B , which are schematic diagrams of the second embodiment of the gate driving circuit of the present invention at the third time and signal waveform diagrams of the second embodiment of the gate driving circuit of the present invention at the third time. As shown in Figure 9A and Figure 9B, at the third time P3, the first signal of the previous stage (at this time its voltage is the first voltage V GL ) turns off the first transistor T1, and the first signal of the subsequent stage (at this time its voltage The voltage is the second voltage V GH ) to turn on the second transistor T2, the first signal of this stage (at this time its voltage is the first voltage V GL ) turns off the sixth transistor T6B, the second signal of this stage (at this time its voltage is the first voltage V GL ) to turn off the third transistor T3 and the eleventh transistor T11, the voltage value of the voltage signal Q[n] of the first node N1 is the first voltage V GL , and the voltage signal Q[n] of the first node N1 n] is transmitted to the control terminals of the fourth transistor T4 and the fifth transistor T5, the voltage of the second node N2 is the first voltage V GL , and the first voltage V GL of the first signal of this stage causes the control terminal voltage of the fourth transistor T4 is less than the voltage at its second terminal, the fourth transistor T4 is turned off, the voltage difference between the second terminal and the control terminal of the fifth transistor T5 is greater than the critical voltage of the fifth transistor T5, the fifth transistor T5 is turned on, and the voltage signal G[n] at the output terminal is the third voltage V L , the voltage signal Q[n] of the first node N1 is also transmitted to the control end of the twelfth transistor T12 , and the first voltage V GL of the first signal of this stage causes the control end of the twelfth transistor T12 The voltage is less than the voltage at its second terminal, and the twelfth transistor T12 is turned off.
第二时脉信号使第七晶体管T7B、第九晶体管T9B和第十晶体管T10导通，第三节点N3的电压信号P[n]的电压值为VGH-VTH_T7，第三节点N3的电压信号P[n]大于第一时脉信号的电压值(此时其电压为第二电压VGH)，造成第八晶体管T8B的第二端和控制端的电压差小于第八晶体管T8B的临界电压，第八晶体管T8B关闭。The second clock signal turns on the seventh transistor T7B, the ninth transistor T9B and the tenth transistor T10. The voltage value of the voltage signal P[n] of the third node N3 is V GH -V TH_T7 . The voltage of the third node N3 The signal P[n] is greater than the voltage value of the first clock signal (its voltage is the second voltage V GH at this time), causing the voltage difference between the second terminal and the control terminal of the eighth transistor T8B to be less than the critical voltage of the eighth transistor T8B, The eighth transistor T8B is turned off.
请参阅图10A和图10B，其为本发明的栅极驱动电路的第二实施例于第四时间的示意图以及本发明的栅极驱动电路的第二实施例于第四时间的信号波形图。如图10A和图10B所示，在第四时间P4，前一级第一信号(此时其电压为第一电压VGL)使第一晶体管T1关闭，后一级第一信号(此时其电压为第一电压VGL)使第二晶体管T2关闭，本级第一信号(此时其电压为第一电压VGL)使第六晶体管T6B关闭，本级第二信号(此时其电压为电压Vk)使第三晶体管T3和第十一晶体管T11导通，第一节点N1的电压信号Q[n]为第一电压VGL，第一节点N1的电压信号Q[n]传输至第四晶体管T4和第五晶体管T5，第四晶体管T4关闭，第五晶体管T5的第二端和控制端的电压差大于第五晶体管T5的临界电压，第五晶体管T5导通，输出端的电压信号G[n]为第二电压VGH，第一节点N1的电压信号Q[n]也传递至第十二晶体管T12的控制端，第十二晶体管T12关闭。Please refer to FIG. 10A and FIG. 10B , which are schematic diagrams of the second embodiment of the gate driving circuit of the present invention at the fourth time and a signal waveform diagram of the second embodiment of the gate driving circuit of the present invention at the fourth time. As shown in Figure 10A and Figure 10B, at the fourth time P4, the first signal of the previous stage (at this time its voltage is the first voltage V GL ) turns off the first transistor T1, and the first signal of the subsequent stage (at this time its voltage The voltage is the first voltage V GL ) to turn off the second transistor T2, the first signal of this level (at this time its voltage is the first voltage V GL ) turns off the sixth transistor T6B, the second signal of this level (at this time its voltage is The voltage V k ) turns on the third transistor T3 and the eleventh transistor T11 , the voltage signal Q[n] of the first node N1 is the first voltage V GL , and the voltage signal Q[n] of the first node N1 is transmitted to the Four transistors T4 and fifth transistors T5, the fourth transistor T4 is turned off, the voltage difference between the second terminal and the control terminal of the fifth transistor T5 is greater than the critical voltage of the fifth transistor T5, the fifth transistor T5 is turned on, and the voltage signal G at the output terminal is [ n] is the second voltage V GH , the voltage signal Q[n] of the first node N1 is also transmitted to the control end of the twelfth transistor T12, and the twelfth transistor T12 is turned off.
第二时脉信号使第七晶体管T7B、第九晶体管T9B和第十晶体管T10关闭，第三节点N3的电压信号P[n]的电压值电压Vp，第三节点N3的电压信号P[n]传输至第八晶体管T8B的控制端，第八晶体管T8B的第二端和控制端的电压差小于第八晶体管T8B的临界电压，第八晶体管T8B关闭。当第一时脉信号的电压值为第二电压VGH，第二电容C2的耦合使第三节点N3的电压信号P[n]的电压值为电压Vp，确保晶体管T8关闭。The second clock signal turns off the seventh transistor T7B, the ninth transistor T9B and the tenth transistor T10. The voltage value of the voltage signal P[n] of the third node N3 is V p . The voltage signal P[n of the third node N3 is ] is transmitted to the control terminal of the eighth transistor T8B. The voltage difference between the second terminal and the control terminal of the eighth transistor T8B is less than the critical voltage of the eighth transistor T8B, and the eighth transistor T8B is turned off. When the voltage value of the first clock signal is the second voltage V GH , the coupling of the second capacitor C2 causes the voltage value of the voltage signal P[n] of the third node N3 to be the voltage V p , ensuring that the transistor T8 is turned off.
承上所述，本发明的栅极驱动电路，提供双向低频操作的功能及显示面板所需的扫描信号，无须额外电路辅助即能达成双向低频操作。As mentioned above, the gate drive circuit of the present invention provides the function of bidirectional low-frequency operation and the scanning signal required by the display panel, and can achieve bidirectional low-frequency operation without the need for additional circuit assistance.
以上所述仅为举例性，而非为限制性者。任何未脱离本发明的精神与范畴，而对其进行的等效修改或变更，均应包含于后附的申请专利范围中。The above is only illustrative and not restrictive. Any equivalent modifications or changes that do not depart from the spirit and scope of the present invention shall be included in the appended patent application scope.
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