CN101071246A - Liquid crystal display device, gate drive circuit and drive circuit unit thereof - Google Patents
Liquid crystal display device, gate drive circuit and drive circuit unit thereof Download PDFInfo
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- CN101071246A CN101071246A CN 200710127483 CN200710127483A CN101071246A CN 101071246 A CN101071246 A CN 101071246A CN 200710127483 CN200710127483 CN 200710127483 CN 200710127483 A CN200710127483 A CN 200710127483A CN 101071246 A CN101071246 A CN 101071246A
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Abstract
A drive circuit unit in a liquid crystal display device is manufactured on a glass substrate and used for outputting a drive signal, and the drive circuit unit comprises a first transistor, an auxiliary input unit and a second transistor. The gate terminal of the first transistor receives an input signal, the first terminal of the first transistor is electrically coupled to a voltage source, and the second terminal of the first transistor is used for outputting a first signal. The auxiliary input unit is electrically coupled to the second end of the first transistor, and receives the first signal and the timing signal to output a second signal. The gate terminal of the second transistor is electrically coupled to the auxiliary input unit and receives the second signal, the first terminal of the second transistor receives the timing signal, and the second terminal of the second transistor is used for outputting the driving signal. A liquid crystal display device and a gate driving circuit are also disclosed.
Description
[technical field]
The invention relates to a kind of driving circuit and drive circuit unit thereof, and particularly relevant for gate driver circuit in a kind of LCD and drive circuit unit thereof.
[background technology]
Recently be used for the gate driver circuit of LCD, its practice is to make the gate driver circuit that comprises a plurality of drive circuit units on glass substrate, and utilize these drive circuit units to export gate drive signal in regular turn to sweep trace, so just can replace and use general grid-driving integrated circuit (IC), and then save the expensive cost that uses gate driving IC.
Fig. 1 system illustrates the synoptic diagram of the drive circuit unit in the known gate driver circuit.At this is that drive circuit unit with the K level is an example, receives the gate drive signal SN that is exported from (K-1) stage drive circuit unit as transistor M1
K-1Afterwards, therefore conducting of transistor M1 makes the signal of voltage source V CC be sent to node P by transistor M1, uses turn-on transistor M2.Then, when treating that clock signal CLK is high levels, clock signal CLK is again by transistor M2 output, with as gate drive signal SN
KThis kind made the voltage of the gate terminal of the genealogy of law by drawing and lifting transistor M2, and then shortens the gate drive signal SN of output
KRise time (rising time); That is, when transistor M1 conducting, draw and lift the voltage of node P earlier, then when transistor M2 receives clock signal CLK, draw and lift the voltage of node P once more, quickening the time that transistor M2 opens, and shorten output signal SN
KRise time.
Yet, because it is very little to make its mobility of the employed amorphous silicon of thin film transistor (TFT) (a-Si), and generally only use the thin film transistor (TFT) of n type to use as switch, therefore after gate drive signal output, thin film transistor (TFT) also can't promptly cut out immediately, the fall time (falling time) of the gate drive signal of feasible output is long, and the gate drive signal that causes exporting can be overlapping in time with the gate drive signal of next stage output; That is two sweep trace meetings thereby driven simultaneously make that incorrect situation may take place to write data.
Therefore, be necessary to propose a kind of drive circuit unit, can use and improve the problem that sweep trace is driven simultaneously, avoid the situation of data write error mistake to take place.
[summary of the invention]
One of the present invention technology sample attitude system is about a kind of LCD drive circuits unit.This kind drive circuit unit system is made on the glass substrate, and in order to export a drive signal, it comprises a first transistor, an auxiliary input block and a transistor seconds.The gate terminal system of the first transistor receives an input signal, and its first end system is electrically coupled to a voltage source, and its second end system is in order to export one first signal.Auxiliary input block system is electrically coupled to second end of the first transistor, and receives first signal and a clock signal to export a secondary signal.The gate terminal system of transistor seconds is electrically coupled to auxiliary input block and receives secondary signal, and its first end system receives clock signal, and its second end system is in order to output drive signal.
Another technology sample attitude system of the present invention is about a kind of gate driver circuit.This kind gate driver circuit system is made on the glass substrate, and comprises a plurality of drive circuit units, and in order to driving the multi-strip scanning line in the LCD, and drive circuit unit is exported a gate drive signal respectively in regular turn to one of corresponding sweep trace.Each drive circuit unit comprises a first transistor, an auxiliary input block and a transistor seconds in addition.The gate terminal system of the first transistor receives the gate drive signal of being exported by the upper level drive circuit unit, and its first end system is electrically coupled to a voltage source, and its second end system is in order to export one first signal.Auxiliary input block system is electrically coupled to second end of the first transistor, and receives first signal and a clock signal to export a secondary signal.The gate terminal system of transistor seconds is electrically coupled to auxiliary input block and receives secondary signal, and its first end system receives clock signal, and its second end is in order to the output gate drive signal, and gate drive signal is sent to the next stage drive circuit unit.
Another technology sample attitude system of the present invention is about a kind of liquid crystal indicator.This kind liquid crystal indicator comprises many data lines, multi-strip scanning line, a datawire driver and a gate driver circuit.Sweep trace and data line intersect to form one and show array, and datawire driver then couples data line and produces a plurality of signal of video signal to data line.Gate driver circuit system is made on the glass substrate, and comprises a plurality of drive circuit units in order to the driven sweep line, and drive circuit unit is exported a gate drive signal respectively in regular turn to one of corresponding sweep trace.Each drive circuit unit comprises a first transistor, an auxiliary input block and a transistor seconds in addition.The gate terminal system of the first transistor receives the gate drive signal of being exported by the upper level drive circuit unit, and its first end system is electrically coupled to a voltage source, and its second end system is in order to export first signal.Auxiliary input block system is electrically coupled to second end of the first transistor, and receives first signal and a clock signal with the output secondary signal.The gate terminal system of transistor seconds is electrically coupled to auxiliary input block and receives secondary signal, and its first end system receives clock signal, and its second end is in order to the output gate drive signal, and gate drive signal is sent to the next stage drive circuit unit.
According to the present invention, application of aforementioned gate driver circuit and drive circuit unit thereof can be used the rise time of the gate drive signal of control output, avoid driving simultaneously two sweep traces and cause writing the incorrect situation of data and take place.
[description of drawings]
Fig. 1 system one of illustrates in the known gate driver circuit synoptic diagram of drive circuit unit.
Fig. 2 system illustrates the synoptic diagram according to liquid crystal indicator embodiment of the present invention.
Fig. 3 system illustrates the synoptic diagram of a kind of drive circuit unit among Fig. 2.
Fig. 4 system illustrates the synoptic diagram of another kind of drive circuit unit among Fig. 2.
Fig. 5 system illustrates the sequential chart of drive circuit unit action among Fig. 3.
[embodiment]
Please refer to Fig. 2, it illustrates the synoptic diagram according to a kind of liquid crystal indicator of the embodiment of the invention.Liquid crystal indicator 200 comprises many data line D
1D
N, multi-strip scanning line G
1G
N, a datawire driver 202 and a gate driver circuit 204.Datawire driver 202 couples data line D
1D
N, and transmit a plurality of signal of video signal to data line D
1D
N Gate driver circuit 204 is to be made on the glass substrate (not illustrating), and comprises a plurality of drive circuit units 210 in order to driven sweep line G
1G
N, and export gate drive signal SN in regular turn respectively
1SN
NTo corresponding sweep trace G
1G
NData line D
1D
NWith sweep trace G
1G
NBe staggered to form demonstration array 220, and this shows that array 220 is according to data line D
1D
NMiddle signal of video signal and the sweep trace G that transmits
1G
NThe middle gate drive signal that transmits shows image.
Fig. 3 system illustrates the synoptic diagram of a kind of drive circuit unit among Fig. 2.Present embodiment system is an example with the drive circuit unit of K level, and drive circuit unit comprises a transistor Q1, a transistor Q2 and an auxiliary input block 300a, and wherein transistor Q1 and Q2 are respectively N type metal-oxide-semiconductor (MOS) (NMOS) transistor.The gate terminal of transistor Q1 system receives the gate drive signal SN that is exported by (K-1) level-drive circuit unit of upper level-promptly
K-1, its drain electrode end system is electrically coupled to a voltage source V CC, and its source terminal is then in order to export one first signal FS.Auxiliary input block 300a is electrically coupled to the source terminal of transistor Q1, and receives its first a signal FS that exports and clock signal CLK, uses output one secondary signal SS.The gate terminal system of transistor Q2 is electrically coupled to auxiliary input block 300a, and receives secondary signal SS, and its drain electrode end system receives clock signal CLK, and its source terminal is then in order to output gate drive signal SN
KWith driven sweep line G
K, and with gate drive signal SN
KBeing sent to next stage one is in (K+1) level one drive circuit unit.
In addition, can comprise a transistor Q3 in addition among the auxiliary input block 300a, and transistor Q3 also is a nmos pass transistor in the present embodiment.The gate terminal system of transistor Q3 is electrically coupled to the source terminal of transistor Q1, and its drain electrode end system receives clock signal CLK, and its source terminal then is electrically coupled to the gate terminal of transistor Q2, and in order to output secondary signal SS.With preferred embodiment, transistor Q3 can be a large-sized nmos pass transistor, that is it has bigger channel width length than (W/L).
Please refer to Fig. 4, it illustrates the synoptic diagram of another kind of drive circuit unit among Fig. 2.Compared to Fig. 3, the auxiliary input block 300b of present embodiment can comprise a transistor Q4 and a transistor Q5 in addition, and wherein transistor Q4 and Q5 also are respectively a nmos pass transistor in the present embodiment.The gate terminal of transistor Q4 and Q5 all is electrically coupled to the source terminal of transistor Q1, the drain electrode end of transistor Q4 and Q5 all receives clock signal CLK, the source terminal of transistor Q4 and Q5 then all is electrically coupled to the gate terminal of transistor Q2, and in order to output secondary signal SS.With preferred embodiment, transistor Q4 and Q5 can be respectively a large-sized nmos pass transistor, and are different size respectively, that is have different channel width length than (W/L).
Below the operational scenario of drive circuit unit will be described with an embodiment, wherein the drive circuit unit of the drive circuit unit of Fig. 3 and Fig. 4 is roughly the same in action.Fig. 5 system illustrates the sequential chart of drive circuit unit action among Fig. 3.Please refer to Fig. 3 and Fig. 5, when at time t1, gate drive signal SN that upper level-promptly (K-1) level one drive circuit unit is exported
K-1Can be sent to transistor Q1, make transistor Q1 conducting.This moment, voltage source signal VCC can be by the source terminal output of transistor Q1, and being stored in the gate terminal of transistor Q3 as the first signal FS, and transistor Q3 is the state of conducting.Because the clock signal CLK that transistor Q3 is received at this moment system is positioned at the low level state, so node P also is positioned at the low level state, makes transistor Q2 still present closing state.
When the time when asking t2, because the clock signal CLK system that transistor Q3 is received is positioned at the high levels state, so clock signal CLK can be by the source terminal output of transistor Q3, with as secondary signal SS, and node P also is positioned at the high levels state, makes transistor Q2 conducting.At this moment, the source terminal output that clock signal CLK just can be by transistor Q2 is with as gate drive signal SN
KThus, just can come the charging rate of Control Node P by the size of design transistor Q3, that is the conducting speed of coming oxide-semiconductor control transistors Q2 by the size of design transistor Q3, and then the output time (rise time) of decision gate drive signal.
By the embodiment of the invention described above as can be known, use the rise time that this gate driver circuit and drive circuit unit thereof can be used the gate drive signal of control output, avoid driving simultaneously two sweep traces and cause writing the incorrect situation of data and take place.
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (15)
1. a LCD drive circuits unit is made on the glass substrate, and in order to export a drive signal, this drive circuit unit comprises:
One the first transistor has gate terminal, first end and second end, and this gate terminal system receives an input signal, and this first end system is in order to receive voltage signal, and this second end system is in order to export first signal;
One auxiliary input block is electrically coupled to second end of this first transistor, and receives this first signal and a clock signal, with the output secondary signal; And
One transistor seconds, have gate terminal, first end and second end, the gate terminal system of this transistor seconds is electrically coupled to this auxiliary input block and receives this secondary signal, first end system of this transistor seconds receives this clock signal, and second end system of this transistor seconds is in order to export this drive signal.
2. drive circuit unit according to claim 1 is characterized in that, this auxiliary input block comprises:
One the 3rd transistor, have gate terminal, first end and second end, the 3rd transistorized gate terminal is second end that is electrically coupled to this first transistor, the 3rd transistorized first end system receives this clock signal, and second end system of this transistor seconds is electrically coupled to the gate terminal of this transistor seconds and in order to export this secondary signal.
3. drive circuit unit according to claim 2, it is characterized in that, this the first transistor, this transistor seconds and the 3rd transistor are N type metal-oxide-semiconductor (MOS) (NMOS) transistor, and this first transistor, this transistor seconds and the 3rd transistorized first end are a drain electrode end, and this first transistor, this transistor seconds and the 3rd transistorized second end are the one source pole end.
4. drive circuit unit according to claim 1 is characterized in that, this auxiliary input block comprises:
One the 4th transistor has gate terminal, first end and second end, and the 4th transistorized gate terminal is second end that is electrically coupled to this first transistor, and the 4th transistorized first end is to receive this clock signal; And
One the 5th transistor has gate terminal, first end and second end, and the 5th transistorized gate terminal is second end that is electrically coupled to this first transistor, and the 5th transistorized first end is to receive this clock signal;
Wherein the 4th transistorized second end and the 5th transistorized second end all are electrically coupled to the gate terminal of this transistor seconds, and in order to export this secondary signal.
5. drive circuit unit according to claim 4, it is characterized in that, this the first transistor, this transistor seconds, the 4th transistor and the 5th transistor are nmos pass transistor, and this first transistor, this transistor seconds, the 4th transistor and the 5th transistorized first end are a drain electrode end, and this first transistor, this transistor seconds, the 4th transistor and the 5th transistorized second end are the one source pole end.
6. gate driver circuit, be made on the glass substrate, and comprise a plurality of drive circuit units, in order to drive the multi-strip scanning line in the LCD, and those drive circuit units are exported a gate drive signal respectively in regular turn to one of corresponding those sweep traces, and wherein each drive circuit unit comprises:
One the first transistor, have gate terminal, first end and second end, this gate terminal system receives this gate drive signal of being exported by the upper level drive circuit unit in those drive circuit units, and this first end system is in order to receive voltage signal, and this second end system is in order to export first signal;
One auxiliary input block is electrically coupled to second end of this first transistor, and receives this first signal and a clock signal, with the output secondary signal; And
One transistor seconds, have gate terminal, first end and second end, the gate terminal system of this transistor seconds is electrically coupled to this auxiliary input block and receives this secondary signal, first end system of this transistor seconds receives this clock signal, second end of this transistor seconds system is in order to exporting this gate drive signal, and this gate drive signal is sent to the next stage drive circuit unit.
7. gate driver circuit according to claim 6 is characterized in that, this auxiliary input block comprises in addition:
One the 3rd transistor, have gate terminal, first end and second end, the 3rd transistorized gate terminal is second end that is electrically coupled to this first transistor, the 3rd transistorized first end system receives this clock signal, and second end system of this transistor seconds is electrically coupled to the gate terminal of this transistor seconds and in order to export this secondary signal.
8. gate driver circuit according to claim 7, it is characterized in that, this the first transistor, this transistor seconds and the 3rd transistor are N type metal-oxide-semiconductor (MOS) (NMOS) transistor, and this first transistor, this transistor seconds and the 3rd transistorized first end are a drain electrode end, and this first transistor, this transistor seconds and the 3rd transistorized second end are the one source pole end.
9. gate driver circuit according to claim 6 is characterized in that, this auxiliary input block comprises in addition:
One the 4th transistor has gate terminal, first end and second end, and the 4th transistorized gate terminal is second end that is electrically coupled to this first transistor, and the 4th transistorized first end is to receive this clock signal; And
One the 5th transistor has gate terminal, first end and second end, and the 5th transistorized gate terminal is second end that is electrically coupled to this first transistor, and the 5th transistorized first end is to receive this clock signal;
Wherein the 4th transistorized second end and the 5th transistorized second end all are electrically coupled to the gate terminal of this transistor seconds, and in order to export this secondary signal.
10. gate driver circuit according to claim 9, it is characterized in that, this the first transistor, this transistor seconds, the 4th transistor and the 5th transistor are nmos pass transistor, and this first transistor, this transistor seconds, the 4th transistor and the 5th transistorized first end are a drain electrode end, and this first transistor, this transistor seconds, the 4th transistor and the 5th transistorized second end are the one source pole end.
11. a liquid crystal indicator comprises:
Many data lines;
The multi-strip scanning line intersects to form one with those data lines and shows array;
One datawire driver couples those data lines and produces a plurality of signal of video signal to those data lines; And
One gate driver circuit, be made on the glass substrate, and comprise a plurality of drive circuit units in order to driving those sweep traces, and those drive circuit units export a gate drive signal respectively in regular turn to one of corresponding those sweep traces, and wherein each drive circuit unit comprises:
One the first transistor, the gate terminal system of this first transistor receives this gate drive signal of being exported by the upper level drive circuit unit in those drive circuit units, first end system of this first transistor is electrically coupled to a voltage source, and second end system of this first transistor is in order to export one first signal;
One auxiliary input block is electrically coupled to second end of this first transistor, and receives this first signal and a clock signal to export a secondary signal; And
One transistor seconds, the gate terminal system of this transistor seconds is electrically coupled to this auxiliary input block and receives this secondary signal, first end system of this transistor seconds receives this clock signal, second end of this transistor seconds system is in order to exporting this gate drive signal, and this gate drive signal is sent to next stage drive circuit unit in those drive circuit units.
12. liquid crystal indicator according to claim 11 is characterized in that, this auxiliary input block comprises:
One the 3rd transistor, the 3rd transistorized gate terminal is second end that is electrically coupled to this first transistor, the 3rd transistorized first end system receives this clock signal, and second end system of this transistor seconds is electrically coupled to the gate terminal of this transistor seconds and in order to export this secondary signal.
13. liquid crystal indicator according to claim 12, it is characterized in that, this the first transistor, this transistor seconds and the 3rd transistor are nmos pass transistor, and this first transistor, this transistor seconds and the 3rd transistorized first end are a drain electrode end, and this first transistor, this transistor seconds and the 3rd transistorized second end are the one source pole end.
14. liquid crystal indicator according to claim 11 is characterized in that, this auxiliary input block comprises:
One the 4th transistor, the 4th transistorized gate terminal is second end that is electrically coupled to this first transistor, the 4th transistorized first end is to receive this clock signal; And
One the 5th transistor, the 5th transistorized gate terminal is second end that is electrically coupled to this first transistor, the 5th transistorized first end is to receive this clock signal;
Wherein the 4th transistorized second end and the 5th transistorized second end all are electrically coupled to the gate terminal of this transistor seconds, and in order to export this secondary signal.
15. liquid crystal indicator according to claim 14, it is characterized in that, this the first transistor, this transistor seconds, the 4th transistor and the 5th transistor are nmos pass transistor, and this first transistor, this transistor seconds, the 4th transistor and the 5th transistorized first end are a drain electrode end, and this first transistor, this transistor seconds, the 4th transistor and the 5th transistorized second end are the one source pole end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101274831A CN100483241C (en) | 2007-06-28 | 2007-06-28 | Liquid crystal display device, gate drive circuit and drive circuit unit thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101274831A CN100483241C (en) | 2007-06-28 | 2007-06-28 | Liquid crystal display device, gate drive circuit and drive circuit unit thereof |
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| Publication Number | Publication Date |
|---|---|
| CN101071246A true CN101071246A (en) | 2007-11-14 |
| CN100483241C CN100483241C (en) | 2009-04-29 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007101274831A Active CN100483241C (en) | 2007-06-28 | 2007-06-28 | Liquid crystal display device, gate drive circuit and drive circuit unit thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102842278A (en) * | 2012-08-06 | 2012-12-26 | 北京大学深圳研究生院 | Gate drive circuit unit, gate drive circuit and display |
| CN111341282A (en) * | 2019-10-23 | 2020-06-26 | 友达光电股份有限公司 | Pixel circuit |
| CN111417895A (en) * | 2017-12-22 | 2020-07-14 | 株式会社半导体能源研究所 | Display device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5712653A (en) * | 1993-12-27 | 1998-01-27 | Sharp Kabushiki Kaisha | Image display scanning circuit with outputs from sequentially switched pulse signals |
| TW491988B (en) * | 2001-03-21 | 2002-06-21 | Century Semiconductor Inc | Single-ended high voltage level shifters applied in TET-LCD gate drivers |
| AU2003241202A1 (en) * | 2002-06-10 | 2003-12-22 | Samsung Electronics Co., Ltd. | Shift register, liquid crystal display device having the shift register and method of driving scan lines using the same |
-
2007
- 2007-06-28 CN CNB2007101274831A patent/CN100483241C/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102842278A (en) * | 2012-08-06 | 2012-12-26 | 北京大学深圳研究生院 | Gate drive circuit unit, gate drive circuit and display |
| CN111417895A (en) * | 2017-12-22 | 2020-07-14 | 株式会社半导体能源研究所 | Display device |
| CN111417895B (en) * | 2017-12-22 | 2023-06-16 | 株式会社半导体能源研究所 | Display device |
| CN111341282A (en) * | 2019-10-23 | 2020-06-26 | 友达光电股份有限公司 | Pixel circuit |
| CN111341282B (en) * | 2019-10-23 | 2022-05-03 | 友达光电股份有限公司 | pixel circuit |
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| Publication number | Publication date |
|---|---|
| CN100483241C (en) | 2009-04-29 |
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