JPH09321043A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH09321043A JPH09321043A JP8133026A JP13302696A JPH09321043A JP H09321043 A JPH09321043 A JP H09321043A JP 8133026 A JP8133026 A JP 8133026A JP 13302696 A JP13302696 A JP 13302696A JP H09321043 A JPH09321043 A JP H09321043A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- resist
- forming
- wirings
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置の製造
方法、特に化学的機械研磨法による平坦化をおこなう半
導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device which is planarized by a chemical mechanical polishing method.
【０００２】[0002]
【従来の技術】従来の半導体製造工程における半導体基
板上の絶縁膜の平坦化について、図２を参照にして説明
する。図２は、従来の半導体装置の断面図である。図２
（ａ）に示されるように、半導体基板１０１の表面上に
図示せぬ絶縁膜を形成し、金属膜を蒸着する。次に、図
示せぬレジストを用いて光露光技術を用いてレジストの
パターニングを行う。その結果形成されたパターンを基
に、エッチングを行い配線１０２を形成する。配線１０
２の形成後に半導体基板１０１及び配線１０２の表面上
に層間絶縁膜１０３を形成し、その後ＣＭＰ（Chemical
Mechanical Polishing ）法により層間絶縁膜１０３表
面の平坦化を行う。2. Description of the Related Art The planarization of an insulating film on a semiconductor substrate in a conventional semiconductor manufacturing process will be described with reference to FIG. FIG. 2 is a sectional view of a conventional semiconductor device. FIG.
As shown in (a), an insulating film (not shown) is formed on the surface of the semiconductor substrate 101, and a metal film is deposited. Next, resist patterning is performed by using a light exposure technique using a resist (not shown). Based on the pattern formed as a result, etching is performed to form the wiring 102. Wiring 10
2 is formed, an interlayer insulating film 103 is formed on the surfaces of the semiconductor substrate 101 and the wiring 102, and then CMP (Chemical
The surface of the interlayer insulating film 103 is planarized by the mechanical polishing method.
【０００３】このＣＭＰ法は、ＬＳＩ（Large Scale In
tegrated circuit）の微細化に伴い要求される半導体基
板１０１表面の平坦化に関する技術であり、化学研磨剤
を滴下した研磨布上に半導体基板１０１を載せ、この半
導体基板１０１に荷重を加え、半導体基板１０１表面の
凹凸を化学機械的に研磨して平坦化するものである。This CMP method is an LSI (Large Scale In
This is a technique relating to the flattening of the surface of the semiconductor substrate 101 which is required with the miniaturization of an integrated circuit. The semiconductor substrate 101 is placed on a polishing cloth on which a chemical polishing agent has been dropped, and a load is applied to the semiconductor substrate 101. 101 The surface unevenness is planarized by chemical mechanical polishing.
【０００４】層間絶縁膜１０３を形成した際に、下地の
配線１０２層の凹凸によって層間絶縁膜１０３に凹凸が
生じる場合がある。ＣＭＰ法により平坦化を行う場合、
配線１０２間の段差領域１０４に研磨剤が入り込み、研
磨布の硬度、配線１０２間の距離等の要素によって段差
領域１０４にも荷重が加わり、図２（ｂ）に示されるよ
うに、段差領域１０４も配線領域１０５と同様に研磨さ
れてしまうというディッシング現象が見られることがあ
る。従って、配線１０２が配置されている配線領域１０
５と、配線１０２間の段差領域１０４との絶対的段差は
解消されない可能性がある。When the inter-layer insulation film 103 is formed, the inter-layer insulation film 103 may have irregularities due to the irregularities of the underlying wiring 102 layer. When flattening by the CMP method,
Abrasive enters the step region 104 between the wirings 102, and a load is applied to the step region 104 due to factors such as the hardness of the polishing cloth and the distance between the wirings 102. As shown in FIG. In some cases, a dishing phenomenon in which the same is polished as in the wiring region 105 can be seen. Therefore, the wiring region 10 in which the wiring 102 is arranged is
5 and the absolute level difference between the step region 104 between the wirings 102 may not be eliminated.
【０００５】多層配線を形成しようとする場合に、ディ
ッシング現象が起こり、下層配線層の上の層間絶縁膜１
０３の表面上に凹凸が見られると、その段差によって上
層配線と下層配線の間が断線してしまう可能性がある。
また、凹凸があるまま上層配線となる金属を形成し、パ
ターニングすると、段差部の側壁に金属の残瑳が生じ、
本来絶縁状態にあるべき配線１０２同士がショートして
しまうことがある。従って、従来、このディッシング現
象を防止するために、図３の従来の半導体装置に示され
るように、段差領域１０４にダミーパターン１０６を配
置する方法がある。When attempting to form a multi-layered wiring, a dishing phenomenon occurs, and the interlayer insulating film 1 on the lower wiring layer is formed.
If unevenness is seen on the surface of 03, the step may cause disconnection between the upper layer wiring and the lower layer wiring.
Further, if a metal to be the upper layer wiring is formed with the unevenness and is patterned, a metal residue is generated on the side wall of the step portion,
In some cases, the wirings 102, which should be originally in an insulating state, may short-circuit. Therefore, conventionally, there is a method of arranging the dummy pattern 106 in the step region 104 as shown in the conventional semiconductor device of FIG. 3 in order to prevent the dishing phenomenon.
【０００６】まず、配置される配線１０２のレイアウト
を基にして、計算機処理により配線１０２間の距離が大
きい領域を抽出する。次に、配線１０２と同じ材料の金
属を用いて、配線１０２を形成するのと同一工程で、配
線領域１０５と擬似的な配線模様のダミーパターン１０
６を形成する。その後、半導体基板１０１表面上に層間
絶縁膜１０３を形成すれば、配線１０２間に形成される
層間絶縁膜１０３の段差が解消される。従って、ＣＭＰ
法により平坦化を行っても、ディッシング現象が生じ
ず、層間絶縁膜１０３の表面上は均一に平坦となる。First, an area having a large distance between the wirings 102 is extracted by computer processing based on the layout of the wirings 102 to be arranged. Next, in the same step as forming the wiring 102 using the same metal as the wiring 102, the dummy pattern 10 having a pseudo wiring pattern with the wiring region 105 is formed.
6 is formed. After that, when the interlayer insulating film 103 is formed on the surface of the semiconductor substrate 101, the step of the interlayer insulating film 103 formed between the wirings 102 is eliminated. Therefore, CMP
Even if planarization is performed by the method, the dishing phenomenon does not occur and the surface of the interlayer insulating film 103 is uniformly flattened.
【０００７】[0007]
【発明が解決しようとする課題】上記の製造方法によれ
ば、ダミーパターン１０６は配線１０２と同じ材料の導
体であるため、このダミーパターン１０６及び配線１０
２が電極となって、その間の層間絶縁膜１０３が誘電体
となり、ダミーパターン１０６と配線１０２との間に容
量が生じ、ＬＳＩの動作が遅くなってしまうという問題
があった。According to the manufacturing method described above, since the dummy pattern 106 is a conductor made of the same material as the wiring 102, the dummy pattern 106 and the wiring 10 are not formed.
2 serves as an electrode, and the interlayer insulating film 103 between them serves as a dielectric, and a capacitance is generated between the dummy pattern 106 and the wiring 102, which causes a problem that the operation of the LSI is delayed.
【０００８】従って、この容量を減少させるために配線
１０２のレイアウトを基に容量計算を更に行い、論理的
にダミーパターン１０６の配置を決定する必要が生じる
が、その論理合成を行うのには複雑な計算を行わなけれ
ばならず、計算機処理に時間がかかり、製造工程が完了
するまでに時間がかかるという問題があった。Therefore, in order to reduce this capacitance, it is necessary to further perform capacitance calculation based on the layout of the wiring 102 and logically determine the placement of the dummy pattern 106, but it is complicated to perform the logic synthesis. However, there is a problem in that it takes time to perform computer processing and it takes time to complete the manufacturing process.
【０００９】また、パターンミスや製造工程の不具合が
発生して配線１０２とダミーパターン１０６が接触した
場合、ダミーパターン１０６が導体であるため、ショー
トし回路が正常に動作しなくなり、また、ショートして
いる場合でも、レイアウト上の何処で配線１０２とダミ
ーパターン１０６との間がショートしているかを検証す
ることも難しい。When the wiring 102 and the dummy pattern 106 come into contact with each other due to a pattern error or a defect in the manufacturing process, the dummy pattern 106 is a conductor, so that a short circuit occurs and the circuit does not operate normally. However, it is difficult to verify where on the layout the wiring 102 and the dummy pattern 106 are short-circuited.
【００１０】本発明は上記のような事情を考慮し、ダミ
ーパターンを配置する位置を決定する計算機処理を行う
必要がなく、また、配線１０２とダミーパターン１０６
との間のショートが発生しない半導体装置の製造方法を
提供することを目的とする。In consideration of the above circumstances, the present invention does not need to perform the computer processing for determining the position where the dummy pattern is arranged, and the wiring 102 and the dummy pattern 106.
It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a short circuit between and does not occur.
【００１１】[0011]
【課題を解決するための手段】上記目的を達成するため
に本発明の半導体装置の製造方法は、半導体基板上に第
１及び第２配線を形成する工程と、前記半導体基板、前
記第１及び第２配線上に、前記第１及び第２配線と同等
の厚さを有する絶縁膜を形成する工程と、前記第１及び
第２配線間にエッチングマスクを形成する工程と、前記
エッチングマスクをマスクにエッチングを行い、前記第
１及び第２配線間にダミーパターンを形成する工程とを
具備したことを特徴とするものである。In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming first and second wirings on a semiconductor substrate, the semiconductor substrate, the first and second wirings. Forming an insulating film having the same thickness as the first and second wirings on the second wiring; forming an etching mask between the first and second wirings; and masking the etching mask And forming a dummy pattern between the first and second wirings.
【００１２】更に、前記エッチングマスクを形成するマ
スクは、前記第１及び第２配線と同程度以上の線幅及び
間隔を持つパターンを半導体基板上の全面に有すること
が望ましい。Further, it is preferable that the mask forming the etching mask has a pattern having a line width and a spacing which are equal to or larger than those of the first and second wirings on the entire surface of the semiconductor substrate.
【００１３】また、半導体基板上に第１及び第２配線を
形成する工程と、前記半導体基板、前記第１及び第２配
線上に、前記第１及び第２配線と同等の厚さを有する絶
縁膜を形成する工程と、前記絶縁膜上にレジストを形成
し、前記第１及び第２配線間にレジストパターンを形成
する工程と、前記レジストパターンをマスクにエッチン
グを行い、前記第１及び第２配線間にダミーパターンを
形成する工程とを具備したことを特徴とする半導体装置
の製造方法がある。In addition, the step of forming the first and second wirings on the semiconductor substrate, and the insulation having the same thickness as the first and second wirings on the semiconductor substrate and the first and second wirings. A step of forming a film, a step of forming a resist on the insulating film and forming a resist pattern between the first and second wirings, an etching using the resist pattern as a mask, And a step of forming a dummy pattern between the wirings.
【００１４】また、前記レジストは、前記第１及び第２
配線間に前記ダミーパターンを形成するためのマスクと
なる粘度を有することが望ましい。更に、前記レジスト
は、粘度が５０センチポアズ程度以下であるとよい。The resist is composed of the first and second resists.
It is desirable to have a viscosity that serves as a mask for forming the dummy pattern between the wirings. Furthermore, the resist preferably has a viscosity of about 50 centipoise or less.
【００１５】また、半導体基板上に配線領域を形成する
工程と、前記配線領域及び非配線領域上に、前記配線領
域と同等の厚さを有する絶縁膜を形成する工程と、前記
絶縁膜上にレジストを形成し、マスクを用いて半導体基
板上の全面を光露光する工程と、前記レジストを現像
し、レジストパターンを形成する工程と、前記レジスト
パターンをマスクにエッチングを行い、前記非配線領域
にダミーパターンを形成する工程とを具備したことを特
徴とする半導体装置の製造方法がある。Further, a step of forming a wiring region on the semiconductor substrate, a step of forming an insulating film having the same thickness as the wiring region on the wiring region and the non-wiring region, and a step of forming an insulating film on the insulating film. A step of forming a resist and exposing the entire surface of the semiconductor substrate to light using a mask, a step of developing the resist to form a resist pattern, and an etching using the resist pattern as a mask to form a non-wiring region And a step of forming a dummy pattern.
【００１６】更に、前記光露光する工程において、焦点
を前記非配線領域の前記絶縁膜と前記レジストとの境界
面に合わせることが望ましい。また、前記レジストパタ
ーンを形成するマスクは、前記配線領域と同程度以上の
線幅及び間隔を持つパターンを半導体基板上の全面に有
することが望ましい。Further, in the step of exposing to light, it is desirable that the focus is adjusted to the boundary surface between the insulating film and the resist in the non-wiring region. Further, it is preferable that the mask for forming the resist pattern has a pattern having a line width and a spacing that are substantially equal to or larger than those of the wiring region on the entire surface of the semiconductor substrate.
【００１７】[0017]
【発明の実施の形態】以下、図面を参照して本発明の実
施の形態に係る半導体装置の製造方法について説明す
る。図１（ａ）乃至（ｅ）は、本発明の実施の形態に係
る半導体装置の製造工程を示した図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. 1A to 1E are views showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.
【００１８】図１（ａ）に示されているように、半導体
基板上１に図示せぬ絶縁膜を形成し、配線材料、例えば
Ａｌ−Ｓｉ−Ｃｕを６００ｎｍ程度蒸着させる。次に、
表面上に図示せぬレジストを形成し、光露光技術を用い
てレジストのパターニングを行う。その結果形成された
パターンを基に、配線材料のエッチングを行い配線２を
形成する。配線２の形成後、配線２と同等の厚み、すな
わち厚さ６００ｎｍ程度の層間絶縁膜３をＬＰ−ＣＶＤ
（Low Pressure-Chemical Vapour Deposition）法によ
り形成する。その結果、配線２の厚さによって、配線２
が形成されている配線領域５では、層間絶縁膜３の断面
形状は凸となり、配線２間の距離が例えば最小配線間隔
の約１０倍以上離れている段差領域４の層間絶縁膜３の
断面形状は凹となる。その後、層間絶縁膜３の上に５０
ＣＰ（センチポアズ）程度の粘性の低いレジスト６を形
成する。As shown in FIG. 1A, an insulating film (not shown) is formed on the semiconductor substrate 1 and a wiring material such as Al--Si--Cu is vapor-deposited to a thickness of about 600 nm. next,
A resist (not shown) is formed on the surface, and the resist is patterned by using a light exposure technique. Based on the pattern formed as a result, the wiring material is etched to form the wiring 2. After the wiring 2 is formed, the interlayer insulating film 3 having the same thickness as the wiring 2, that is, a thickness of about 600 nm is formed by LP-CVD.
(Low Pressure-Chemical Vapor Deposition) method. As a result, depending on the thickness of the wiring 2, the wiring 2
In the wiring region 5 in which is formed, the cross-sectional shape of the interlayer insulating film 3 becomes convex, and the cross-sectional shape of the interlayer insulating film 3 in the step region 4 in which the distance between the wirings 2 is, for example, about 10 times or more the minimum wiring distance Becomes concave. Then, on the interlayer insulating film 3, 50
A resist 6 having a viscosity as low as CP (centipoise) is formed.
【００１９】次に、図１（ｂ）に示されているように、
半導体基板１上の全面に、例えば、配線２の最小線幅及
び最小間隔と同程度の大きさである線幅約０．４μｍ程
度及び間隔約０．５μｍ程度のパターンを全面にもつマ
スク７を用意する。次に、焦点を配線２間の段差領域４
に形成された層間絶縁膜３とレジスト６との境界面８に
合わせて光露光を行う。Next, as shown in FIG.
For example, a mask 7 having, on the entire surface of the semiconductor substrate 1, a pattern having a line width of about 0.4 μm and an interval of about 0.5 μm, which are about the same as the minimum line width and the minimum interval of the wiring 2. prepare. Next, the focus is focused on the step region 4 between the wirings 2.
Photoexposure is performed in accordance with the boundary surface 8 between the interlayer insulating film 3 and the resist 6 formed in the above.
【００２０】次に、図１（ｃ）に示されているように、
露光されたレジスト６を現像する。焦点を段差領域４の
層間絶縁膜３とレジスト６との境界面８に合わせたの
で、配線領域５上のレジスト６は、きれいに解像されず
全面が現像され、一方、段差領域４上にはレジストパタ
ーン９が形成される。Next, as shown in FIG. 1 (c),
The exposed resist 6 is developed. Since the focus is set on the boundary surface 8 between the interlayer insulating film 3 and the resist 6 in the step region 4, the resist 6 on the wiring region 5 is not completely resolved and the entire surface is developed, while on the step region 4, A resist pattern 9 is formed.
【００２１】次に、図１（ｄ）に示されているように、
レジストパターン９をマスクにしてＣＨＦ3及びＣＦ4の
混合ガスを用いて、ＲＩＥ（Reactive Ion Etching）法
により層間絶縁膜３をエッチングする。その後レジスト
６を剥離すると、段差領域４に、配線領域５とほぼ同じ
厚さの層間絶縁膜３によるダミーパターン１０が形成さ
れる。Next, as shown in FIG. 1 (d),
Using the resist pattern 9 as a mask and using a mixed gas of CHF 3 and CF 4 , the interlayer insulating film 3 is etched by the RIE (Reactive Ion Etching) method. After that, when the resist 6 is peeled off, a dummy pattern 10 made of the interlayer insulating film 3 having substantially the same thickness as the wiring region 5 is formed in the step region 4.
【００２２】その後、図１（ｅ）に示されているよう
に、層間絶縁膜３の上に、ＬＰ−ＣＶＤ法により再度層
間絶縁膜１１を形成する。次に、ＣＭＰ法によって層間
絶縁膜１１表面の平坦化をおこなう。以上により、本発
明の実施の形態にかかる半導体装置の製造工程が終了す
る。Thereafter, as shown in FIG. 1E, the interlayer insulating film 11 is formed again on the interlayer insulating film 3 by the LP-CVD method. Next, the surface of the interlayer insulating film 11 is flattened by the CMP method. As described above, the manufacturing process of the semiconductor device according to the embodiment of the present invention is completed.
【００２３】本発明では、下地にダミーパターン１０が
形成されているため、ＣＭＰ法による平坦化工程の前
に、既に層間絶縁膜１１の表面は凹凸が減少している。
また、ダミーパターン１０は層間絶縁膜３により形成さ
れているため、ダミーパターン１０と配線２との間の容
量を考慮する必要がなく、また、パターンミスにより配
線２とダミーパターン１０とが接触した場合でも、ショ
ートする心配がない。In the present invention, since the dummy pattern 10 is formed on the base, the surface of the interlayer insulating film 11 has already been reduced in roughness before the flattening step by the CMP method.
Further, since the dummy pattern 10 is formed of the interlayer insulating film 3, it is not necessary to consider the capacitance between the dummy pattern 10 and the wiring 2, and the wiring 2 and the dummy pattern 10 are brought into contact with each other due to a pattern mistake. Even if you don't worry about short circuits.
【００２４】また、ダミーパターン１０を形成する際、
配線２の最小線幅及び最小間隔と同程度の線幅及び間隔
を有するパターンを全面にもつマスク７を用いてマスク
となるレジストパターン９を形成し、段差領域４にレジ
ストパターン９に準じたサイズのダミーパターン１０が
形成できるため、従来のように、配線２のレイアウトか
らダミーパターン１０の配置を決定する計算機処理をお
こなう必要がなくなる。従って、論理合成に時間をかけ
ることなく、また、配線２のレイアウトによらず、ダミ
ーパターン１０が等間隔になるように配置することがで
き、段差領域４の段差を解消することができる。When forming the dummy pattern 10,
A resist pattern 9 serving as a mask is formed by using a mask 7 having a pattern having a line width and a spacing that are similar to the minimum line width and the spacing of the wiring 2, and the size corresponding to the resist pattern 9 is formed in the step region 4. Since the dummy pattern 10 can be formed, it is not necessary to perform a computer process for determining the layout of the dummy pattern 10 from the layout of the wiring 2 as in the conventional case. Therefore, it is possible to arrange the dummy patterns 10 at equal intervals regardless of the layout of the wiring 2 without spending time for the logic synthesis, and it is possible to eliminate the step in the step region 4.
【００２５】また、粘性が低いレジスト６を用いること
によって、配線領域５にはレジスト６が薄く塗布され、
段差領域４にはレジスト６が厚く塗布されることにな
る。更に、焦点を配線２間の距離が大きい段差領域４に
形成された層間絶縁膜３とレジスト６との境界面８に合
わせて、焦点深度の小さい光露光を行うと、焦点の合わ
ない配線領域５上のレジスト６にはパターンがきれいに
解像されず、全面が現像されてしまう。従って、レジス
ト６をエッチングすると配線領域５に形成されたレジス
ト６はすべて剥離され、段差領域４にのみレジストパタ
ーン９が形成されることになる。すなわち、規則的な配
線模様のパターンがマスク７全面にわたって形成されて
いるとしても、半導体基板１上には、パターンが必要と
される配線２間の段差領域４にのみレジストパターン９
が形成されることになる。Further, by using the resist 6 having low viscosity, the resist 6 is thinly applied to the wiring region 5,
The resist 6 is applied thickly to the step region 4. Further, when the focus is adjusted to the boundary surface 8 between the interlayer insulating film 3 and the resist 6 formed in the step region 4 where the distance between the wirings 2 is large, and the light exposure with a small depth of focus is performed, the wiring area where the focus is not achieved. The pattern is not finely resolved on the resist 6 on 5 and the entire surface is developed. Therefore, when the resist 6 is etched, all the resist 6 formed in the wiring region 5 is peeled off, and the resist pattern 9 is formed only in the step region 4. That is, even if a regular wiring pattern is formed over the entire surface of the mask 7, the resist pattern 9 is formed only on the step region 4 between the wirings 2 where the pattern is required on the semiconductor substrate 1.
Is formed.
【００２６】また、層間絶縁膜３を配線２の厚さ以上に
形成することによって、段差領域４に層間絶縁膜３によ
るダミーパターン１０を形成した際に、配線２が形成さ
れている配線領域５とダミーパターン１０が形成された
配線２間の段差領域４との間の段差が減少するため、層
間絶縁膜３の表面上に形成する層間絶縁膜１１の表面の
凹凸が減少する。従って、ＣＭＰを行うことによって、
層間絶縁膜１１の表面を更に段差なく平坦化することが
可能である。Further, by forming the interlayer insulating film 3 to be thicker than the thickness of the wiring 2, when the dummy pattern 10 is formed by the interlayer insulating film 3 in the step region 4, the wiring region 5 in which the wiring 2 is formed is formed. Since the step between the wiring and the step region 4 between the wirings 2 on which the dummy pattern 10 is formed is reduced, the unevenness of the surface of the interlayer insulating film 11 formed on the surface of the interlayer insulating film 3 is reduced. Therefore, by performing CMP,
The surface of the interlayer insulating film 11 can be further flattened without any step.
【００２７】また、レジストパターン９をマスクにして
層間絶縁膜３をエッチングする際に、半導体基板１の保
護のために半導体基板１の表面付近の層間絶縁膜３を残
してもよい。When the interlayer insulating film 3 is etched using the resist pattern 9 as a mask, the interlayer insulating film 3 near the surface of the semiconductor substrate 1 may be left for protection of the semiconductor substrate 1.
【００２８】また、マスク７のパターンの線幅及び間隔
は、配線２間の段差領域４内に少なくともパターンが１
つ形成されるようにすればよく、配線２の最小線幅及び
最小間隔と同程度か、それ以上であるとよい。また、レ
ジスト６は、ポジ型でも、ネガ型でもよい。Further, the line width and the space of the pattern of the mask 7 are such that at least the pattern is within the step region 4 between the wirings 2.
The minimum line width and the minimum interval of the wiring 2 are about the same or more. Further, the resist 6 may be a positive type or a negative type.
【００２９】[0029]
【発明の効果】本発明によれば、一定の線幅及び間隔を
有するパターンを全面にもつマスクを用いて、配線間の
段差が生じる領域に絶縁膜のダミーパターンを形成する
ことによって、配線間の容量を考慮した計算機処理を行
う必要がなく配線とのショートの心配が無い、半導体基
板の表面が段差なく平坦化された半導体装置の製造方法
を実現することができる。According to the present invention, by using a mask having a pattern having a constant line width and a constant spacing on the entire surface, a dummy pattern of an insulating film is formed in a region where a step between wirings is generated, It is possible to realize a method for manufacturing a semiconductor device in which the surface of the semiconductor substrate is flattened without any step, and there is no need to perform a computer process in consideration of the capacitance of the above, there is no fear of short-circuiting with wiring.
【図１】本発明の半導体装置の製造工程図。FIG. 1 is a manufacturing process diagram of a semiconductor device of the present invention.
【図２】従来の半導体装置の製造工程図。FIG. 2 is a manufacturing process diagram of a conventional semiconductor device.
【図３】従来のダミーパターンを有する半導体装置の断
面図。FIG. 3 is a cross-sectional view of a conventional semiconductor device having a dummy pattern.
１，１０１…半導体基板、 ２，１０２…配線、 ３，１１，１０３…層間絶縁膜、 ４，１０４…段差領域、 ５，１０５…配線領域、 ６…レジスト、 ７…マスク、 ８…境界面、 ９…レジストパターン、 １０，１０６…ダミーパターン 1, 101 ... Semiconductor substrate, 2, 102 ... Wiring, 3, 11, 103 ... Interlayer insulating film, 4, 104 ... Step area, 5, 105 ... Wiring area, 6 ... Resist, 7 ... Mask, 8 ... Boundary surface, 9 ... Resist pattern, 10, 106 ... Dummy pattern
Claims (6)
上に前記凸部の高さ以上の厚さを有する第１絶縁膜を形
成する工程と、 前記第１絶縁膜上に前記凹部が覆われるようにレジスト
を形成する工程と、 前記凸部間の間隔以下の線幅をもつパターンを有する露
光マスクを用いて前記レジストを露光する工程と、 前記露光されたレジストを現像し、前記凹部にレジスト
パターンを形成する工程と、 前記レジストパターンをマスクにして、前記第１絶縁膜
の凸部を前記第１絶縁膜の凹部と同程度の高さまでエッ
チングする工程と、 前記第１絶縁膜上に第２絶縁膜を形成する工程とを具備
したことを特徴とする半導体装置の製造方法。1. A step of forming a first insulating film having a thickness equal to or higher than a height of the convex portion on a semiconductor substrate having a convex portion and a concave portion on a surface, and the concave portion covering the first insulating film. Forming a resist as described above, exposing the resist using an exposure mask having a pattern having a line width equal to or less than the interval between the convex portions, developing the exposed resist to form the concave portion. Forming a resist pattern; using the resist pattern as a mask, etching the convex portions of the first insulating film to the same height as the concave portions of the first insulating film; and forming a resist pattern on the first insulating film. And a step of forming a second insulating film.
焦点を前記凹部の前記第１絶縁膜と前記レジストとの境
界面に合わせることを特徴とする請求項１記載の半導体
装置の製造方法。2. In the step of exposing the resist,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the focus is on the boundary surface between the first insulating film and the resist in the recess.
は、一定の間隔及び線幅をもつパターンを全面に有する
ことを特徴とする請求項１記載の半導体装置の製造方
法。3. The method of manufacturing a semiconductor device according to claim 1, wherein the mask for forming the resist pattern has a pattern having a constant interval and a line width on the entire surface.
する工程と、 前記半導体基板、前記第１及び第２配線上に、前記第１
及び第２配線の高さ以上の厚さを有する第１絶縁膜を形
成する工程と、 前記第１及び第２配線間にレジストパターンを形成する
工程と、 前記レジストパターンを用いて前記第１絶縁膜をパター
ニングし、前記第１及び第２配線間にダミーパターンを
形成する工程と、 前記第１絶縁膜上に第２絶縁膜を形成する工程とを具備
したことを特徴とする半導体装置の製造方法。4. A step of forming first and second wirings on a semiconductor substrate; and a step of forming the first and second wirings on the semiconductor substrate and the first and second wirings.
And a step of forming a first insulating film having a thickness not less than the height of the second wiring, a step of forming a resist pattern between the first and second wirings, and the first insulation using the resist pattern. Manufacturing a semiconductor device, comprising: patterning a film to form a dummy pattern between the first and second wirings; and forming a second insulating film on the first insulating film. Method.
間に前記ダミーパターンを形成するためのマスクとなる
粘度を有することを特徴とする請求項１または請求項４
記載の半導体装置の製造方法。5. The resist according to claim 1, wherein the resist has a viscosity that serves as a mask for forming the dummy pattern between the first and second wirings.
The manufacturing method of the semiconductor device described in the above.
ズ程度以下であることを特徴とする請求項５記載の半導
体装置の製造方法。6. The method of manufacturing a semiconductor device according to claim 5, wherein the resist has a viscosity of about 50 centipoise or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8133026A JPH09321043A (en) | 1996-05-28 | 1996-05-28 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8133026A JPH09321043A (en) | 1996-05-28 | 1996-05-28 | Method for manufacturing semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09321043A true JPH09321043A (en) | 1997-12-12 |
Family
ID=15095070
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8133026A Pending JPH09321043A (en) | 1996-05-28 | 1996-05-28 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09321043A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010009385A (en) * | 1999-07-09 | 2001-02-05 | 김영환 | Manufacturing method for metal line in semiconductor device |
| JP2001156072A (en) * | 1999-11-29 | 2001-06-08 | Mitsubishi Electric Corp | Semiconductor device, method for designing pattern of semiconductor device, and semiconductor device pattern designing apparatus |
| CN100343977C (en) * | 2001-10-16 | 2007-10-17 | Nxp股份有限公司 | Multilevel poly-si tiling for semiconductor circuit manufacture |
| JP2009044076A (en) * | 2007-08-10 | 2009-02-26 | Toshiba Corp | Pattern forming method and manufacturing method of semiconductor device |
| JP2009218503A (en) * | 2008-03-12 | 2009-09-24 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method thereof |
| JP4578635B2 (en) * | 1999-07-22 | 2010-11-10 | フランス・テレコム | Method for correcting surface shape effects on electronic circuit boards |
| US9224745B2 (en) | 2011-12-28 | 2015-12-29 | Fujitsu Semiconductor Limited | Method of manufacturing semiconductor device |
| CN109148270A (en) * | 2017-06-19 | 2019-01-04 | 东京毅力科创株式会社 | Film build method, storage medium and film-forming system |
| CN113363233A (en) * | 2020-03-06 | 2021-09-07 | 铠侠股份有限公司 | Semiconductor device and method for manufacturing the same |
-
1996
- 1996-05-28 JP JP8133026A patent/JPH09321043A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010009385A (en) * | 1999-07-09 | 2001-02-05 | 김영환 | Manufacturing method for metal line in semiconductor device |
| JP4578635B2 (en) * | 1999-07-22 | 2010-11-10 | フランス・テレコム | Method for correcting surface shape effects on electronic circuit boards |
| JP2001156072A (en) * | 1999-11-29 | 2001-06-08 | Mitsubishi Electric Corp | Semiconductor device, method for designing pattern of semiconductor device, and semiconductor device pattern designing apparatus |
| CN100343977C (en) * | 2001-10-16 | 2007-10-17 | Nxp股份有限公司 | Multilevel poly-si tiling for semiconductor circuit manufacture |
| JP2009044076A (en) * | 2007-08-10 | 2009-02-26 | Toshiba Corp | Pattern forming method and manufacturing method of semiconductor device |
| JP2009218503A (en) * | 2008-03-12 | 2009-09-24 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method thereof |
| US9224745B2 (en) | 2011-12-28 | 2015-12-29 | Fujitsu Semiconductor Limited | Method of manufacturing semiconductor device |
| CN109148270A (en) * | 2017-06-19 | 2019-01-04 | 东京毅力科创株式会社 | Film build method, storage medium and film-forming system |
| CN109148270B (en) * | 2017-06-19 | 2023-11-03 | 东京毅力科创株式会社 | Film forming method, storage medium, and film forming system |
| CN113363233A (en) * | 2020-03-06 | 2021-09-07 | 铠侠股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN113363233B (en) * | 2020-03-06 | 2024-04-09 | 铠侠股份有限公司 | Semiconductor device and method for manufacturing the same |
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