JP2009218503A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

Reliability is improved by suppressing intrusion of cracks from the side wall of a semiconductor chip during dicing.
A planarization insulating film region is formed on an end portion of a surface of a semiconductor chip region so as to surround the integrated circuit region. The planarization insulating film region 30 is obtained by replacing a portion where a conventional dummy metal layer has been formed with a dummy insulating film. Three dummy insulating film patterns 20 are formed at regular intervals on the first interlayer insulating film 12 extending from the integrated circuit region 31. Further, the second interlayer insulating film 14 extending from the integrated circuit region 31 covers the three dummy insulating film patterns 20, and the three dummy insulating film patterns 21 are also formed on the second interlayer insulating film 14 at regular intervals. ing. Further, the third interlayer insulating film 16 extending from the integrated circuit region 31 covers the three dummy insulating film patterns 21, and the three interlayer insulating film 16 is also formed with three dummy insulating film patterns 22 at regular intervals. ing.
[Selection] Figure 4

Description

  The present invention relates to a semiconductor device having multilayer wiring and a method for manufacturing the same.

  Conventionally, in a semiconductor device having multilayer wiring, a dummy metal layer has been provided in a space between wiring layers in an LSI region for the purpose of ensuring flatness of the surface of the semiconductor chip. The dummy metal layer has a laminated structure using a multilayer wiring process, and an interlayer insulating film is formed between two adjacent dummy metal layers.

Further, a similar dummy metal layer is provided at the end of the semiconductor chip outside the LSI region. This is to ensure flatness from the LSI area, which is the effective area of the semiconductor chip, to the dicing area outside it, in order to perform dicing to cut the semiconductor wafer into a plurality of chips with high precision. It is. Non-patent document 1 describes the planarization of the surface of the semiconductor chip.
“Latest Trends of LED Printer Heads” OKI Technical Review 2006 No. 208 Vol. 73 NO. 4 pages 28-31

  However, when the dicing blade is in contact with the dummy metal layer at the end of the semiconductor chip during dicing, the dummy metal layer is peeled off from the interlayer insulating film, or cracks are formed in the interlayer insulating film from the sidewall of the semiconductor chip exposed by dicing. There was a risk of causing problems such as intrusion, deterioration of flatness and deterioration of reliability.

  The semiconductor device of the present invention includes an integrated circuit region including a semiconductor substrate, a plurality of metal layers formed on the semiconductor substrate, and a plurality of interlayer insulating films sandwiched between the metal layers, and the integrated circuit And a planarization insulating film region formed on the end portion of the semiconductor substrate so as to surround the region.

  According to a method of manufacturing a semiconductor device of the present invention, a step of forming a first interlayer insulating film on a semiconductor substrate including an integrated circuit region and a metal layer on the first interlayer insulating film formed in the integrated circuit region are provided. Forming a dummy insulating film pattern having the same thickness as the metal layer on the first interlayer insulating film formed outside the integrated circuit region; the metal layer and the dummy insulating film; Forming a second interlayer insulating film covering the pattern.

  According to the present invention, since the portion of the dummy metal layer is replaced with the insulating film, the flatness of the semiconductor chip can be ensured and the interface between the dummy metal layer and the interlayer insulating film does not exist. The problem of peeling is also solved. In addition, since the insulating film is integrated with the interlayer insulating film to become a planarized insulating film, cracks from the side wall of the semiconductor chip are prevented from entering during dicing, and the reliability of the semiconductor device can be improved. .

[First Embodiment]
The semiconductor device according to the first embodiment of the present invention will be described below with reference to the drawings. As shown in FIG. 1, a plurality of semiconductor chip regions 10 are partitioned on the surface of a semiconductor wafer 100 by dicing regions DL extending in a line shape vertically and horizontally. The plurality of semiconductor chip regions 10 are regions divided into a plurality of semiconductor chips by dicing the semiconductor wafer 100 along the dicing region DL.

  As shown in FIG. 2 (partially enlarged view of FIG. 1), an integrated circuit region 31 (an integrated circuit made of semiconductor elements, wirings, etc.) is formed in the semiconductor chip region 10. Then, a planarization insulating film region 30 is formed on the edge of the surface of the semiconductor chip region 10 so as to surround the integrated circuit region 31. The planarization insulating film region 30 extends to the dicing region DL. Further, the two planarization insulating film regions 30 sandwiching the dicing region DL are formed symmetrically with respect to the center line of the dicing region DL.

  Hereinafter, the structures of the planarization insulating film region 30 and the integrated circuit region 31 will be described with reference to FIGS. 3 is an enlarged view of a region R surrounded by a broken line in FIG. 2, and FIG. 4 is a cross-sectional view taken along line XX in FIG. Since the planarization insulating film region 30 is formed using the multilayer wiring structure in the integrated circuit region 31, the integrated circuit region 31 will be described first.

  A first interlayer insulating film 12 is formed to cover the surface of the semiconductor substrate 11, and a first metal layer 13 is formed on the first interlayer insulating film 12. A second interlayer insulating film 14 is formed so as to cover the first metal layer 13, and a second metal layer 15 is formed on the second interlayer insulating film 14. Further, a third interlayer insulating film 16 is formed so as to cover the second metal layer 15, and a third metal layer 17 is formed on the third interlayer insulating film 16. A passivation film 18 for passivation is formed on the uppermost third metal layer 17. In order to flatten the surface of the protective film 18, a fourth interlayer insulating film (not shown) is formed on the uppermost third metal layer 17, and the protective film 18 is formed on the fourth interlayer insulating film. May be.

  Here, the first interlayer insulating film 12 is a BPSG film, the second interlayer insulating film 14, the third interlayer insulating film 16, and the fourth interlayer insulating film are formed of a plasma TEOS film / SOG film / plasma TEOS film for planarization. A three-layer film structure is preferable, and the protective film 18 is preferably a silicon nitride film or a stacked film of a silicon nitride film and a silicon oxide film for passivation.

  The first metal layer 13 is connected to a semiconductor element 19 formed on the surface of the semiconductor substrate 11 through a via hole C1 (which may be called a contact hole) formed in the first interlayer insulating film 12. . The semiconductor element 19 includes a MOS transistor, a bipolar transistor, a diffusion resistance element, and the like.

  A metal member is buried in the via hole C1. When the first metal layer 13 and the second metal layer 15 are connected, they are connected through the via hole SC1 formed in the second interlayer insulating film 14. A metal member is buried in the via hole SC1. Similarly, when the second metal layer 15 and the third metal layer 17 are connected, they are connected through the via hole TC1 formed in the third interlayer insulating film 16. A metal member is buried in the via hole TC1. The integrated circuit region 31 is not shown in the plan view of FIG.

  Next, the structure of the planarization insulating film region 30 will be described. The planarization insulating film region 30 is an insulating film region formed on the semiconductor substrate 11 outside the integrated circuit region 31, and is the uppermost layer with respect to the height of the integrated circuit region 31 (based on the surface of the semiconductor substrate 11). The height h1 up to the third metal layer 17 or the height h2 up to the surface of the protective film 18) is substantially the same. Thereby, the flatness of the area | region from the integrated circuit area | region 31 to the dicing area | region DL can be ensured, and the precision of dicing can be improved.

  The planarization insulating film region 30 is obtained by replacing a portion where a conventional dummy metal layer has been formed with a dummy insulating film. That is, as shown in FIG. 4, on the first interlayer insulating film 12 extending from the integrated circuit region 31, three dummy insulating film patterns 20 made of an insulating film are formed at regular intervals.

  Further, the second interlayer insulating film 14 extending from the integrated circuit region 31 covers the three dummy insulating film patterns 20, and the three dummy insulating film patterns 21 are also formed on the second interlayer insulating film 14 at regular intervals. Has been. The three dummy insulating film patterns 21 and the three lower dummy insulating film patterns 20 overlap each other. Further, the third interlayer insulating film 16 extending from the integrated circuit region 31 covers the three dummy insulating film patterns 21, and the three dummy insulating film patterns 22 are also formed on the third interlayer insulating film 16 at regular intervals. Has been. The three dummy insulating film patterns 22 and the lower three dummy insulating film patterns 21 overlap each other. Three dummy insulating film patterns 20, 21, and 22 are formed, but can be appropriately increased or decreased according to the required width of the planarizing insulating film region 30.

  In order to form the three dummy insulating film patterns 20, an insulating film is deposited on the first interlayer insulating film 12 by a plasma CVD method or the like, and then a resist pattern is formed on the deposited insulating film. An insulating film may be formed using as a mask. The same applies to the dummy insulating film patterns 21 and 22.

  The protective film 18 in the integrated circuit region 31 extends to cover the uppermost three dummy insulating film patterns 22. When the fourth interlayer insulating film is formed, the fourth interlayer insulating film extending from the integrated circuit region 31 covers the uppermost three dummy insulating film patterns 22, and the protective film 18 is disposed thereon. become. The dummy insulating film patterns 20, 21, and 22 are each preferably an insulating film having the same quality as the first to third interlayer insulating films 12, 14, and 16, such as a plasma TEOS film, in order to improve adhesion.

  In the plan view of FIG. 3, the dummy insulating film pattern stacks 23 including the dummy insulating film patterns 20, 21, and 22 overlapping in the vertical direction are arranged in three rows in the vertical direction along the integrated circuit region 31. Yes. Further, the dummy insulating film pattern laminate 23 on the left side in FIG. 3 straddles the end of the dicing region DL.

  As described above, by providing the planarization insulating film region 30, the flatness of the semiconductor chip region 10 can be ensured from the integrated circuit region 31 to the dicing region DL, and the interface between the dummy metal layer and the interlayer insulating film can be secured. Therefore, the problem of peeling off of the dummy metal layer is also eliminated. In addition, since the dummy insulating film pattern is an insulating film with the interlayer insulating film, it has good adhesion and is integrated into a flattened insulating film, so that cracks from the side wall of the semiconductor chip may intrude during dicing. The reliability of the semiconductor device can be improved.

  If the adhesion between the protective film 18 and the dummy insulating film pattern 22 is weak, the protective film 18 may be peeled off due to mechanical impact during dicing. Therefore, when such a concern is concerned, it is preferable to remove the protective film 18 on the dicing region DL so that the dicing blade 50 does not contact the protective film 18 as shown in FIG. . In the structure of FIG. 5, the protective film 18 is removed partway through the planarization insulating film region 30 in consideration of the positional deviation of the dicing blade.

  Then, by dicing the semiconductor wafer 100 configured as described above along the dicing region DL with the dicing blade 50, the semiconductor wafer 100 is divided into a plurality of semiconductor chips. That is, the plurality of semiconductor chip regions 10 are separated from each other to form a plurality of semiconductor chips. FIG. 6 shows one semiconductor chip after dicing. In this case, since the dummy insulating film pattern laminate 23 is formed across the end of the dicing region DL, the dummy insulating film pattern laminate 23 is cut by the dicing blade 50.

  The dummy insulating film pattern can also be used for the integrated circuit region 31. That is, by replacing the dummy metal layer used for planarization of the integrated circuit region 31 with a dummy insulating film pattern, in addition to ensuring planarization, the parasitic capacitance between the metal layers can be reduced as compared with the case where the dummy metal layer is used. The effect to reduce can be acquired.

  FIG. 7 is a cross-sectional view of the integrated circuit region 31 showing such a dummy insulating film pattern structure. As illustrated, a dummy insulating film pattern 26 is formed between the second metal layer 24 and the metal layer 25 on the second interlayer insulating film 14. Further, a dummy insulating film pattern 29 is formed between the metal layer 27 and the metal layer 28 on the third interlayer insulating film 16. By doing so, the space between the metal layers is filled with an insulator, and the parasitic capacitance between the metal layers adjacent to each other in the vertical and horizontal directions is reduced. For example, the parasitic capacitance Cs1 between the left and right adjacent metal layers 27 and 28 and the parasitic capacitance Cs2 between the metal layer 27 and the lower metal layer 33 are reduced.

[Second Embodiment]
The semiconductor device according to the second embodiment of the present invention will be described below with reference to the drawings. In the first embodiment, the dummy insulating film pattern is formed by a process separate from the interlayer insulating film, but in this embodiment, a process for forming an interlayer insulating film having a three-layer structure of TEOS film / SOG film / TEOS film is used. Thus, the process of forming the planarization insulating film region 30A including the dummy insulating film is streamlined.

Hereinafter, a method of forming the planarization insulating film region 30A will be described with reference to FIGS.
First, as shown in FIG. 8A, a first TEOS film 40 is formed by plasma CVD on the first interlayer insulating film 12 on which the first metal layer 13 in the integrated circuit region 31 is formed. To do. The first TEOS film 40 is formed thicker than a normal TEOS film.

  Next, as shown in FIG. 8B, a resist pattern 41 is formed on the first TEOS film 40 in the planarization insulating film region 30A. Here, for comparison, the dummy insulating film pattern 20 of the first embodiment is indicated by a broken line. The dummy insulating film pattern 20 is formed at substantially the same height as the first metal layer 13, but the first TEOS film 40 is formed thicker than the dummy insulating film pattern 20.

  Next, as shown in FIG. 8C, the first TEOS film 40 is etched using the resist pattern 41 as a mask. The resist pattern 41 is removed after the etching. Alternatively, so-called etch back, in which the resist pattern 41 and the first TEOS film 40 are simultaneously etched, may be performed. As a result, an uneven dummy insulating film pattern 20A is formed in the planarizing insulating film region 30A. On the first metal layer 13, the first TEOS film 40 thinned by etching is left. The film thickness is the same as that obtained by an ordinary interlayer insulating film forming process having a three-layer structure.

Next, as shown in FIG. 8D, SOG is spin coated on the semiconductor substrate 11 (semiconductor wafer 100) on which the dummy insulating film pattern 20A is formed. Then
The SOG film 42 is embedded in the concave portion of the dummy insulating film pattern 20A, and the surface of the dummy insulating film pattern 20A becomes flat. Further, a second TEOS film 43 is formed on the SOG film 42 by plasma CVD. Thus, the second interlayer insulating film 14A is formed by the dummy insulating film pattern 20A (first TEOS film), the SOG film 42, and the second TEOS film 43.

  That is, the second interlayer insulating film 14A including the dummy insulating film pattern 20A can be formed by utilizing the interlayer insulating film process. As shown in FIG. 9, the third interlayer insulating film 16A and the fourth interlayer insulating film 44 can also be formed by the same method as described above.

  Then, by dicing the semiconductor wafer 100 configured as described above along the dicing region DL with the dicing blade 50, the semiconductor wafer 100 is divided into a plurality of semiconductor chips. That is, the plurality of semiconductor chip regions 10 are separated from each other to form a plurality of semiconductor chips. FIG. 10 shows one semiconductor chip after dicing.

  Further, since the dummy insulating film pattern 20A is formed using the resist pattern 41, the arbitrary dummy insulating film pattern 20A can be formed by changing the resist pattern 41. For example, as shown in FIG. 11, a flat, dummy dummy insulating film pattern 20B may be formed over substantially the entire planarizing insulating film region 30B. The dummy insulating film pattern 20B has a recess in a region adjacent to the integrated circuit region 31, and the SOG film 42 is buried in the recess and planarized. Other regions form flat convex portions. Such a solid dummy insulating film pattern 20B is formed as a part of the second to fourth interlayer insulating films 14A, 16A, and 44.

  Needless to say, the present invention is not limited to the above-described embodiment, and can be changed without departing from the gist thereof. For example, in the first and second embodiments, a semiconductor device having a three-layer wiring structure has been described as an example. However, the present invention can be applied to a semiconductor device having a general multilayer wiring structure.

It is a top view which shows a semiconductor wafer. It is the elements on larger scale of FIG. It is a top view which shows the semiconductor device (before dicing) by the 1st Embodiment of this invention. It is sectional drawing in the XX line of FIG. It is sectional drawing which shows the semiconductor device (after dicing) by the 1st Embodiment of this invention. It is sectional drawing which shows the semiconductor device (before dicing) by the 1st Embodiment of this invention. It is sectional drawing which shows an integrated circuit area | region. It is sectional drawing which shows the manufacturing method of the semiconductor device by the 2nd Embodiment of this invention. It is sectional drawing which shows the semiconductor device (before dicing) by the 2nd Embodiment of this invention. It is sectional drawing which shows the semiconductor device (after dicing) by the 2nd Embodiment of this invention. It is sectional drawing which shows the semiconductor device (before dicing) by the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor chip area | region 11 Semiconductor substrate 12 1st interlayer insulation film 13 1st metal layer 14 2nd interlayer insulation film 15 2nd metal layer 16 3rd interlayer insulation film 17 3rd metal layer 18 Protective film 19 Semiconductor element 20, 21, 22 dummy insulating film patterns 20A, 20B dummy insulating film patterns 23 dummy insulating film pattern stacks 24, 25 metal layers 26 dummy insulating film patterns 27, 28 metal layers 29 dummy insulating film patterns 30, 30A, 30B planarizing insulating film regions 40 First TEOS film 41 Resist pattern 42 SOG film 43 Second TEOS film 44 Fourth interlayer insulating film 50 Dicing blade 100 Semiconductor wafer

Claims (10)

A semiconductor substrate;
An integrated circuit region formed on the semiconductor substrate and comprising a plurality of metal layers and a plurality of interlayer insulating films sandwiched between the metal layers;
And a planarization insulating film region formed on an end portion of the semiconductor substrate so as to surround the integrated circuit region. The semiconductor device according to claim 1, wherein the planarization insulating film region is formed at substantially the same height as the integrated circuit region. 2. The planarization insulating film region includes the plurality of interlayer insulating films extending from the integrated circuit region and a dummy insulating film pattern formed on each interlayer insulating film. Item 3. The semiconductor device according to Item 2. The semiconductor device according to claim 1, wherein the planarization insulating film region extends to a dicing region on the semiconductor substrate. 5. The semiconductor device according to claim 4, further comprising a protective film covering the integrated circuit region, wherein the protective film is removed at least on the planarizing insulating film region of the scribe region. 4. The semiconductor according to claim 1, wherein a dummy insulating film pattern is disposed between two metal layers adjacent to each other in a vertical direction of the semiconductor substrate in the integrated circuit region. apparatus. Forming a first interlayer insulating film on a semiconductor substrate including an integrated circuit region;
Forming a metal layer on the first interlayer insulating film formed in the integrated circuit region;
Forming a dummy insulating film pattern having the same thickness as the metal layer on the first interlayer insulating film formed outside the integrated circuit region;
Forming a second interlayer insulating film covering the metal layer and the dummy insulating film pattern. Forming an interlayer insulating film on the semiconductor substrate including the integrated circuit region;
Forming a metal layer on the interlayer insulating film formed in the integrated circuit region;
Forming a first TEOS film covering the metal layer and the interlayer insulating film by a plasma CVD method;
Forming a resist pattern on the first TEOS film formed outside the integrated circuit region, and etching the first TEOS film to form a dummy insulating film pattern corresponding to the resist pattern; When,
Forming an SOG film covering the dummy insulating film pattern;
Forming a second TEOS film covering the SOG film by a plasma CVD method. 9. The semiconductor according to claim 8, wherein the dummy insulating film pattern has a concave portion and a convex portion corresponding to the resist pattern, and the SOG film is formed so as to fill the concave portion of the dummy insulating film pattern. Device manufacturing method. A semiconductor substrate;
An integrated circuit region comprising a plurality of metal layers formed on the semiconductor substrate and a plurality of interlayer insulating films sandwiched between metal layers adjacent to each other in the vertical direction of the semiconductor substrate;
A planarizing insulating film region surrounding the integrated circuit region and formed on an end portion of the semiconductor substrate, and the planarizing insulating film region includes a dummy insulating film pattern having a concave portion and a convex portion. A featured semiconductor device.

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