JPH0729918A - High frequency field effect transistor - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to provide a high-frequency field-effect transistor which can be used at higher frequencies by reducing the phase difference. [Structure] The unit gate 3 is formed in a comb shape, and the drain 5 and the source 4 of each unit transistor are formed so as to interlock between them. The width of the unit gate located in the central portion is 250 μm, the width of the unit gate located in the peripheral portion is 150 μm, and the gate width gradually decreases from the central portion to the peripheral portion. The drain 5 of each unit transistor is connected to each other by an air bridge 6, and the source 4 is connected to each other by a lead wire of an electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency field effect transistor used in a microwave band.

[0002]

2. Description of the Related Art Conventionally, a high frequency field effect transistor used in a microwave band (hereinafter referred to as a high frequency FET).
Makes it possible to use in the microwave band by increasing the gate width and passing a large current to increase the output. A high-frequency FET is a FE having a large gate width obtained by arranging a plurality of FETs having a small gate width and summing the gate widths.
It is T. The high-frequency FET having this structure is called a multi-finger type transistor, each transistor is called a unit transistor, and each gate is called a unit gate.

FIG. 2 shows an example thereof. High frequency FE
It is a perspective view which shows the structure of T. In the figure, the unit gates 3 having a gate width of 200 μm are arranged in a comb shape at intervals of 60 μm. The gate bonding pad 1 and the drain bonding pad 2 are arranged so as to sandwich substantially the central portion of the gate array. The source 4 and the drain 5 of each unit transistor are formed so as to interlock between the unit gates 3 arranged in a comb shape. Each drain 5 is connected to each other by an air bridge 6, and each source 4 is connected to each other by a lead wire of an electrode. In the high-power FET configured in this manner, the input signal is dispersed in the chip, reaches each FET, and is reassembled to be propagated as an output signal.

[0004]

In order to obtain the maximum efficiency power gain, it is preferable that all the unit transistors operate in the same phase. However, a signal path (shortest path) passing through the unit transistor located in the center as shown by the dotted line in FIG. A difference occurs in the signal path length from the (longest path). Therefore, there is a problem that a phase difference occurs and the gain is reduced. The decrease in gain begins to occur when the signal path length difference is about 1/16 of the wavelength of the used frequency, and at 1/8 or more of the wavelength,
It becomes impossible to use in the high frequency band. The FET shown in FIG. 2 has a signal path length difference of about 420 μm, and a decrease in gain starts to occur from a use frequency of about 15 GHz.

Therefore, the present invention has been made in order to solve the above problems, and an object thereof is to realize a high frequency field effect transistor in which a phase difference is reduced and an efficient gain is obtained.

[0006]

In the high frequency field effect transistor of the present invention, the gates of the plurality of unit transistors, the sources thereof, and the drains thereof are commonly connected to each other, and the gates of the respective unit transistors are comb-shaped. The gate common pad and the drain common pad are arranged so as to sandwich almost the central part of the gate array of the unit transistor, and the gate width of the unit transistor located in the central part of the gate array is located in the peripheral part. It is characterized in that it is larger than the gate width of the unit transistor.

The gate width of the unit transistor can be gradually reduced from the central portion of the gate array toward the peripheral portion.

[0008]

In the high-frequency field-effect transistor of the present invention, the gate width of the central unit transistor is larger than the gate width of the peripheral unit transistors. The path length difference from the signal path passing through the located FET can be reduced. Therefore, since the phase difference can be reduced, it is possible to obtain an efficient output gain and use at higher frequencies.

[0009]

Embodiments of the present invention will be described below with reference to the accompanying drawings. In the description of the drawings, the same elements will be denoted by the same reference symbols, without redundant description.

An embodiment of the present invention will be described with reference to FIG.
FIG. 1 is a perspective view showing the structure of a high frequency field effect transistor formed on a GaAs substrate. Unit gate 3 is 6
It is formed in a comb shape at an interval of 0 μm, and the drain 5 and the source 4 of each unit transistor are formed so as to interlock between them. Unit gate 3 located in the center
Has a width of 250 μm, the unit gate 3 located in the peripheral portion has a width of 150 μm, and the gate width gradually decreases from the center to the peripheral portion. The drains 5 of the unit transistors are connected to each other by an air bridge 6, and the sources 4 are connected to each other by lead lines of electrodes.

In FIG. 1, a signal path (shortest path) passing through the central FET is indicated by a dotted line, and a signal path (longest path) passing through a peripheral FET is indicated by a dashed line. The signal path length difference between the shortest path and the longest path is about 320 μm, which is smaller than the signal path length difference of the conventional high output FET shown in FIG. Therefore, since the phase difference can be reduced,
An efficient gain can be obtained. The FET of the embodiment can increase the frequency at which the gain reduction starts to occur up to 20 GHz.

The present invention is not limited to the above embodiment, but various modifications can be made.

For example, although the gate width of each unit gate 3 is gradually reduced from the center to the peripheral portion in the embodiment, it is not necessary to reduce the gate width at a constant rate, and the width of the unit gate located at the center is not necessary. Is larger than that located in the peripheral portion, the signal path length difference can be mitigated.
The phase difference can be reduced.

Although the drains 5 are connected to each other by the air bridge 6, they may be connected to each source 4 through a bus via an insulating film.

[0015]

As described in detail above, according to the present invention, the phase difference can be made small, so that an efficient gain can be obtained, and it can be used at a higher frequency.

[Brief description of drawings]

FIG. 1 is a perspective view showing the configuration of a high-power FET according to an embodiment.

FIG. 2 is a perspective view showing a configuration of a conventional high output FET.

[Explanation of symbols]

1 ... Gate bonding pad, 2 ... Drain bonding pad, 3 ... Unit gate, 4 ... Source, 5
… Drain, 6… Air bridge

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Jiro Fukui 1 Taya-cho, Sakae-ku, Yokohama-shi, Kanagawa Sumitomo Electric Industries, Ltd. Yokohama Works (72) Ryoji Sakamoto 1 Taya-cho, Sakae-ku, Yokohama, Kanagawa Sumitomo Electric Ki Industry Co., Ltd. Yokohama Works

Claims (2)

[Claims] 1. The gates of a plurality of unit transistors,
In a high-frequency field effect transistor in which sources are connected to each other and drains are connected to each other, the gates of the unit transistors are arranged in a comb shape, and the gate bonding pads and the drain bonding pads are connected to the unit transistors. It is arranged so as to sandwich a substantially central portion of the gate array, and the gate width of the unit transistor located in the central portion of the gate array is larger than the gate width of the unit transistor located in the peripheral portion. High frequency field effect transistor. 2. The high frequency field effect transistor according to claim 1, wherein a gate width of the unit transistor is gradually reduced from a central portion of the gate array toward a peripheral portion thereof.