JPH0737901A - High output field-effect transistor - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to provide a high output field effect transistor capable of suppressing the amount of heat and reducing the phase difference of signals to obtain an efficient gain. [Structure] Gate wiring 7 from gate bonding pad 1 to drain bonding pad 2 direction
, The unit gate 3 is formed in a comb shape in the direction perpendicular to the gate wiring 7, and the source 4 and the drain 5 are formed so as to interlock between them. The unit gates 3 arranged in a comb shape are formed on both sides of the gate wiring 7.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a high power field effect transistor used in a microwave integrated circuit.

[0002]

2. Description of the Related Art Conventionally, a high output field effect transistor (hereinafter referred to as a high output FET) has a large gate width,
A large drain current is used to increase the output. High output FE
T is a series of FETs having a small gate width,
An FET having a large gate width is obtained by summing up the gate widths. The high-power FET having this structure is called a multi-finger type transistor, each transistor is called a unit transistor, and each gate is called a unit gate.

FIG. 7 shows an example thereof. High output FE
It is a perspective view which shows the structure of T. The unit gates 3 having the same gate width are arranged in a comb shape at regular intervals.
The source 4 and the drain 5 of each unit transistor are formed so as to interlock between the unit gates 3 arranged in a comb shape. The gate bonding pad 1 and the drain bonding pad 2 are arranged so as to sandwich substantially the central portion of the gate array. Each drain 5 is connected to each other by an air bridge wiring 6, and each source 4 is connected to each other by a lead wire of an electrode.

To further increase the output, the unit gate width is increased, the number of unit gates is increased, and the overall gate width is increased.

[0005]

The amount of heat generated in the channel portion of the unit transistor increases in proportion to the increase in the gate width. When the amount of heat generation increases, the temperature rises, which may exceed the operating range of the high power FET.

Therefore, as a method of suppressing the temperature rise, the unit gate width is reduced to reduce the heat source to suppress the generation of heat, and the arranging intervals are increased to disperse the heat. When this method is applied to the high-power FET shown in FIG. 2, it is necessary to increase the number of unit gates as much as the unit gate width is reduced, and the width becomes longer in the lateral direction (X direction in the figure). Therefore, a signal path (shortest path) passing through the unit transistor located in the center as shown by the dotted line in FIG. 2 and a signal path passing through the unit transistor located at the periphery as shown by the dashed line A difference occurs in the signal path length from the (longest path). for that reason,
There is a problem that a phase difference of signals occurs and output power gain decreases. The signal path length difference is 1 of the wavelength of the used frequency.
A decrease in gain begins to occur at about / 16 and 1/8 of the wavelength
With the above, use in a high frequency band becomes impossible. And
Since it becomes long in the lateral direction (X direction in FIG. 7), the layout of this high-power FET cannot be efficiently laid out,
This led to an increase in chip area.

Therefore, the present invention has been made in order to solve the above problems, and it is possible to suppress the amount of heat and reduce the phase difference between signals to obtain an efficient gain high output electric field effect. The purpose is to provide a transistor.

[0008]

A high-power field-effect transistor of the present invention is formed on a semiconductor substrate by commonly connecting gates, sources and drains of a plurality of unit transistors to each other. The gate wiring is arranged in the direction from the pad to the drain bonding pad, and the gates of the unit transistors are arranged in a comb shape in a direction substantially perpendicular to the gate wiring and connected to the gate wiring. And

Here, the gate array of the unit transistors may be formed on only one side or both sides of the gate wiring.

[0010]

In the high output field effect transistor of the present invention, the gate wiring is arranged from the gate bonding pad to the drain bonding pad direction, and the gates of the plurality of unit transistors are substantially perpendicular to the gate wiring. Since they are formed in a comb shape, the maximum difference in the path length of the signal passing through each FET is only twice the unit gate width.

That is, the signal path length difference is determined only by the unit gate width, and does not depend on the interval at which the unit gates are arranged and the number of unit gates. Therefore, the phase difference between the signals is high output FE
Since it does not become so large as to deteriorate the operating characteristics of T, no decrease in output power gain is observed. Therefore, the unit gate interval can be widened in order to suppress the heat quantity, and since the phase difference does not change even if the number of unit gates is increased, there is no limitation on the total gate width and a desired maximum output can be obtained.

[0012]

Embodiments of the present invention will be described below with reference to the accompanying drawings. In the description of the drawings, the same elements will be denoted by the same reference symbols, without redundant description.

FIG. 1 is a perspective view showing the structure of the high-power FET of the first embodiment. Gate bonding pad 1
To the drain bonding pad 2 direction, the gate wiring 7 is arranged, and the unit gate 3 is formed in a comb shape in a direction perpendicular to the gate wiring 7, and the source 4 and the drain 4 are combined so as to be intervened therebetween. 5 is formed. The drains 5 are connected to each other by air bridge wiring 6.

The signal input from the gate bonding pad 1 is distributed to each unit transistor via the gate wiring 7, amplified, and then reassembled to be propagated to the drain bonding pad 2 as an output signal. In FIG. 1, a dotted line (shortest path) indicates a signal path passing through the unit transistor located closest to the gate bonding pad 1, and a signal path (longest path) passing through the unit transistor located furthest away is shown. It is indicated by a dashed line. In the shortest path and the longest path, the vertical direction of the chip (Y direction in FIG. 1)
Since the distance of the signal path does not change, the maximum difference in signal path length is only twice the width of the unit gate 3. That is,
The generation of the phase difference between the signals amplified in each unit gate 3 is determined only by the unit gate width, and does not depend on the interval between the unit gates 3 and the number of unit gates. If the signal path difference is set to 1/16 or less of the wavelength, no remarkable decrease in gain is observed, so that the unit gate width can be increased to 1/32 of the wavelength. Therefore, in order to suppress the amount of heat generated in each unit transistor, even if the unit gate width is reduced to increase the number of unit gates or the unit gate interval is increased, the signal path difference does not increase. No gain reduction will occur.

As described above, the high output FET in which the unit gates are arranged in the direction perpendicular to the gate wiring arranged from the gate bonding pad has a small unit gate width even if the unit gate interval is widened. However, since the signal path difference does not widen even if the number of unit gates is increased, it is possible to suppress the generation of heat and reduce the temperature rise.
Further, in order to further increase the output, it can be dealt with by increasing the number of unit gates and increasing the total gate width, so that the signal path difference does not increase, and theoretically, there is no limitation on the maximum output. Therefore, the amount of heat can be suppressed and an efficient gain can be obtained.

Next, a second embodiment will be described with reference to FIG. FIG. 2 is a perspective view showing the structure of the high power FET of the second embodiment. This embodiment is different from the first embodiment in that
The unit gates 3 are formed in a comb-teeth shape on both sides of the gate wiring 7 in that the unit gates 3 are formed in a comb-teeth shape in the vertical direction with respect to the gate wiring 7 arranged from the gate bonding pad 1. That is what is being done.

In the high output FET structure of the first embodiment, when the unit gate interval is widened in order to suppress the amount of heat, or when the number of unit gates is increased in order to achieve higher output, the high output FET becomes It becomes long in the vertical direction (Y direction in FIG. 1). If the unit gates 3 are formed on both sides of the gate wiring 7 as in the high power FET of the second embodiment, the length in the vertical direction is half that of the high power FET of the first embodiment, so the layout is Can be efficiently performed, and the chip area can be effectively used.

The unit gates 3 are provided on both sides of the gate wiring 7.
Even in the case of forming, the difference in signal path length is only twice the maximum unit gate width. Therefore, even if the unit gate interval is widened or the unit gate width is reduced to increase the number of unit gates, the signal path difference does not widen, so that the heat generation can be suppressed and the temperature rise can be reduced. it can. Further, in order to further increase the output, it is possible to deal with it by increasing the number of unit gates and increasing the total gate width.

Therefore, the high output FET of this embodiment can also suppress the amount of heat and obtain an efficient gain. Further, since the configuration of the high output FET can be efficiently laid out, the chip area can be effectively used and the chip cost can be reduced.

The present invention is not limited to the above embodiment, but various modifications can be made.

For example, although the unit gate 3 is formed at a right angle to the gate wiring 7 in the embodiment, the angle formed may be any angle. Further, the formation position of the unit gate 3,
The unit gate width and the unit gate interval can be changed for each unit gate. 3 to 6 show a modification of the second embodiment. 3 to 5 are pattern diagrams showing the structure of the high-power FET. Since the configuration is shown in the pattern diagram, the configuration can be shown even in the portion where the wirings and the like overlap.

First, in the high power FET of FIG. 3, the unit gates 3 are alternately formed on both sides of the gate wiring 7, and the drain 5 and the source 4 are formed between them. When the unit gates 3 are alternately formed on both sides of the gate wiring 7, the heat flows extending from the unit gates 3 on both sides in the gate width direction can spread and radiate heat without colliding with each other.

Next, in the high output FET shown in FIG. 4, in the gate arrangement of the unit transistors 3 formed on both sides of the gate wiring 7, the unit gate width gradually increases from the central portion of the gate arrangement to the peripheral portion. . Here, it is not necessary to increase the gate width at a constant rate, and the width of the unit gate 3 located in the central portion may be smaller than the width of the unit gate 3 located in the peripheral portion. In this high-power FET, the heat generated in each channel overlaps in the central portion of the array of the unit gates 3 and has a higher temperature than the peripheral portion. Is suppressed. This structure can also be applied to the first embodiment.

Further, in order to suppress the concentration of heat quantity, the structure of the high power FET may be as shown in FIG. In the high output FET shown in the figure, in the gate array of the unit transistors 3 formed on both sides of the gate wiring 7, the unit gate interval is narrowed from the central part to the peripheral part of the gate array.
Here, it is not necessary to gradually reduce the unit gate interval,
It suffices that the interval between the unit gates 3 located in the central part is wider than the interval between the unit gates located in the peripheral part. This high output F
Since the ET has a higher temperature than the peripheral portion because heat is superposed in the central portion of the array of the unit gates 3, the unit gate interval in the central portion is set wide to suppress heat concentration. This structure can also be applied to the first embodiment.

Further, in order to suppress the concentration of heat quantity, the interval between the unit gates 3 sandwiching the gate wiring 7 is set to this high output FE.
The thickness may be twice or more the thickness of the semiconductor substrate on which T is formed. Since heat flows within an angle of up to 45 degrees from the heat generating portion, when the distance between the unit gates 3 sandwiching the gate wiring 7 is twice the thickness of the semiconductor substrate or more, heat flows generated on both sides of the gate wiring 7 The temperature rise can be suppressed without hitting each other.

In order to make the interval between the unit gates 3 sandwiching the gate wiring 7 at least twice as large as that of the semiconductor substrate, the gate wiring 7
Can have a width twice or more the thickness of the substrate. At this time, since the width of the gate wiring 7 becomes large, it becomes easy to provide a heat dissipation means on the surface of the gate wiring 7. As shown in FIG. 6, unevenness can be provided on the surface of the gate wiring 7 to facilitate heat dissipation. This structure can also be applied to the first embodiment.

[0027]

As described above in detail, according to the high output field effect transistor of the present invention, the unit gates are arranged in the direction perpendicular to the gate wiring provided from the gate bonding pad. Moreover, since the phase difference between the signals can be reduced, the operating characteristics do not deteriorate. Therefore, there is no limitation on the size of the total gate width due to the phase difference of the signals, so that the unit gate interval can be increased to suppress the heat generation amount, and further higher output can be achieved. Therefore, the temperature rise of the high output FET due to heat generation can be suppressed, and an efficient output power gain can be obtained.

[Brief description of drawings]

FIG. 1 is a perspective view showing a configuration of a high output FET according to a first embodiment.

FIG. 2 is a perspective view showing the configuration of a high-power FET according to a second embodiment.

FIG. 3 is a pattern diagram showing a configuration of a high output FET of a modified example of the second embodiment.

FIG. 4 is a pattern diagram showing a configuration of a high power FET of a modified example of the second embodiment.

FIG. 5 is a pattern diagram showing a configuration of a high output FET of a modified example of the second embodiment.

FIG. 6 is a perspective view showing a gate wiring of a modified example.

FIG. 7 is a perspective view showing a configuration of a conventional high-power FET.

[Explanation of symbols]

1 ... Gate bonding pad, 2 ... Drain bonding pad, 3 ... Unit gate, 4 ... Source, 5
... Drain, 6 ... Air bridge wiring, 7 ... Gate wiring.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tatsuya Hashicho, 1 Taya-cho, Sakae-ku, Yokohama-shi, Kanagawa Sumitomo Electric Industries, Ltd. Yokohama Works (72) Ryoji Sakamoto 1-tani, Taya-cho, Sakae-ku, Yokohama, Kanagawa Sumitomo Electric Industry Co., Ltd. Yokohama Works

Claims (8)

[Claims] 1. A high output field effect transistor formed by commonly connecting gates, sources, and drains of a plurality of unit transistors on a semiconductor substrate, in a direction from a gate bonding pad to a drain bonding pad. A gate wiring is provided for the unit transistor, and the gates of the unit transistors are arranged in a comb shape in a direction substantially perpendicular to the gate wiring and connected to the gate wiring. Transistor. 2. The high output field effect transistor according to claim 1, wherein the gate array of the unit transistors is formed only on one side of the gate wiring and is connected to the gate wiring. 3. The high output field effect transistor according to claim 1, wherein the gate array is formed on both sides of the gate wiring and is connected to the gate wiring. 4. The gate width of the unit transistor located in the central part of the gate array is smaller than the gate width of the unit transistor located in the peripheral part. High output field effect transistor. 5. The gate spacing of the unit transistors located in the central portion of the gate array is wider than the gate spacing of the unit transistors located in the peripheral portion. Output field effect transistor. 6. The high output field effect transistor according to claim 1, wherein the distance between the unit gate and the gate bonding pad is different in all the unit gates. . 7. The height according to claim 1, wherein a distance between the unit gates sandwiching the gate wiring is at least twice the thickness of the semiconductor substrate. Output field effect transistor. 8. The high output field effect transistor according to claim 1, wherein unevenness is provided on a surface of the gate wiring.