JPH07235940A - Supplied signal compensating method/device and supplied signal processing system - Google Patents

Abstract

PURPOSE:To give no influence to the signals supplied from a common line even when the number of internal modules is increased or decreased in such a device constitution or a system constitution w.here the signals are supplied to plural modules through the common line. CONSTITUTION:A mounted sheet number.deciding part 11 fetches the mounting information J1 to Jn obtained by mounting the interface modules INF to INFn to the connectors k1 to kn. Then the number of mounted sheets of modules are counted and this count value is given to a resistance value control part 10 as the resistance value control information. The resistance value of a variable resistance circuit rc2 of a power supply control circuit PCR is set by a resistance value control signal based on the count value. This control signal is given to the circuit PCR. Thus the PCR sets the circuit rc2 based on the mounted sheet number of modules and applies the optimum voltage to the insertion data/clock lines with no disturbance of data or clocks.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a supply signal compensating method, a supply signal compensating apparatus, and a supply signal processing system, and relates to an output signal of a certain signal generating section through a common transmission line (for example, an electric bus line or an optical fiber) ) Through a plurality of signal receiving means (for example, a signal receiving module)
It can be applied to the case of distributed supply to.

[0002]

2. Description of the Related Art In recent years, many circuits of electronic devices have been integrated so that complicated processing can be performed in a small size, and a plurality of processing modules are provided (for example, 10 or more).

In addition, in order to improve reliability, the electronic device has a built-in test circuit for self-inspection and system test so that the function of the device can be tested at any time. ing.

Therefore, for example, an insert test in a transmission device will be described below. FIG. 2 is a system configuration diagram for explaining the insert test. Further, FIG. 3 is a specific configuration diagram of the transmission device 1 used in the insert test.

First, in the insert test system of FIG. 2, insert tests are performed on the processing modules P1 to Pn and PR1 to PRn inside the transmission device 1 on the transmission side and the transmission device 2 on the reception side. The insert test data INSD is given to these processing modules as a test signal and then given to the receiving side through the transmission line CL to test the electrical functional performance of the receiving side processing module.

Therefore, in the transmission-side transmission device 1, insert data INSD (for example, pseudo-random data) is generated from the insert data generator 3 which is a signal generator and given to the test control circuit 1a of the transmission device 1. . Then,
The test control circuit 1a receives the given insert data IN
SD is driven by the driver DV1 and given to each processing module P1 to Pn through the insert data line. At the same time, the test control circuit 1a generates a clock synchronized with the insert data INSD, and inserts the insert clock INCK.
It gives to each processing module P1-Pn through a line.

The processing modules P1 to Pn are
As shown in FIG. 3, the signals are received by the receivers R1 to Rn, and then the processing modules P1 to Pn respectively perform predetermined processing, and the processed signal and the insert clock I are transmitted to the transmission line CL.
It outputs NCK and transmits it to the transmission device 2 on the receiving side. Then, the processing module PR inside the transmission device 2 on the receiving side
1 to PRn are the processing signal and the insert clock I, respectively.
Demodulation processing is performed from NCK to output insert reception data, which is applied to the test control circuit 2a.

Then, the test control circuit 2a supplies the insert reception data given from the processing modules PR1 to PRn to the insert reception data measuring instrument 4 connected to the outside. The insert reception data measuring device 4 observes the waveform of a signal, and may be, for example, an oscilloscope. Then, the insert reception data measuring instrument 4 transmits the insert data I
The NSD and the insert received data are compared in waveform to test the functional performance of the transmission system from the transmission device 1 to the transmission device 2.

[0009]

As shown in FIGS. 2 and 3, the transmission device 1 has the internal insert data I.
A plurality of processing modules P1 to Pn are connected to the NSD line and the insert clock INCK line, respectively. Therefore, a high drive capacity (drive power) is required for the driver DV1 of the test control circuit 1a.

That is, for example, the insert data INS
If a maximum of 10 processing modules are connected to the D line, the driver DV1 of the test control circuit 1a has a maximum of 10 modules.
Receivers R1 to R of the individual processing modules P1 to P10
As a matter of course, the driving capability capable of transmitting the waveform without distortion is required for 10. By designing the driving capability of the driver DV1 in this way, the waveform of the insert data INSD cannot be distorted unless special processing is performed even if the number of processing modules connected to the insert data INSD line is reduced.

However, if it is desired to increase the number of processing modules connected to the insert data INSD line due to an increase in demand for line use, etc., it cannot be easily added. This is insert data INS
Increasing the number of processing modules connected to the D line increases the burden on the driver DV1 of the test control circuit 1a. As a result, if a processing module having a load exceeding the driving capability of the original driver DV1 is connected to the insert data INSD line, the waveform applied to the receiver of each processing module will be distorted or dull. Such a phenomenon similarly occurs for the insert clock INCK.

Further, an increase or decrease in the number of processing modules connected causes a change in impedance when the driver DV1 is viewed from the load side, and this change causes a reflected wave from the load side processing module to return to the driver DV1. This has caused a problem that the waveforms of the insert clock INCK and the insert data INSD given to each processing module are disturbed. Such a phenomenon does not appear prominently at low speeds. For example, at a speed of about 6 Mbit / s, which is generally used for a dedicated line transmission device, the above-mentioned phenomenon has occurred remarkably.

Due to the disturbance of the waveforms of the insert data INSD and the insert clock INCK (distortion, dullness, etc.), the output waveforms of the receivers R1 to Rn have a pulse width change or a pulse The cycle will change. Due to such a phenomenon, there is a problem that the processing in each of the processing modules P1 to Pn cannot be performed normally.

Therefore, in order to prevent such an abnormal state from occurring, in the transmission device as shown in FIGS. 2 and 3, the insert data INSD line and the insert clock INCK shared by a plurality of processing modules are used.
When processing modules are additionally installed in the above, conventionally, it was necessary to repair the driver DV1 so as to increase the driving capacity of the driver DV1 in accordance with the number of additional installations. Also,
The driver DV1 is specifically a general-purpose LSI (for example,
LS240) etc. are used, so depending on the newly required driving capacity, it may be possible to drive with one unit at first, but it may be necessary to configure with two or more units after repair,
The layout of the PWB (Printed Wiring Board) circuit also had to be significantly modified.

From the above, in a device configuration or a system configuration in which a signal is applied to a plurality of modules from a common line, even if the number of internal modules increases or decreases, the signal applied from the common line is not affected. It was requested to provide such a mechanism.

[0016]

Therefore, the supply signal compensating method of the present invention is realized by the following characteristic configuration in order to achieve the above requirements.

That is, signal receiving means (eg, signal receiving module, coupler, optical / electrical conversion module, etc.)
And a signal output means (for example, a test signal output module) for outputting a signal (for example, an electrical signal, an optical signal, etc.) to be used in a signal transmission path (for example, an electric bus line, an optical fiber cable, etc.) , A signal transmission path for distributing the signal from the signal output means to at least two or more signal receiving means that can be inserted and removed by a connection connector.

Further, at least two detachable signal receiving means for receiving the signal from the signal transmission line through the connector are provided.
The above is prepared. Then, each signal receiving means outputs a connection state signal (for example, an ON signal, an OFF signal, an analog signal, or several bit data) indicating that the signal receiving means is connected when connected to the connector. Furthermore, signal distribution adjustment to the signal transmission path is performed according to the number of connections from the connection status signal to the connector of the signal receiving means. The signal supplied to each signal receiving means is compensated according to the insertion / extraction of each signal receiving means to / from the connection connector.

Here, the signal distribution adjustment is (1) adjusting the voltage applied to the signal transmission line according to the number of connections to the connection connector of the signal receiving means, and (2) the signal of the signal transmission line. Any one of the signal distribution adjustments such as adjusting the current, (3) adjusting the impedance matching state between the signal transmission line and each signal receiving means, (4) or adjusting the signal amplification of the signal transmission line. Is preferably performed.

Further, the supply signal compensating apparatus for realizing the above-mentioned invention can be realized by the following characteristic configuration.

That is, the supply signal compensator of the present invention is
Signals (eg, electrical signals, optical signals, etc.) for use in signal receiving means (eg, signal receiving modules, couplers, optical / electrical conversion modules, etc.) are transmitted through signal transmission paths (eg, electrical bus lines, optical signals). Fiber cable, etc.)
And a signal transmission path for distributing a signal from the signal output means to at least two or more signal receiving means that can be inserted and removed by a connection connector.

Further, at least two insertable / removable signal receiving means for receiving the signal from the signal transmission line through the connecting connector are provided, and each signal receiving means is connected when connected to the connecting connector. A connection state signal output means capable of outputting the connection state signal is provided.

Furthermore, a signal distribution adjusting means for receiving the connection status signal and adjusting the signal distribution to the signal transmission path according to the number of connections of the signal receiving means to the connection connector is provided. The present invention is characterized in that the supply signal to each signal receiving means is compensated according to the insertion / removal of the connection connector.

As the signal distribution adjusting means, depending on the number of connection of the signal receiving means to the connection connector, for example,
(A) means for adjusting the voltage applied to the signal transmission path, (b)
Means for adjusting the current of the signal transmission path, (c) means for adjusting the impedance matching state between the signal transmission path and each signal receiving means, (d) or means for adjusting the amplification of the signal of the signal transmission path, etc. It is preferable to include any one of the above means.

Further, the supply signal processing system of the present invention comprises the structure of the supply signal compensating device described above, and includes two or more signal receiving means (for example, a signal receiving module, a coupler, an optical / electrical conversion device). Interface with a module or the like, and two or more signal processing means (for example,
Signal processing module, etc., and each signal receiving means transfers a signal received from a signal transmission line (for example, an electric bus line, an optical fiber cable, etc.) to the above-mentioned two or more signal processing means corresponding to an interface. Each signal processing means processes the given signal.

[0026]

In general, when the signal from the signal output means is output to the signal transmission path and this signal is given to the insertable / removable signal reception means, the number of the signal reception means connected to the signal transmission path does not increase. For the signal output means, the load becomes heavy, so if this load becomes too heavy,
The signal power becomes insufficient, and the quality of the signal given to each signal receiving means deteriorates.

Therefore, in the present invention, the number of signal receiving means connected to the signal transmission path is obtained from the connection state signal. Then, signal distribution adjustment (for example, adjustment by electrical or optical signal) is performed on the signal of the signal transmission line according to the number of connections, so that the quality of the signal given to the signal receiving means is not deteriorated. can do.

Further, in the supply signal processing system including the supply signal compensating apparatus having the above-described configuration, the signal processing means corresponding to each signal receiving means is provided, so that the signal whose signal quality is compensated is converted into the signal. By being supplied to the receiving means, it becomes possible to guarantee a reliable operation even in the signal processing means compatible with the interface.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention applied to a transmission device will be described with reference to the drawings. Therefore, in order to solve the above-mentioned conventional problem, in this embodiment, the insert data INSD and the insert clock are changed due to the change in the number of connections of the test control circuit and the interface module INF connected to the insert data INSD line and the insert clock INCK line. The configuration is such that the disturbance of the waveform of INCK is minimized.

[Summary]: In order to do so, the drive capacity of the test control circuit is improved, and the insert data INSD and the insert clock INCK are added.
Interface module INF connected to the line
By controlling the supply of electric power supplied to the lines of the insert data INSD and the insert clock INCK in accordance with the change in the number of connections (mounting) of the insert data INSD and the insert clock INCK, the disturbance of the waveform of the insert data INSD and the insert clock INCK is minimized. To do. In order to control the power supply, it is intended to realize it by controlling the value of the terminating resistor inserted in the line of the insert data INSD or the insert clock INCK.

Further, by increasing the driving capability of the test control circuit as described above, the test control circuit is driven so as not to disturb the waveform even when the load becomes heavy. Furthermore, insert data INSD and insert clock IN of this transmission device
Interface module I connected to CK line
A means for monitoring the mounting state of the NF is provided. Then, the above-mentioned insert data INSD and insert clock I based on the information on the number of mounted boards collected by the monitoring means.
It controls the power supply to the NCK line. In other words, the power supply to the line is controlled by controlling the value of the terminating resistance, and thereby the disturbance of the waveform due to reflection or the like is suppressed as much as possible.

FIG. 1 is a block diagram of a transmission device according to an embodiment. In FIG. 1, the transmission device mainly includes a test control circuit 1b and interface modules INF1 to INFn.
And a characteristic resistance control unit 10 and a characteristic mounting number determination unit 11. Furthermore, the test control circuit 1
Characteristically, b is provided with drivers D1 to Dn and a power supply control circuit PCR. And driver D
Outputs 1 to Dn are given to the insert data INSD line or the insert clock INCK line, and the interface modules INF1 to INFn are provided to this line.
Is connected as a load. The control of power supply to this line is configured to be adjusted by the power supply adjusting circuit PCR connected to this line.

Further, each interface module INF
1 to INFn are configured to be able to receive the insert data INSD or the insert clock INCK from the insert data INSD line or the insert clock INCK line by the receivers Rx1 to Rxn and use them for internal processing. Furthermore, characteristically, each of the interface modules INF1 to INFn outputs interface module mounting information indicating that they are connected, when connected to the corresponding connectors k1 to kn, and determines the number of mounted boards. It is configured so that it can be given to the section 11. The power supply adjustment circuit PCR of the test control circuit 1b receives the power from the fixed power source Vcc by the series resistance of the fixed resistor rc1 and the variable resistor circuit rc2, and the fixed resistor rc1 and the variable resistor circuit rc2. rc
The divided voltage output of 2 is applied to the insert data INSD line or the insert clock INCK line. The variable resistance circuit rc2 is configured such that the resistance value is set by the resistance value control signal from the resistance value control unit 10.

Further, the interface module INF1
When mounting information indicating whether INFn is mounted on the connectors k1 to kn is provided to the mounting number determination unit 11, the mounting number determination unit 11 outputs resistance value control information according to the mounting number, and the resistance value control unit Give to 10.

With this configuration, the connectors k1 to kn of the interface modules INF1 to INFn are formed.
The terminating resistance value of the power supply adjusting circuit PCR is adjusted according to the number of mounted boards, and the power supply to the insert data INSD line or the insert clock INCK line is adjusted according to the number of mounted boards. As a result, the necessary power supply control is performed even when the number of mounted boards changes, and the interface module IN
Insert data INSD supplied to F1 to INFn
Also, it is possible to suppress the disturbance of the waveform of the insert clock INCK as much as possible.

Therefore, the mechanism of power supply to the insert data INSD line or the insert clock INCK line in the transmission apparatus of the first embodiment of FIG. 1 will be described in detail below.

That is, in FIG. 1, the test control circuit 1b is described by omitting it as an insert data INSD line or an insert clock INCK line, but in an actual transmission device, the insert data INSD line and the insert clock INCK line are not shown. It is an annex. Therefore, the drivers D1 to Dn also have the insert data INSD line and the insert clock INC.
Two systems are provided corresponding to the K line. However, in the description of FIG. 1, one system will be intensively described as the insert data INSD line or the insert clock INCK line.

Therefore, the drivers D1 to Dn in FIG. 1 use the insert data INSD or the insert clock INCK.
Receive. The drivers D1 to Dn basically have the same characteristics. Such drivers D1-D
n is, for example, L commercially available from various manufacturers
S240 or the like can be used as a driver.
The number of drivers is provided in correspondence with the number of interface modules INF1 to INFn to be mounted.

If, for example, the current that can be passed by one driver D1 is I1, and the current that can be passed by the driver D2 is I2, then n drivers D1 to Dn are provided.
The total value I of the currents that can flow in is expressed by the following equation (1). I = I1 + I2 + I3 + ... + In (1) Formula From this formula (1), it is possible to increase the driving capability by connecting a plurality of drivers, and to drive even when the load increases. Is possible. When the HD74LS240 (manufactured by Hitachi, Ltd.) is used as the driver, the inflow current of the driver is about 24 mA.

(Determination and Setting of Termination Resistance Value for Line): Further, the determination or setting of the resistance values rc1 and rc2 of the power supply adjusting circuit PCR of the test control circuit 1b is as follows. In other words, as seen from the insert data INSD line or the insert clock INCK line,
An AC characteristic equivalent circuit of the power supply adjusting circuit PCR is expressed as shown in FIG.

In FIG. 4, the characteristic of this AC characteristic equivalent circuit is expressed by the following equation (2). 1 / Zo = 1 / rc1 + 1 / rc2 + n / R (2) Formula 1 / Zo is the interface module INF1 to I
Impedance Z _{L of the} backboard on which NFn is mounted
Is. Incidentally, R is a protective resistance for the line. From the above, the resistance value of the variable resistance circuit rc2 is calculated by the following equation (3).
It is represented by. 1 / rc2 = 1 / Z _L −1 / rc1-n / R (3) Equation Further, the DC characteristic equivalent circuit of the power supply adjusting circuit PCR of FIG. 1 is expressed as shown in FIG. In FIG. 5, the parallel resistance of the resistance rc1 and R / n is r. And
When the current flowing through the parallel resistance r is i, the following equation (4)
Have a relationship. Vcc-i · r> 0 (4) Equation (4) can be further transformed into the following Equation (5). i <Vcc / r ≦ I _OLmax (5) Formula _IOLmax represents the maximum output current flowing into the driver. Then, from the above equation (5), rc
The relationship between 1 and n is expressed by the following equation (6). Vcc ≦ I _OLmax · R · rc1 / (R + n · rc1) Expression (6) Further, it is expanded and expressed as the following Expression (7). rc1 ≦ −R · Vcc / (Vcc · n−R / I _OLmax ) (7) Expression Since the value of rc1 is positive, the following expression (8) holds. Vcc · n−R · I _OLmax <0 Equation (8) Further, the above Equation (8) is modified to obtain the following Equation (9). n <R · _IOLmax / Vcc (9) From the above, the number of mounted interface modules INF depends on the maximum value of the current flowing into the driver. Then, for example, R = 10 kΩ, Z _L = 50Ω, Vcc =
When the number of mounted interface modules INF is 1 to 20 in the case of 5V, the value of the terminating resistor rc1 with respect to _IOLmax can be represented by a graph as shown in FIG. This Z _L = 50Ω is a standard impedance value of a microstrip line, a coaxial line, or the like.

In FIG. 6, four examples are shown as characteristics. Characteristic curve for _I OLmax = 24mA First, the characteristic curve of the second case the _I OLmax = 48 mA, the characteristic curve in the case of _I OLmax = 72 mA to the third,
Fourth, the characteristic curve in the case of I _OLmax = 96 mA is shown.

Furthermore, the relationship between rc2 and the number of mounted substrates n is expressed by the following expression (10) from the above expression (3). _{rc2 = R · Z L · rc1} / (R · rc1-R · Z L) · (1-Z L · rc1 · n / (R · rc1 · R · Z L)) -1 ...... (10) equation and The value of the equation (10) can be expressed by almost the same equation (11). R · Z _L · rc1 / (R · rc1−R · Z _L ) · (1 + Z _L · rc1 · n / (R · rc1-R · Z _L )) (11) Expression and the above-mentioned R / Z _L・ rc1 / (R ・ rc1-R ・
Since Z _L ) · n is very small, it can be approximated to the above equation (11). Then, the terminating resistance rc of the power supply adjusting circuit PCR
2 can be represented by the graph of FIG. In FIG. 7, the solid line is the characteristic curve of the theoretical value according to the above equation (10), and the dotted line is the approximate value according to the above equation (11).

Then, the value of rc1 shown in FIG.
When I _OLmax = 48 mA, rc1 = 100Ω. Further, the value of rc2 can be calculated from the above equation (11) by the following equation (1
Represented by 2). rc2 = 100 + n Equation (12) (Structure of power supply adjustment circuit PCR): This (12)
From the equation, the variable resistance circuit rc2 of the power supply adjusting circuit PCR
Can be configured as shown in FIG. That is, in FIG. 8, the insert data INSD line of the line impedance Zo or the insert clock I
A fixed power supply Vcc (for example, +5 V) of 100Ω is connected to the NCK line as a fixed resistor rc1. Further, from the line, interface modules INF1 to I
As a protection resistor R for protecting NFn, 10 kΩ /
n sheets are connected between the line and Vcc.

From the above equation (12), in the variable resistance circuit rc2, series resistors re21 to re2n are connected in series between the line and the ground terminal E.
Then, re21 is 100Ω, and the remaining re22 to re
2n is set to 1Ω. Further, in order to adjust the power supply (current supply) to the line according to the number of mounted boards, the 1Ω series resistors re22 to re2n are bypassed by using the relay switches re1 to ren as necessary, and a combined series resistance value is obtained. To reduce or increase the combined series resistance value without bypassing. By doing so, the combined series resistance value of the variable resistance circuit rc2 can be varied from a minimum of 100Ω to a maximum of 100Ω + 1Ω × n according to the number of mounted interface modules INF.

Then, the relay switches re1 to r1 shown in FIG.
ON / OFF of en is controlled by a resistance value control signal from the resistance value control unit 10 (FIG. 1). Then, when the number of the interface modules INF mounted increases (is inserted into the connector), the combined series resistance value of the variable resistance circuit rc2 is increased in order to increase the voltage applied to the insert data INSD line or the insert clock INCK line. Relay switches re1 to r
Control en on and off.

When the number of interface modules INF mounted is reduced (removed from the connector), the variable resistance circuit rc2 is combined in order to reduce the voltage applied to the insert data INSD line or the insert clock INCK line. The relay switches re1 to ren are turned on and off so that the series resistance becomes small.

(Insertion / Removal of Interface Module INF): Next, the interface module INF1
The operations in the case of inserting (mounting) into the connectors k1 to kn of the backboard of ˜INFn and in the case of removing the connectors will be described with reference to FIG. In FIG. 9, the interface modules INF1 to INFn are connected to backboard connectors k1 to k.
When inserted (mounted) in the n, the connection line IFMNT-LINE between the interface modules INF1 to INFn and the mounted number determination unit 11 through the connectors k1 to kn.
(1) to (n) electrically form a closed loop.

That is, each connection line IFMNT-LIN
E (1) to (n) are interface modules INF
Since they are connected to the ground terminal E inside 1 to INFn, they are set to low level. Then, the low level signal of each line is given to the mounting number determination unit 11.

On the other hand, the interface module INF1
~ INFn is removed from the backboard connectors k1 to kn, the interface modules INF1 to INF
connection line IFMNT between n and the mounting number determination unit 11
-LINE (1) to (n) electrically form an open loop. That is, the connection line IFMNT-LINE (1)-
(N) becomes open. In this state, the mounting number determination unit 1
Given to 1.

(Mounted Number Judging Section): FIG. 9 is a functional block diagram of an example of the mounted number judging section 11. In FIG. 9, the mounting number determination unit 11 mainly includes a parallel / serial conversion circuit 11a, a counter 11b, and an inverter circuit 1.
1c1 to 11cn and resistor circuits r31 to r3n.

The mounting number determination unit 11 incorporates connection lines IFMNT-LINE (1) to (n) with the interface modules INF1 to INFn. Then, the connection line thus taken in has a fixed electric power Vcc (for example, +5 V) on the input side from the resistors r31 to r31.
It is connected via r3n. At the same time, the connection lines IFMNT-LINE (1) to (n) are connected to the inverter circuits 11c1 to 11cn.

((When connected to the interface module)): Therefore, when the connection with the interface modules INF1 to INFn is made, a low level signal is given to the inputs of the inverter circuits 11c1 to 11cn. And the inverter circuit 1
The outputs of 1c1 to 11cn output a high level signal and give it to the parallel / serial conversion circuit 11a. And
A frame pulse and a clock are applied to the parallel / serial conversion circuit 11a, and the inverter circuit 1
The output signals 1c1 to 11cn are converted into serial data and given to the counter 11b at the counter stop start line.

The clock at this time is given at the timing shown in FIG. 11 (1) (a) of the operation timing chart. Further, the frame pulse is given at the timing as shown in FIG. Furthermore, parallel /
The output of the serial conversion circuit 11a is output at the timing as shown in FIG. That is, the mounting state of one interface module INF is represented by the cycle of one clock pulse. Then, during the period of one frame pulse, the mounting states of the interface modules INF1 to INFn are edited into serial data and output.

The counter 11b shown in FIG. 9 uses the serial data from the parallel / serial conversion circuit 11a (see FIG. 1).
1 (c)) to interface modules INF1 to I
Count the number of mounted NFn. Then, the counter value is output at the timing as shown in FIG. 11D and given to the termination resistance value control unit 10.

((When the interface module INF is not connected)): When the interface module INF is not connected, the connection lines IFMNT-LINE (1) to (n) in FIG. 9 are open. Then, a high level signal is given to the inverter circuits 11c1 to 11cn, and the inverter circuit 11c
1 to 11cn provide a low-level signal to the parallel / serial conversion circuit 11a. Then, the parallel / serial conversion circuit 11a edits (multiplexes) the low-level signals from the inverter circuits 11c1 to 11cn into serial signals,
The serial data is given to the counter 11b. The counter 11b counts the number of mounted boards from a given serial signal. However, since the low level signal is multiplexed, it is determined that the counter is not mounted, and the counter corresponding to this is determined. Output the value.

((Interface module INF1,
(When 3, 4, and 7 are connected)): FIG. 12 shows the operation timing of the mounted number determination unit 11 when the interface modules INF1, 3, 4, and 7 are mounted.
It is shown in (Part 2). In this case, the signals of the levels shown in FIGS. 12C to 12L are given to the inputs of the inverter circuits 11c1 to 11cn of the mounting number determination unit 11. That is, the connection line IFMNT-LINE
(1), (3), (4), and (7) are given at a low level, and the other connection lines are given at a high level.

Then, the inverter circuits 11c1 to 11c
These signals given to the input of n are inverted and given to the parallel / serial conversion circuit 11a. Then, it is edited (multiplexed) into serial data and given to the counter 11b at a timing as shown in FIG.

The timing m1 in FIG. 12 (m) is a signal portion representing the mounting state of the interface module INF1. The timing m3 in FIG. 12 (m) is a signal portion representing the mounting state of the interface module INF3. Further, the timing of m4 in FIG. 12 (m) is a signal portion representing the mounting state of the interface module INF4. Furthermore, the timing of m7 in FIG. 12 (m) is a signal portion representing the mounting state of the interface module INF7.

Then, the counter 11b counts the number of mounted boards from the serial data, and outputs the counter value at the timing shown in FIG. 12 (n). That is, the counter values 0 to 4 are output as shown in FIG.

(Structure of Resistance Value Control Unit 10): FIG.
FIG. 3 is a configuration diagram of an example of a resistance value control unit 10. This FIG.
In the above, the resistance value control unit 10 mainly uses the decoder 10a.
And latches 10b1-10bn, 10c1-10cn
And exclusive OR circuits 10d1-10dn, 10e1
10en and OR circuits 10f1 to 10f2.

Then, the decoder 10a decodes the counter value indicating the number of mounted boards from the mounted board number determination unit 11, and decodes the output DEC-LINE (1) to DEC-LINE (1) to the counter values corresponding to the counter values.
(N) is given to the latch circuits 10b1 to 10bn. A frame pulse is applied to the latch circuits 10b1-10bn, and the decode output DEC-LINE is output.
(1) to (n) are latched, and the latch outputs are output to the next latch circuits 10c1 to 10cn and the exclusive OR circuits 10d1 to 10d1.
It is given to 10 dn. The latch circuits 10b1 to 1
0bn has a function of preventing the influence of the change in the counter value on the subsequent circuits (the OR circuits 10f1 to 10f2, etc.).

Then, the latch circuits 10c1 to 10c
n latches the latch output given from the latch circuits 10b1 to 10bn by the frame pulse further given, and the latch output is exclusive OR circuits 10d1 to 10d.
dn and the exclusive OR circuits 10e1 to 10en.

Then, the exclusive OR circuits 10d1-10
dn performs an exclusive OR between the latch outputs of the latch circuits 10b1 to 10bn and the latch outputs of the latch circuits 10c1 to 10cn, and supplies this exclusive OR output to the next exclusive OR circuits 10e1 to 10en. There is. That is,
The exclusive OR circuits 10d1-10dn are connected to the latch outputs of the latch circuits 10b1-10bn and the latch circuit 10c.
A change in the number of mounted boards and a change in the counter value are detected from the latch output of 1 to 10 cn, and the next exclusive OR circuit 10e is detected.
It plays the role of inverting the output of 1 to 10 en.

Then, the exclusive OR circuits 10e1-10e1.
10en performs coincidence detection between the latch outputs of the latch circuits 10c1 to 10cn and the exclusive OR circuits 10d1 to 10dn, and supplies the outputs to the OR circuits 10f1 and 10f2. The OR circuits 10f1 and 10f2 perform an OR operation on the output signals from the exclusive OR circuits 10e1 to 10en, and the ON / OFF control of the switches of the relays re1 to ren of the power supply adjusting circuit PCR is performed by this OR output. Is configured to do. By turning on / off the switches of the relays re1 to ren, the termination resistors re22 to re2n are selected according to the number of the interface modules INF mounted, and the termination resistance value rc2.
Is determined.

That is, the interface module INF
When 1 to INFn are all mounted on the connection connector, the relays re1 to ren are turned off and the termination resistance value r
c2 is 100Ω + 1Ω × n.

(Effect of One Embodiment): According to the configuration of the transmission apparatus of the above one embodiment, even if the number of mounted interface modules INF changes, the number of mounted pieces of mounting information from each interface module INF. A counter value (mounting number) is given to the resistance value control unit 10 as resistance value control information according to the number of mounting sheets, and is supplied to the determining unit 11 to adjust the power supply according to the counter value. Turn on the relays re1 to ren of the circuit PCR,
Since the resistance value for termination of the variable resistance circuit rc2 is adjusted by the off control, the voltage applied to the insert data INSD line or the insert clock INCK line can be adjusted.

With this configuration, even if the number of mounted interface modules INF changes, the insert data INSD or the insert given from the drivers D1 to Dn to each interface module INF through the line is adjusted automatically. The clock INCK can be given without being disturbed.

Therefore, even if the number of interface modules INF mounted in the transmission apparatus is changed more frequently than in the past, it is considered that the interface modules are not affected at all. As a result, the reliability of the transmission device can be greatly improved.

It is considered that the above-mentioned transmission device will greatly improve reliability in the future when applied to a dedicated line node device (CNE) which accommodates a line and realizes multiplexing and line editing functions. To be

(Other Embodiments): (1) FIG. 13 is a diagram showing another configuration example (PCR1) of the power supply adjusting circuit in the test control circuit 1b. In the above-described embodiment, as shown in FIG. 1, the power supply adjustment circuit PCR uses the fixed power Vcc.
(For example, + 5V), the divided voltage output of the fixed resistor rc1 and the variable resistance circuit rc2 is applied to the insert data INSD line or the insert clock INCK line, but in the configuration of FIG. 13, the fixed power Vcc is changed. Variable resistance circuit rc3 (for example, 100Ω + 1Ω × n)
And a fixed resistor rc4 (for example, 100Ω) is applied to the insert data INSD line or the insert clock INCK line. And
The variable resistance circuit rc3 is realized by the configuration described in FIG. 8 above. Then, ON / OFF control of the relays re1 to ren is performed by the resistance value control signal of FIG. 1 described above, and the resistance value of the terminal end of the variable resistance circuit rc3 is adjusted.

When the interface modules INF1 to INFn are mounted by such a configuration, for example, the resistance value of the variable resistance circuit rc3 is set to the minimum value 10
It is set to 0 Ω, and the resistance value is increased from 100 Ω each time the interface module is removed, so that the insert data INSD line or the insert clock IN
By adjusting the voltage applied to the CK line, it is possible to minimize the disturbance of the insert data INSD or the insert clock INCK.

(Other Embodiments): (2) FIG. 14 is a block diagram of a resistance value control unit 10A of another embodiment. In the resistance value control unit 10 of FIG. 10 of the above-described embodiment, the decoder 10
For DEC-LINE (1) to (n), which are the outputs of a, the two-stage latch circuits 10b1 to 10bn,
10c1 to 10cn and a two-stage exclusive OR circuit 10d
1 to 10dn, 10e1 to 10en,
Although the counter value (mounting number) from the mounting number determining unit 11 is received by the decoder 10a, the influence of the change is protected, but such a protecting function may be a little simpler. Such a configuration is shown in FIG. That is, in FIG. 14, the decoder 10a
The DEC-LINE (1) to (n), which are the outputs of the above, are received by the one-stage latch circuits 10b1 to 10bn and are latched and output by the frame pulse. It is also possible to use this latch output to generate a logical sum output by the logical sum circuits 10f1 and 10f2, and use this logical sum output to control ON / OFF of the relay of the power supply adjusting circuit PCR.

With the above structure, the structure can be simplified as compared with the structure of the resistance value control unit 10 of FIG. 10 of the above-described embodiment.

(Other Embodiments): (3) FIG.
FIG. 11 is a configuration diagram of a mounted number determination unit 11A according to another embodiment. The configuration of FIG. 15 is a configuration in which the parallel / serial conversion circuit 11a and the counter 11b are not provided in the configuration of FIG. 9 of the above-described embodiment. That is, FIG.
The mounting number determination unit 11A of No. 5 is the connection line IFMNT-L of the interface modules INF1 to INFn.
The INE (1) to (n) are connected to the inverter circuits 11c1 to 11c.
Receive at cn. As in the case of FIG. 9 described above, the connection lines IFMNT-LINE (1) to (n) are input with a resistance r.
It is connected to a fixed power source Vcc (for example, + 5V) via 31 to r3n (for example, about 10 kΩ).

Then, the inverter circuits 11c1 to 11c
n is for giving an inverted output signal to the resistance value control unit 10B of FIG. With such a configuration, the configuration of the mounting number determination unit 11A can be made very simple as compared with the above-described embodiment.

(Other Embodiments): (4) FIG.
[Fig. 6] is a configuration diagram of a resistance value control unit 10B of another embodiment. The resistance value control unit 10B receives the inverted output signals of the inverter circuits 11c1 to 11cn of the mounting number determination unit 11A of FIG. 15 described above, and uses the inverted output signals to relays re1 to ren of the power supply adjustment circuit PCR. On
The off control is performed. With such a configuration, it is possible to adjust the termination resistance value rc2 according to the number of mounted boards with a simpler configuration than the above-described embodiment.

(Other Embodiments) (5) In the above embodiments, the present invention has been described by taking the application to the transmission device as an example, but the present invention can also be applied to other devices and systems. In other words, if there is an environment in which a plurality of processing boards that can be connected to the bus line are mounted in a removable manner from a certain signal source in the device and the signals are distributed and supplied, then basically, Is considered to be effective by applying this invention. For example, it is an exchange device or an information processing device.

The present invention can also be applied to compensation of signal supply by a bus line in a system for supplying a signal to a plurality of processing devices through a bus line from a signal output device that supplies a signal.

(6) Further, in the above-mentioned embodiment, the power supply adjusting circuit PCR is operated by the power supply adjusting circuit PCR in accordance with the number of mounted boards to insert data INSD line or insert clock INC.
Although the example in which the voltage applied to the K line is adjusted has been described, a configuration in which the current in the line is positively adjusted may be used instead. Alternatively, the line impedance may be adjusted so that the waveform of the supply signal is not disturbed.

(7) Further, the signal to be distributed and supplied is not limited to a digital signal, and the present invention can be applied to compensate for distribution and supply of an analog signal.

(8) Furthermore, the mounting number determination unit 11 and
Regarding the specific configuration of the resistance value control unit 10, FIG. 9 and FIG.
Although the hardware configuration of the logic circuit is shown as 0, the configuration may be such that the number of mounted chips is determined by a program operation and the resistance value is controlled.

(9) Further, in selecting the resistors re1 to ren of the power supply adjusting circuit PCR of the above embodiment,
Although the example in which the relays re1 to ren are controlled to be turned on and off is shown, the relays may be selected by a semiconductor switch or the like without using the relays.

(10) Furthermore, in the above-mentioned embodiment, the transmission path of the test signal is the insert data I which is an electric signal transmission path.
Although it has been described as the NSD line or the insert clock INCK line, it may be an optical waveguide, an optical fiber cable, or the like. In such a case, the signal is transmitted as an optical signal through the optical waveguide, is optically branched by an optical coupler or the like, and is taken into the optical receiving module. When the number of optical receiving modules to be mounted increases when the optical receiving modules are inserted and removed, the optical power to the optical receiving modules may be insufficient and the quality of the optical signal may deteriorate. In this case, it is preferable to adjust the amplification of the optical signal according to the number of optical receiving modules connected to the optical waveguide. By adjusting the distribution of the optical signal in this way, it is possible to prevent the quality of the optical signal to the optical receiving module from deteriorating.

Further, good signal processing can be realized by converting the optical signal received by the optical receiving module into an electric signal and applying it to the signal processing module corresponding to the interface.

[0086]

As described above, according to the present invention, the signal output means for outputting the signal for use in the signal receiving means to the signal transmission line, and the signal from the signal output means can be inserted and removed by the connection connector. A signal transmission path for distributing to at least two or more signal receiving means, and at least two or more insertable / removable signal receiving means for receiving a signal from the signal transmission path through a connection connector, each signal receiving means being a connection connector Output a connection status signal indicating that the connection is established, and adjust the signal distribution to the signal transmission path according to the number of connections from the connection status signal to the connector of the signal receiving means. By compensating the supply signal to each signal receiving means in accordance with the insertion / extraction of the connection connector of each signal receiving means, even if the number of connections of each signal receiving means changes It can be given to the No. receiving means.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a transmission device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of an insert test system in a conventional example.

FIG. 3 is a configuration diagram of a transmission device of a conventional example.

FIG. 4 is an AC characteristic equivalent circuit diagram of an example.

FIG. 5 is a DC characteristic equivalent circuit diagram of an example.

FIG. 6 is a diagram showing a relationship between the termination resistance value rc1 and the number of mounted boards in one embodiment.

FIG. 7 is a relationship diagram between a termination resistance value rc2 and the number of mounted boards in one embodiment.

FIG. 8 is a configuration diagram of a power supply adjustment circuit according to an embodiment.

FIG. 9 is a configuration diagram of a mounting number determination unit according to an embodiment.

FIG. 10 is a configuration diagram of a resistance value control unit according to an embodiment.

FIG. 11 is an operation timing chart (1) of the embodiment.

FIG. 12 is an operation timing chart (2) of the embodiment.

FIG. 13 is a configuration diagram of a power supply adjustment circuit according to another embodiment.

FIG. 14 is a configuration diagram of a resistance value control unit according to another embodiment.

FIG. 15 is a configuration diagram of a mounting number determination unit according to another embodiment.

FIG. 16 is a configuration diagram of a resistance value control unit according to another embodiment.

[Explanation of symbols]

1b ... Test control circuit, 10 ... Resistance value control unit, 11 ... Mounting number determination unit, D1, Dn ... Driver, INF1 to INF
n ... interface module, J1 to Jn ... interface module mounting information, k1 to kn ... backboard connector, PCR ... power supply adjusting circuit, rc1 ...
Fixed resistor, rc2 ... Variable resistance circuit, Rx1 to Rxn ...
Receiver, Vcc ... Fixed power source.

Claims (5)

[Claims] 1. A signal output means for outputting a signal for use in the signal receiving means to a signal transmission path, and a signal from the signal output means is distributed to at least two or more signal receiving means which can be inserted and removed by a connector. And a signal transmission path for receiving the signal from the signal transmission path through a connection connector, and at least two insertable / removable signal reception means are provided. Each signal reception means is connected when connected to the connection connector. A connection state signal indicating that the signal receiving means is connected to the signal transmission path according to the number of connections from the connection state signal to the connection connector of the signal receiving means. A supply signal compensating method for compensating a supply signal to each signal receiving means according to insertion / removal of the connection connector. 2. The signal distribution adjustment adjusts a voltage applied to the signal transmission path, and adjusts a signal current of the signal transmission path according to the number of connections of the signal receiving means to the connection connector. 2. The signal distribution adjustment of either adjusting the impedance matching state between the signal transmission path and each signal receiving means or adjusting the amplification of the signal of the signal transmission path. The supply signal compensation method described. 3. A signal output means for outputting a signal for use in the signal receiving means to a signal transmission line, and a signal from the signal output means is distributed to at least two or more signal receiving means which can be inserted and removed by a connector. And a signal transmission path for receiving the signal from the signal transmission path through a connection connector, and at least two insertable / removable signal reception means, each signal receiving means being connected when connected to the connection connector. A connection status signal output means capable of outputting a connection status signal indicating that the signal is transmitted to the signal transmission path according to the number of connections to the connection connector of the signal receiving means. A configuration is provided in which signal distribution adjusting means for performing distribution adjustment is provided, and a signal supplied to each signal receiving means is compensated in accordance with insertion / extraction of the connection connector of each signal receiving means. A supply signal compensating device characterized by the above. 4. The signal distribution adjusting means adjusts a voltage applied to the signal transmission path according to the number of connections of the signal receiving means to a connector, and adjusts a current of the signal transmission path. A means for adjusting an impedance matching state between the signal transmission path and each signal receiving means, or a means for adjusting amplification of a signal on the signal transmission path. Item 5. The supply signal compensator according to Item 3. 5. A supply signal processing system provided with the supply signal compensating device according to claim 3 or 4, wherein two or more signal processing means are interfaced with the two or more signal receiving means. Each of the signal receiving means supplies the signal received from the signal transmission path to the two or more signal processing means corresponding to the interface, and each signal processing means processes the supplied signal. Supply signal processing system.