JPH0646787B2 - Auto pedestal level clamp circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to an improvement of an automatic pedestal level clamp circuit in an automatic brightness adjustment circuit of a television.

[Conventional technology]

An example of a conventional auto pedestal level clamp circuit is shown in FIG. In FIG. 2, 201 is a volume that outputs a divided voltage on the + side of the power supply voltage (hereinafter referred to as VDD) and the-side of the power supply voltage (hereinafter referred to as VSS), 202 is a diode, and 204, 205, 209, and 210 are capacitors. ,
Reference numerals 203, 206 and 208 are resistors, 207 is a transistor, 211 is a pedestal level clamp switch which opens and closes by a pedestal level clamp pulse, and 212 is an A / D converter which quantizes a composite video signal.

In FIG. 2, the diode connected to the intermediate terminal of the volume 201 clamps the composite video signal that has passed through the capacitor 205, and the clamped composite video signal is smoothed by the resistor 203 and the capacitor 204. According to the change in the smoothed potential, the transistor 207
The collector current of the capacitor changes and charging / discharging of the capacitor 209 occurs. As a result, when a bright screen with a large luminance signal in the composite video signal is obtained, the base potential of the transistor 207 rises, the collector current increases, and the capacitor 20 increases.
9 is discharged, and the potential of the capacitor drops. On the other hand, when the screen becomes dark with a small bright signal, the capacitor is charged and the potential rises.

FIG. 7 is a timing chart showing the relationship between opening and closing of the pedestal clamp pulse and the pedestal clamp switch with respect to the composite video signal for about H of the horizontal period (hereinafter referred to as H) of the composite video signal. ) Is a composite video signal, and FIG. 7 (B) is a high level signal from the rise of the horizontal cycle signal in the composite video signal with the DC level removed to the appearance of the luminance signal (hereinafter referred to as the back porch). A destal level clamp pulse is shown.

In FIG. 7 (C), the state in which both ends of the pedestal level clamp switch are conducting is shown as closed, and the state in which the pedestal level clamp switch is not conducting is shown as open, and the closing timing and the high level of the pedestal level clamp pulse in FIG. As a result, charges flow in and out of the DC blocking capacitor of the composite video signal so that the back porch voltage (hereinafter referred to as the pedestal level) and the voltage at the other end of the pedestal clamp switch become equal.

The reason why the auto-pedestal level clamp circuit is configured in this manner is that multi-gradation display becomes difficult when the image contrast is low such as time-division drive display of a liquid crystal television, and the dynamic range of gradation display is bright. There is a problem such as lack of gradation on a dark screen when adjusting to the screen. Therefore, by narrowing the dynamic range determined by the A / D converter and the like, the pedestal level is lowered on a bright screen to display many gradations of a bright image, while the pedestal level is increased on a dark screen to increase gradations of a dark image. Displaying requires an auto-pedestal clamp circuit that performs an averaged display.

[Problems to be solved by the invention]

However, since the circuit shown in FIG. 2 requires fine adjustment of the volume 201 of FIG. 2 in order to obtain a good display screen, the number of steps is increased, resulting in an increase in cost. Also, in FIG.
Since 5 and 209 cannot be integrated into an IC because they are 0.1 to several tens of microfarads, this circuit must be composed of individual parts, which leads to problems such as low cost and hindering miniaturization of the circuit. there were. Furthermore, in the circuit shown in FIG. 2, the output of the A / D converter is not fed back to the setting of the pedestal level, so it is necessary to precisely select the constants of the components that make up the circuit, and to the amplitude of the composite video signal. Versatility decreases.

An object of the present invention is to improve the above drawbacks and to provide a low cost, compact and highly versatile auto pedestal level clamp circuit.

[Means for solving problems]

The present invention detects the level of a luminance signal in a composite video signal, detects the first detection signal when the level is in the first region, and detects the second detection signal when the level is in the second region. Output,
Luminance signal level detector compares the output time of the first and second detection signals in a predetermined period, and outputs the first or second switch drive signal according to the length of the output time of the two signals. And a first switch and a second switch that operate according to the first and second switch drive signals and guide the first voltage and the second voltage to the pedestal level adjustment voltage applying section, respectively. The first or second voltage is applied to the composite video signal during a period corresponding to the pedestal level according to the level of the luminance signal.

〔Example〕

FIG. 1 is a circuit block diagram of an embodiment of the present invention. First
In the figure, the direction indicated by the arrow indicates the direction of signal travel,
Reference numeral 101 is a first gate circuit for passing a clock which is continuously input and indicated by 113 based on an output 114 of a lower luminance signal level detector indicating that the image is dark.
Is a first counting circuit for counting the number of dark states of the image by the clock passed through the first gate circuit 101 indicated by 116 during a specific period, and 103 is a higher luminance signal level detection indicating that the image is bright. A second gate circuit for passing the clock 113 on the basis of the output 115 of the measuring device; a second gate circuit 104 for counting the number of bright states of the image by the clock passing through the second gate circuit 103 indicated by 117 during a specific period; Counting circuit 105, a comparing circuit 105 for comparing the count values of the first and second counting circuits 102 and 104 indicated by 119 and 120 respectively, and 106 a result of whether or not "the screen is too dark" indicated by 121. Is a first latch circuit for reading and holding the output of the comparison circuit 105 at the end of a specific period, and 107 is a ratio giving a result of "screen is too bright" 122. A second latch circuit that reads and holds the output of the circuit 105 at the end of a specific period, 108 is connected to VDD as a DC potential, and the output of the first latch circuit indicated by 125 is "the screen is too dark" The first switch 109 which is closed at 110 is connected to VSS as a DC potential, and the second switch 110 which is closed when the output of the second latch circuit 107 shown at 126 is "the screen is too bright". Is the first and second switches 108 and 109
Pedestal level clamp switch connected to, 1
11 is a DC blocking capacitor for the input composite video signal,
112 is the pedestal level clamp switch 1 at the input end
4-bit A / D converter connected to 10 and DC blocking capacitor 111, 118 is the first at the beginning of a particular period.
And a reset signal for resetting the second counting circuits 102 and 104, 123 is a clock at which the first and second latch circuits 106 and 107 read the outputs 121 and 122 of the comparison circuit 105 at the end of a specific period, and 124 is During the non-display period such as the vertical blanking interval, the first and second latch circuits 106
And 107 are the first and second switches 108 and 10 respectively.
9 is a control signal for keeping it open, 127 is a pedestal level clamp pulse, and 128 is a 4-bit quantized output of the A / D converter 112.

In FIG. 1, first and second counting circuits 102, 1
04 is reset at the beginning of a specific period, and then clock 11 when there are many low parts of the luminance signal in the specific period.
3 can pass the first gate circuit 101 more times, while the number of times the third gate circuit 103 can pass the second gate circuit 103 is reduced, so that the first and second counting circuits 1 can end at the end of the specific period.
The count value outputs 119 and 120 of 02 and 104 are compared with the comparison circuit 1
05 performs comparison, the first latch circuit 106 reads the output “too dark”, and the second latch circuit reads the output “not too bright”. Then, when the first switch 108 is closed and the pedestal level clamp switch 110 is closed in the next specific period, the positive charge is positively charged due to the time constant determined by the resistance of the circuit and the capacitance of the DC blocking capacitor 111. The pedestal level of the composite video signal flowing into the A / D converter 112 is increased.

On the other hand, in FIG. 1, the first and second counting circuits 102 and 104 are reset at the beginning of a specific period, and then the clock 113 is set to the second level when there are many high luminance signal parts in the specific period. Since the number of times the gate circuit 103 can be passed is increased, while the number of times the first gate circuit 101 can be passed is decreased, the count value output 119 of the first and second counting circuits 102 and 104 at the end of the specific period. , 120 are compared by the comparison circuit 105, the output “too bright” is read by the second latch circuit 107, and the output “not too dark” is read by the first latch circuit 106.
Then, when the second switch 109 is closed by the output of the second latch circuit 107 and the pedestal level clamp switch 110 is closed in the next specific period, a positive charge flows out from the DC blocking capacitor 111 according to the circuit constant. Then, the pedestal level of the composite video signal input to the A / D converter 112 is lowered.

Further, when the high and low places of the luminance signal are almost the same in a specific period, the comparison circuit 1 is provided at the end of the specific period.
Reference numeral 05 designates the first and second counting circuits 10 within the range of inherent accuracy.
2 and 104 count outputs 119 and 120 are determined to be the same number,
The first and second latch circuits 106 and 107 read the outputs of the comparison circuit 105 "not too dark" and "not too bright", respectively. Then, during the next specific period, both the first and second switches 108 and 109 are opened, and the A / D
The pedestal level of the composite video input to the converter 112 does not change.

As a result, the output 1 of the comparison circuit 105 is output at the end of the specific period.
When 21 is “too dark”, the pedestal level input to the A / D converter 112 slightly rises during the next specific period, so that the level of the luminance signal input to the A / D converter 112 also rises. Form a feedback loop so that the "too dark" condition is mitigated.

On the contrary, at the end of the specific period, the output 12 of the comparison circuit 105 is
When 2 is “too bright”, the pedestal level is lowered, and a feedback loop is formed so that the “too bright” state is alleviated, and the pedestal level is automatically adjusted.

FIG. 3 is a circuit diagram of the first and second gate circuits 101 and 103 used in the embodiment of FIG. 1, and FIG. 3 (A) and FIG.
(B) is the first gate circuit, and FIGS. 3 (C) and 3 (D) are the second gate circuits.
It is a gate circuit of.

In FIG. 3, the same numbers as in FIG. 1 correspond to the same signals,
Reference numeral 301 denotes a high level output when the level of the brightness signal input in the A / D converter is equal to or lower than a specific threshold value.
Lower comparator output to be input to the gate circuit of
2 is the most significant bit output of the A / D converter, 303 is A
The second upper bit output of the / D converter, 304 is the upper comparator output that operates in the same manner as the comparator that performs the output 302 or has a high threshold value, and 305 is an AND circuit, 306 is a NOR circuit, and 307 is an inverter. . The circuits of FIGS. 3 (A) and 3 (B) as the first gate circuit are such that, when the level of the luminance signal is low, the output 301 of the lower comparator becomes high level or the output of the A / D converter When both the most significant bit output 302 and the second bit output 303 are low level, it is judged as "dark" and the clock 113 is passed, while the output 301 of the comparator is low level when the luminance signal level is high. , Or the high-order 2 bit outputs 302 and 303 are at a high level, and it is judged as “bright” and the clock is not passed.

The second gate circuit shown in FIGS. 3 (C) and 3 (D) shows that the output 304 of the higher-order comparator becomes low level when the luminance signal level is high, or the higher-order 2-bit output 3
Both 02 and 303 go to high level and are "bright"
When the luminance signal level is low, the output 304 of the comparator becomes high level, or at least one of the high-order 2 bit outputs 302 and 303 becomes low level, and it is determined that it is “dark”. Do not pass the clock.

FIG. 4 is a circuit diagram of the first and second counting circuits 102 and 104 and the comparison circuit 105 used in the embodiment of FIG. In FIG. 4, the same numbers as in FIG.
1, 402, 403, 404, 405, 406, 40
7, 408, 409, 410, 411, 412 are frequency dividers, φ is a clock input, Q is a frequency division output, R is a reset input, 413, 414, 415, 416 are inverters,
417, 418, 419 and 420 are AND, 421 and 4
22 is an OR, 423 is an air exclusive NOR, 424 is a block surrounded by a dotted line is a first counting circuit, 425
The block surrounded by the dotted line indicated by is the second counting circuit, and the remaining part is the comparison circuit.

In FIG. 4, for example, in the case where there are many low-brightness signals “too dark”, the output of the frequency divider 406 is between 32 and 63 clocks 116 input to the first counter 424 during a specific period. When the output of the frequency divider 412 is at the low level because the clock 117 input to the second counter 425 is 31 or less, the AND 418 is at the high level. And 122 go high and low, respectively, resulting in "too dark".

If the number of clocks 116 input to the first counter 424 during a specific period is 16 to 31 and the number of clocks 117 input to the second counter 425 is 31 or less, the frequency dividers 405, 406, Output 1 of 411, 412
19 and 120 are high level, low level, low level, and low level, respectively.
Since 3 and AND 417 are at high level, the outputs 121 and 122 of the comparator circuit are also at high level and low level, respectively, which results in "too dark".

In addition to the above two examples in FIG.
Also, assuming that the maximum value of the clocks 116 and 117 that can be input to the second counting circuits 424 and 425 is within 63 shots, the comparison circuit operates with the comparison accuracy of 16 shots even though the result “too dark” is output. .

On the contrary, in the case of “too bright” where there are many high luminance signals during a specific period, the number of clocks 117 input to the second counting circuit 425 is equal to the number of clocks 116 input to the first counting circuit 424. Comparison accuracy is 1 because it is more than the number
As six shots, the outputs 121 and 122 of the comparison circuit become low level and high level, respectively, and the result "too bright" is output.

In addition, the first and second counting circuits 424 and 4
If the numbers of the clocks 116 and 117 input to 25 match within 16 shots of the comparison accuracy, the output 12 of the comparison circuit
1 and 122 are both low level, "not too dark"
And the result is "not too bright".

FIG. 5 shows the first and second latch circuits 106 and 107 and the first and second switches 108 and 10 of the first embodiment shown in FIG.
9 is a circuit diagram showing 9, a pedestal level clamp switch 110, and a DC blocking capacitor 111. FIG.

5, the same numbers as in FIG. 1 correspond to the same signals,
Reference numeral 501 denotes a data type flip-flop (hereinafter referred to as D-FF) used as the first latch circuit 106 in FIG. 1, where D is a data input terminal and an output 121 of the comparison circuit.
Is input and R is a reset input terminal for inputting a signal 118 for opening both the first and second switches in a vertical period or the like, Q is a normal output, QB is an inverted output, and 502 is a first output.
Below the D-F used as the second latch circuit in the figure, 503 is the P-MOS used as the first switch 108 in FIG.
When the contents held and output by the D-FF 501, which is the first latch circuit, are "too dark" in the FET, D-
Since the QB output of the FF 501 is low-level, the first switch 503 is closed, and 504 is the N-MOSFET used as the second switch 109 in FIG. 1 and the D-FF 502 which is the second latch circuit. D-FF502 when the contents held / output are "too bright"
Q output becomes high level, the second switch 504 is closed, 505 is an inverter, 506 is a transmission gate, the inverter 505 and the transmission gate 506 form a pedestal level clamp switch, and 507 is a DC blocking of the composite video signal. It is a condenser.

FIG. 6 is a timing chart showing an example of the timings of the reset signals of the first counting circuit and the second counting circuit and the read clocks of the first latch circuit and the second latch circuit for the composite video signal.

In FIG. 6, a specific period is one horizontal cycle, and FIG.
6A is a composite video signal, FIG. 6B is a reset pulse output at the beginning of a specific period, and FIG. 6B is a reading pulse output at the end of a specific period.

In FIG. 1, a smoothing circuit including a resistor and a capacitor is arranged between the connection portion of the first and second switches 108 and 109 and the pedestal level clamp switch 110, and if the auto pedestal level clamp function is weakened, a small-amplitude composite image is obtained. Enabled for signals.

If a control function is added to the first latch circuit and the second latch circuit so that the timing when the first switch and the second switch are closed becomes the same timing as the pedestal clamp switch, the pedestal level clamp switch becomes It can be omitted.

This is considered an application of the invention.

When the highest and lowest comparators of the A / D converter are used as the brightness signal level detector, the data input to the A / D comparator causes overflow and underflow, and the respective display portions are completely The ratio of white to safe black matches, and the contrast of the display device can be effectively used.

Further, it is convenient to use the sampling clock of the A / D converter or its inversion for the clock passing through the first gate circuit and the second gate circuit.

In addition, in order to finely adjust the pedestal level clamp, the first switch 108 and the second switch 1 in FIG.
09 and the pedestal level clamp switch 110 may be connected to a DC potential such as VDD or VSS with a variable resistor or a fixed resistor. Further, when considering the temperature characteristics of the liquid crystal panel or the like, the material of the resistor may be selected so that the change in the resistance value of the resistor due to the temperature becomes the optimum value for adjustment. The circuit can also be applied to a CRT display type television.

〔The invention's effect〕

As is clear from the above description, according to the present invention, since the auto-pedestal level clamp circuit can be composed almost of a digital circuit, it is easy to form an IC, so that the cost of parts can be reduced and the size can be reduced.

Further, since the pedestal level is determined by feeding back the output of the luminance signal level detector such as the A / D converter, a high quality screen can be obtained without adjustment, and the adjustment cost can be reduced. The versatility is improved because there are almost no constraints on the amplitude.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional auto pedestal level clamp circuit, and FIGS. 3 (A) and 3 (B) are of the first embodiment of FIG. A first gate circuit diagram, FIGS. 3C and 3D are circuit diagrams showing examples of the second gate circuit of the first embodiment, and FIG. 4 is a first circuit diagram of the embodiment of FIG.
And FIG. 5 is a circuit diagram showing a circuit example of a second counting circuit and a comparison circuit, and FIG. 5 is a first and second latch circuit and a first circuit of the embodiment of FIG.
And FIG. 6 is a circuit diagram showing a circuit example of a second switch, a transmission gate, and a DC blocking capacitor. FIG. 6 shows an embodiment of the present invention, FIG. 6 (A) is a composite video signal, and FIG. 6 (B) is a first.
Reset signal for the second counting circuit and the second counting circuit, FIG.
(C) is a waveform diagram of each of the read clocks of the first latch circuit and the second latch circuit, FIG. 7 illustrates a conventional technique, FIG. 7 (A) is a composite video signal, and FIG. 7 (B). ) Is a pedestal level clamp pulse, and FIG. 7 (C) is a waveform diagram of opening and closing timing of the pedestal level clamp switch. 101 ... First gate circuit, 102 ... First counting circuit, 103 ... Second gate circuit, 104 ... Second counting circuit, 105 ... Comparison circuit, 106 ... First latch circuit 107 ... second latch circuit, 108 ... first switch, 109 ... second switch.

Claims (4)

[Claims] 1. An automatic pedestal level clamp circuit for applying a pedestal level adjustment voltage to a composite video signal according to the level of a luminance signal in the composite video signal during a period corresponding to the pedestal level of the composite video signal. , A brightness signal level detector that detects the level of the brightness signal, and outputs a first detection signal when the level is in the first region and a second detection signal when the level is in the second region When,
Comparing means for comparing the output times of the first and second detection signals in a predetermined period and outputting a first or second switch drive signal according to the length of the output time of the two signals; A first switch and a second switch, which operate according to the second switch drive signal and respectively guide the first voltage and the second voltage to the pedestal level adjustment voltage applying section, are provided, and the first switch and the second switch are provided according to the level of the luminance signal. Then, the automatic pedestal level clamp circuit is characterized in that the first or second voltage is applied to the composite video signal during a period corresponding to the pedestal level. 2. The luminance signal level detector, when the data from the A / D converter for quantizing the luminance signal is in the first bit area, sends the first detection signal to the second bit area. The auto pedestal level clamp circuit according to claim 1, wherein the second detection signal is output at a certain time. 3. Comparing means outputs first and second gate circuits for controlling clock passage based on the first and second detection signals, respectively, and signals from the first and second gate circuits. First and second counting circuits for counting respectively, and the first and second counting circuits.
A comparison circuit that compares the count values of the counting circuit in a predetermined period and outputs a first or second comparison signal according to the magnitude of the two count values, and is latched by the first and second comparison signals, The auto pedestal level clamp circuit according to claim 1, wherein the auto pedestal level clamp circuit comprises first and second latch circuits that output first and second switch drive signals, respectively. 4. The automatic pedestal level clamp circuit according to claim 1, wherein the predetermined period is a horizontal period of the composite video signal.