JP3416304B2 - Display device drive circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a drive circuit of a display device capable of color display of 16 gradations.

[0002]

2. Description of the Related Art Some conventional active matrix type color liquid crystal display devices employ a PWM (pulse width modulation) method to enable color display of 16 gradations.
FIG. 5 shows the configuration of the driving circuit of such a color liquid crystal display device.
Shown in. As shown in the figure, the conventional driving circuit of a liquid crystal display device includes a shift register 10, a data register 20, a latch 30, a 4-bit comparator 40, a 4-bit counter 50.
And a level shifter sample / hold circuit 60. This drive circuit receives a digitized 4-bit grayscale data signal for each of the three primary colors as video input data, samples the grayscale level input voltage corresponding to each data signal, and outputs it to each pixel electrode. is there. FIG. 6 is a time chart showing the operation of each part of this drive circuit. Hereinafter, the configuration and operation of the conventional drive circuit will be described with reference to FIGS.

To this drive circuit, gradation data signals (DA0 to A3, DB0 to B3, DC0 to C3) represented by digital signals for each of the three primary colors (RGB) are externally supplied as a video input signal. The 4-bit gradation data signal is temporarily held in the data register 20 and the latch 30 at a predetermined timing according to the drive signal of the shift register 10. Then, the latch 30 outputs the 4-bit gradation data signal held according to the timing of the data latch pulse input from the outside to the comparator 40.

A gradation clock generation circuit (not shown)
Outputs a gradation clock composed of a pulse train having a constant pulse interval to the 4-bit counter 50, converts the number of gradation steps indicated by each pulse into 4-bit data, and then outputs the gradation data to the comparator 40.
Output to.

The comparator 40 compares the 4-bit gradation data signal supplied from the latch 30 with the 4-bit gradation clock data supplied from the 4-bit counter 50,
When the two coincide with each other, an H level signal is output to the level shifter sample / hold circuit 60.

The level shifter sample / hold circuit 60 is also supplied with a gradation level input voltage synchronized with the gradation clock. As shown in FIG. 6, the gradation level input voltage has a step-like voltage waveform having a predetermined voltage value corresponding to each of 16 gradations. When the output signal is received from the comparator 40, sampling pulses (SP0 to 15) corresponding to the signal are generated, and the gradation level input voltage is sampled and supplied to each pixel electrode during a period corresponding to the pulse. Analog voltage (output 0 to 1)
5) is generated. In the time chart shown in FIG.
For example, when the comparator 40 determines that the count value “2” of the grayscale clock matches the input grayscale data signal, the sampling pulse SP2 is generated, and the output voltage (output 2) is generated according to the sampling pulse SP2. To generate.

As described above, the conventional driving circuit of the liquid crystal display device uses the stepwise gradation level input voltage having a voltage level corresponding to each of the 16 gradations, and uses the input gradation data signal and the gradation. The step-like gradation level input voltage is sampled at a timing determined by coincidence with the clock and output to the pixel electrode.

[0008]

However, in the above configuration, when performing luminance modulation such as γ correction, the value of the step voltage corresponding to each gradation step number of the step-like gradation level input voltage is set. It is necessary to set the values so as to correspond to the values to be corrected and output them to the level shifter sample / hold circuit 60. Further, when performing color correction, it is necessary to generate a gradation level input voltage having an individual step shape for each of RGB. Therefore, in order to meet these requirements, a gradation level input voltage generation circuit capable of arbitrarily adjusting the voltage value of each step is required, and such a circuit has a problem that its configuration becomes complicated. .

Therefore, it is an object of the present invention to provide a drive circuit for a display device in which the gradation level input voltage generating circuit can be simplified and the gradation level voltage can be easily modulated.

[0010]

A drive circuit of a display device according to the present invention samples a gradation level voltage corresponding to video input data and outputs it to a pixel, and the voltage level is linear with time. Gradation level input voltage generating means for generating a changing gradation level input voltage for each pixel,
An output means is provided for sampling a gradation level voltage corresponding to the gradation level indicating the video input data from the gradation level input voltage generated by the gradation level input voltage generating means and outputting the sampled voltage to the pixel.

In the drive circuit of the display device according to the limited aspect of the present invention, the output means outputs a grayscale clock having a pulse train corresponding to each grayscale level and having a pulse interval arbitrarily set with respect to time. The grayscale clock generation circuit that generates the grayscale level in synchronization with the input voltage matches the grayscale level indicated by the video input data and the grayscale level indicated by each pulse of the grayscale clock generated by the grayscale clock generation means. A comparator for determining whether or not there is a sampling circuit and a sampling circuit for sampling a gradation level voltage corresponding to the matched gradation level when the comparator determines that the matching is found.

In the drive circuit of the display device having the more limited structure of the present invention, the sampling circuit performs sampling of the gradation level voltage during the period when the comparator determines the coincidence, and then at the end of the sampling. It holds the voltage level of.

In the drive circuit of the display device according to the more limited structure of the present invention, the sampling circuit starts sampling of the gradation level voltage in synchronization with the generation of the gradation clock, and the comparator determines that there is a match. Sampling is ended at the timing of the falling edge of a predetermined pulse of the adjustment clock, and the voltage level at the end of sampling is held.

Further, in the drive circuit of the display device having the more limited structure of the present invention, the grayscale clock generation circuit has three types of grayscale clocks each having different clock waveforms corresponding to digital image input data of three primary colors. Is generated.

[0015]

In the drive circuit of the display device according to the present invention, the gradation level voltage generating means generates the gradation level input voltage whose voltage level changes linearly with time. In the specific example, the gradation level input voltage includes a voltage level that linearly increases with time and a voltage level that linearly decreases with time. Further, the output means samples the gradation level voltage corresponding to the gradation level indicating the video input data from the gradation level input voltage and outputs it to the pixel.

In a more limited configuration of this output means, the grayscale clock generation circuit generates a grayscale clock having a pulse train in which the pulse interval of the pulses corresponding to each grayscale level is set to a predetermined value. Further, the comparator determines whether or not the gradation level indicated by the image input data and the gradation level indicated by a predetermined pulse of the gradation clock generated by the gradation clock generation circuit match. The sampling circuit samples the grayscale level voltage corresponding to the matched grayscale level when the comparator determines that the grayscale levels match. That is, for a gradation level input voltage having a voltage level that changes linearly with time, the pulse interval of each pulse corresponding to each gradation level is set non-linearly so that the sampling timing of the gradation level voltage is It is possible to sample gray level voltages that are set non-linearly with respect to time so that each gray level has a different voltage increment. As a result, a gradation level voltage that is non-linear with the gradation level can be applied to each pixel.

[0017]

1 is a block diagram showing the configuration of a drive circuit of an active matrix type color liquid crystal display device according to an embodiment of the present invention. As shown in FIG. 1, the drive circuit is
Shift register 10, data register 20, latch 30, 4-bit comparator 40, 4-bit counter 50
A level shifter sample / hold circuit 60, a gradation clock generation circuit 70 and a gradation level signal generation circuit 8
It has 0 and. The drive circuit receives a digitized 4-bit gradation data signal as video input data.

The shift register 10 includes three primary colors (R, G,
The 4-bit gradation data signal input for each B) is sampled from the gradation data signal line to the data register 20 according to a predetermined scanning method, and is temporarily held in the latch 30.

The latch 30 outputs the held 4-bit gradation data to the 4-bit comparator 40 according to the input timing of the data latch pulse. The gradation clock generation circuit 70 receives the basic clock as an input and has gradation clock pulses CKR, CK having a predetermined pulse interval for each RGB.
G and CKB are generated and output to the 4-bit counter 50 respectively. An example of the grayscale clock pulse is shown in FIG. In FIG. 3, the pulse intervals of the pulse trains of the gradation clock pulses CKR, CKG, and CKB are set to different time widths. This is because, as will be described later, a non-linear voltage value is extracted corresponding to each number of stages of 16 gradations.

The 4-bit counter 50 has a gradation clock pulse CKR output from the gradation clock generating circuit 70,
By dividing the frequencies of CKG and CKB, they are converted into 4-bit binary grayscale data and output to the 4-bit comparator 40.

The 4-bit comparator 40 includes latches 30-4.
A bit input gradation data signal is received, 4-bit gradation data for each RGB is received from the 4-bit counter 50, the values of both are compared, and when both match, the level shifter sample / hold circuit 60 is set to H level. Output level signal.

As shown in FIG. 2, the gradation level signal generation circuit 80 generates a gradation level input voltage having a linear voltage level that monotonically increases within a predetermined time (scanning time per pixel). , To the level shifter sample / hold circuit 60.

Level shifter sample / hold circuit 6
0 receives a gradation level input voltage having a linear voltage change from the gradation level signal generation circuit 80 and turns on the gate while the H-level output signal is input from the 4-bit comparator 40 Level Input voltage is sampled. Then, the signal is output to the pixel electrode through the signal line Si at a predetermined timing.

The operation of each part of the drive circuit when brightness adjustment is required will be described with reference to the time chart shown in FIG. For example, in brightness adjustment such as γ correction, there is no linear relationship between the gradation level indicated by the data of the input gradation data signal and the gradation level voltage to be actually applied to the pixel electrode, and the correction value is added. The relationship is nonlinear. Therefore, the operation of generating a gradation voltage having a non-linear correspondence with the gradation level indicated by the input gradation data signal using the gradation level input voltage having a linear voltage level waveform is performed as follows. .

As shown in FIG. 2, the gradation level input voltage has a voltage waveform whose voltage value linearly increases with time. Further, the gradation clock generated from the gradation clock generation circuit 70 shows a predetermined number of stages where the falling position of each pulse is 16 gradations. Therefore, the position where the dotted line extending upward from each falling portion of the gradation clock and the solid line indicating the gradation level input voltage intersect represents the gradation level voltage value at each stage of 16 gradations. As can be seen from the above relationship, the voltage value of the gradation level input voltage is defined by the falling position of each pulse of the gradation clock. Therefore, the value of the gradation level voltage corresponding to each gradation can be set arbitrarily by adjusting the falling position of each pulse of the gradation clock.

At the timing when the number of gradation steps indicated by the input gradation data signal and the number of gradation clock count values match, the comparator 40 corresponds to the gradation clock count value at this time. It is determined that the level voltage value corresponds to the input gradation data signal.

Then, the sample / hold circuit 60 is
While the two match, the gate is turned on to sample the gradation level voltage, and when the two do not match, the gate is turned off and the sampled voltage is held. Sampling pulse SP0 during this sampling / holding
~ SP15 and sample / hold output (output 0 to 15)
The relationship with is as shown in FIG.

Further, a more specific description will be given with reference to FIG. For example, it is assumed that the gradation level indicated by the 4-bit data of the input gradation data signals DR0 to DR3 is "2". In this case, the gradation clock generation circuit 70 outputs the gradation clock pulse CKR as shown in FIG. 3, for example, to the 4-bit counter 50, converts the number of pulses into 4-bit data, and outputs it to the comparator 40.

The comparator 40 is provided with 4-bit data ("001" indicating the gradation level "2" supplied from the latch 30.
0 ") and 4-bit data indicating the number of pulses given from the 4-bit counter 50, and the 4-bit counter 5
4-bit data (“001
0 ") is output, the sample / hold circuit 60
The output signal of H level is output to. Upon receiving this output signal, the sample / hold circuit 60 generates the sampling pulse SP2 shown in FIG. 2, turns on the gate, and samples the gradation level voltage from the gradation level input voltage. Then, when the gate is turned off by the fall of the sampling pulse SP2, the sampled gradation level voltage is held.

After that, the held gradation level voltage is applied to the pixel electrode via each data line Si at a predetermined timing. Next, the operation of the drive circuit according to another embodiment of the present invention will be described. FIG. 4 shows a time chart of each part of the drive circuit corresponding to FIG. In this example, the sampling pulses SP0 to SP15 for sampling the gradation level voltage rise in synchronization with the start point of the gradation clock and fall in response to detection of the end of sampling by the comparator 40. It has a waveform. Therefore, the sample / hold circuit 60 samples the gradation level voltage during a period corresponding to the H level portion of the sampling pulses SP0 to SP15, and holds the voltage after the period ends.

In the embodiments shown in FIGS. 2 and 4, the gradation level input voltage has a linear voltage change that rises to the right with the passage of time, but it is indicated by a dotted line in FIG. A gradation level input voltage having a linear voltage change that decreases downward to the right may be used. Further, in a liquid crystal display device in which the pixel electrodes are AC-driven, the two are alternately used. As described above, the driving circuit according to the embodiment of the present invention has a sawtooth-like voltage distribution in which the grayscale level input voltage monotonously increases and decreases, and therefore, the grayscale level input voltage is grayscale compared with the conventional circuit using 16 grayscale step voltages. It becomes easy to simplify or standardize the circuit configuration of the level input voltage generating circuit. Further, it becomes easy to form an IC.

Further, in the case of performing the brightness modulation such as γ correction, the brightness modulation can be easily performed by changing the waveform of the gradation clock pulse. Also, when performing color correction, without changing the gradation level input voltage,
This can be easily performed by generating and supplying three types of gradation clock pulses for RGB.

Further, by changing the gradation clock pulse, it is possible to give different gradation voltages to the upper and lower parts of the screen (each gate line), for example.

[0034]

As described above, the drive circuit of the display device according to the present invention uses the gradation level input voltage whose voltage level changes linearly with time, based on the gradation level, for each gradation at a predetermined timing. Since the voltage can be sampled, the structure of the gradation level voltage generating circuit can be simplified, and the luminance adjustment such as γ correction and the color correction can be easily performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a drive circuit of a display device according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining an example of the operation of the drive circuit shown in FIG.

FIG. 3 is a clock waveform diagram showing an example of a gradation clock.

FIG. 4 is a timing chart for explaining another example of the operation of the drive circuit shown in FIG.

FIG. 5 is a block diagram showing a configuration of a drive circuit of a conventional display device.

FIG. 6 is a timing chart for explaining the operation of a conventional drive circuit.

[Explanation of symbols]

10 ... shift register 20 ... Data register 30 ... Latch 40 ... Comparator 50 ... 4-bit counter 60 ... Level shifter sample / hold circuit 70 ... Gradation clock generation circuit 80 ... Gradation level signal generation circuit

Front page continuation (58) Fields surveyed (Int.Cl. ⁷ , DB name) G02F 1/133 520 G02F 1/133 550 G09G 3/36

Claims (4)

(57) [Claims] 1. A drive circuit of a display device for sampling a gradation level voltage corresponding to video input data and outputting the same to a pixel, wherein the gradation level input voltage whose voltage level linearly changes with time is applied to the pixel. A gradation level input voltage generating means for generating each gradation level, and a gradation level voltage corresponding to the gradation level indicated by the video input data from the gradation level input voltage generated by the gradation level input voltage generating means. Output means for sampling and outputting to the pixel, the output means
Corresponds to each gradation level, and pairs to the pulse interval time
The grayscale clock with the pulse train set arbitrarily.
A grayscale clock generated in synchronization with the grayscale level input voltage
Clock generation circuit, the gradation level indicated by the video input data, and the gradation clock.
Each pulse of the gradation clock generated by the clock generation circuit is shown.
And a comparator that determines whether or not there is a match with the gradation level, and if a match is determined by the comparator, a match is found.
The gradation level voltage corresponding to the gradation level is set to the gradation level
Equipped with a sampling circuit that samples from the input voltage
A drive circuit of a display device characterized by the above. 2. The sampling circuit holds the voltage level at the end of sampling after sampling the gradation level voltage during a period in which the comparator determines a match. The drive circuit of the display device according to claim 1 . 3. The sampling circuit starts sampling of the grayscale level voltage in synchronization with generation of the grayscale clock, and a predetermined pulse of the grayscale clock falls when the comparator determines coincidence. 2. The drive circuit for a display device according to claim 1 , wherein the voltage level at the end of the sampling is held at the same time as the sampling is ended corresponding to the timing. 4. The display according to claim 1 , wherein the grayscale clock generation circuit generates three types of grayscale clocks each having different clock waveforms corresponding to digital image input data of three primary colors. Device drive circuit.