JPS63220228A - LCD drive method - Google Patents

Abstract

PURPOSE:To eliminate the influence of spike generated in a common electrode at the time of non-selection and to prevent a trailing phenomenon by changing the non-selection voltage value is supplied to the common electrode of a liquid crystal display panel, by a minute quantity in accordance with display data at every modulation period of gradation control. CONSTITUTION:A non-selection voltage control circuit 11 corrects common-side non-selection voltages V1 and V4 to voltages V1' and V4' in accordance with segment data, and a non-selection voltage control circuit 11A corrects a common-side non-selection voltage VM to a voltage VM' in accordance with segment data. Since common-side non-selection voltage V1', V4', and VM' corrected in accordance with segment data are used, the influence of spike is eliminated from a common-side non-selection waveform. In this case, spike is not cancelled but the voltage level is raised by the spike component to correct this spike with respect to effective value.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a liquid crystal driving method for displaying gradations in a multiplex method on a liquid crystal display panel.

[Prior art and its problems] Conventionally, a liquid crystal drive circuit for driving a liquid crystal display panel in, for example, a liquid crystal television is generally configured as shown in FIG. 8 or 9. FIG. 8 shows an example of the circuit configuration when both the common signal and the segment signal are 4W1, and FIG. 9 shows an example of the circuit configuration when the common signal is 3-valued and the segment signal is 2-valued.

In FIG. 8, 1 is a display control circuit, segment side drive circuit 2. Segment side analog multiplexer 3.
Common side drive circuit 4. The common side analog multiplexer 5 is controlled. Further, 6 is an LCD drive voltage generation circuit, which generates an LCD drive voltage from a predetermined power supply voltage 1 [VO, V
l, V2. V3゜V4, V5 are generated, VO, V2
, V3, and V5 are supplied to the segment-side analog multiplexer 3, and voltages of VO, Vl, V4, and V5 are supplied to the common-side analog multiplexer 5. Then, the segment side drive circuit 2 sequentially reads the digital display data of multiple bits, for example, 3 pits, sent from the display control circuit 1, and after reading the data for one line, generates a gradation signal according to the data. is created and output to analog multiplexer 3.

This analog multiplexer 3 outputs VO, V2, or V3 according to the gradation signal from the segment side drive circuit 2.
．． The voltage V5 is selected and the segment electrodes of the LCD panel (n-crystal display panel) 1 are driven for display. On the other hand, the common side drive circuit 4 reads the common signal given from the display system circuit 1, for example, every field period, shifts it sequentially, generates a common drive timing signal, and outputs a common drive timing signal to the common side analog multiplexer 5. Output to. This analog
The multiplexer 5 outputs VO and Vl according to the common drive timing signal from the common side drive circuit 4.

The voltages V4 and V5 are selected and the common electrodes of the LCD panel 7 are sequentially driven.

In the above configuration, segment signal waveforms and common signal waveforms are shown in FIG. 10 (△) when using a field inversion method in which the drive signal is inverted and controlled for each field.
Figure 10 (B) shows segment signals and common signals when using the 1-common inversion method in which the drive signal is inverted υ1Ill for each common.On the other hand, the liquid crystal drive circuit shown in Figure 9 R
Raw circuit 6 k: J: V+, V-, VH, VM.

generate a driving voltage of Vt, and send the voltages of V-)- and V- to the segment measurement analog multiplexer 3;
The voltages H, VM, and VL are supplied to the common-side analog multiplexer 5, and the other configuration is the same as that of the circuit shown in FIG.

Figure 10 (G) shows the segment signal waveform and common signal waveform when using the field inversion method that inverts the drive signal for each field, and Figure 10 (D) shows the inversion control of the drive signal for each common. The segment signal and common signal waveforms are shown when using the 1-common inversion method.

Therefore, if the LCD panel 7 is driven with ideal signal waveforms as shown in FIGS. 10(A) to 10(D), a good display image can be obtained. but.

The LCD panel 7 has input resistors RC and R3 on the common side and segment side, respectively, as shown in FIG. 11.
is formed, and each common 1! ! A capacitor C is formed between the pole and the segment electrode. In particular, due to the input resistance RC on the common side and the capacitor C between the N pole, the signal waveform when the common electrode is not selected is changed to The sound becomes distorted as shown in Figures (A) to (D). These FIGS. 12(A) to (D) are the same as those shown in FIGS. 10(A) to (D) above.
Corresponding to D), only the non-select voltage is shown. That is, the segment signal (A>,
In case of (B) 4; [V5 → V3J or “VO → v2
”, and in the case of (C) and (D), “V+ → V−J or [V− → V+J”, and the potential is constantly changing. Therefore, the high frequency component When not selected, it is output as a spike to the common Nl1i side through the common signal. Figure 12 (A) shows a one-field inverted common signal waveform, and the selection voltage is omitted. Figure 12 (B)
) is the common signal waveform when 1 common is inverted, and the 7th floor X11 (
This is an example of display data (3 bits per pixel), and one common period is divided into seven. As shown in FIG. 13, the seven gradation signal waveforms are set to values whose time widths are sequentially determined from roolJ to rllllJ. Therefore, the 13th
As shown by ■ to ■ in the figure, there is a possibility that six edges occur in one common period, and this corresponds to the spikes shown by ■ to ■ in FIG. 12. In one common period, each segment electrode is driven at gradations from ■ to ■, and the size of the spike is determined depending on which gradation is more frequent.

In the example in Figure 12 (B), the spike at the position ■ is large;
It can be seen that the segment electrodes driven at the gray level (010) are the most common.

For the reasons mentioned above, spikes occur at the common electrode during non-selection, and as a result, the effective voltage actually applied to the liquid crystal differs from the effective voltage of the accurate non-selection voltage, resulting in a trailing phenomenon.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and it is possible to eliminate the influence of spikes occurring on the common electric floor, prevent the occurrence of trailing phenomenon, and display a good image on a liquid crystal display panel. The purpose of the present invention is to provide a liquid crystal driving method that achieves the desired results.

[Summary of the Invention] The present invention eliminates the influence of spikes by correcting the non-selection voltage value supplied to the common electrode of the liquid crystal display panel in accordance with display data for each common power scanning period. It is.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In Figure 1, both the common signal and segment signal are 411iI.
This is an example of a liquid crystal drive circuit in the case of , and corresponds to the conventional circuit shown in FIG. The embodiment shown in FIG.
A common side non-selection voltage Mi11 circuit 11 is connected between the D drive vJN pressure generation circuit 6 and the common side analog multiplexer 5.
The other circuit configuration is similar to that shown in FIG. 8. The LCD drive voltage generation circuit 6 is as follows:
The voltages VO to 5 are supplied to the non-selected voltage control circuit 11, and the selected voltages VO and V5 are directly supplied to the common-side analog multiplexer 5. Further, the display control circuit 1 supplies display data and the υJllll signal to the non-selection voltage control circuit 11. The non-selection voltage control circuit 11 sets the LCD driving voltage Vl according to display data and control signals from the display control circuit 1.

Correct V4 and convert it to Vl', V4', analog
Supplied to multiplexer 5.

In addition, in FIG. 2, the common signal is 3111. This is an example of a liquid crystal drive circuit when the segment signal is 24'a, and corresponds to the conventional circuit shown in FIG. In the embodiment shown in FIG. 2, a common side non-selection voltage control circuit 11A is provided between the LCD drive voltage generation circuit 6A and the common side analog multiplexer 5, and the other parts are as shown in FIG. It has the same configuration as the circuit. The LCD driver 1jJ voltage generation circuit 6A supplies the voltages VM, V+, and V- to the non-selection voltage control circuit 11A, and also supplies the voltages VH and VL directly to the common-side analog multiplexer 5.

Furthermore, display data and control signals are supplied from the display control circuit 1 to the non-selection voltage vJ I11 circuit 11A. The non-selected voltage control circuit 11A corrects the t-CD drive voltage Vv according to the display data and control signal from the display control circuit 1, converts it into V Ml, and supplies it to the analog multiplexer 5.

Therefore, the non-selected voltage control circuit 11 shown in FIG. 3 (A
) As shown in (B), the common side non-selection voltage Vl, V4
■1' according to the segment data.

The voltage is corrected to V4', and the non-selection voltage 11+1[
1 circuit 11A corrects the common III IF-selection voltage VM to the voltage VM' in accordance with the segment data, as shown in FIGS. 3(C) and 3(D). Common non-selection voltage VI changed according to segment data as above
By using ', V4', and VM', the unselected waveform on the common side becomes a waveform as shown in FIGS. 4(A) to (D), and the influence of spikes is removed. In this case, instead of canceling out the spikes, the voltage level is increased by that amount to compensate for the spikes in terms of effective values.

Next, details of the non-selection voltage control circuit 11.11A will be explained with reference to FIG. In the figure, 21 is a decoder, into which n-bit display data D1 to Qn sent from the display Ill I11 circuit 1 and chip enable GE are input. The decoder 21 classifies the data sent from the display control circuit 1. For example, in the case of 3-bit data D1 to D3, it is classified into 61 data r001J to r110J, and a counter 22a provided for each data is used.
- Count up 22f. The count outputs of the counters 22a to 22f are the latch circuits 23a to 23f.
Sent to 23f. These latch circuits 23a to 23f are
The counters 22a-
The count outputs of 22f are each latched and output to the data selector 24. At this time, the timing signal IN
The counters 22a to 22f are reset. In addition, the data selector 24 also has a display control circuit 1 to 1
eili signal creation pulse 1C and timing signal M? ,
is given. The data selector 24 sequentially reads out the data latched in the latch circuits 23a to 23f in synchronization with the gradation signal generation pulse IC.
Output to analog multiplexer 25. The analog multiplexer 25 is also supplied with various voltages obtained by dividing the voltage from the LCD drive voltage generation circuit 6.6A using a resistor divider circuit 26. The analog multiplexer 25 selects the various voltages divided by the resistor divider circuit 26 according to the voltage applied from the data selector 24, and selects the voltages V1', V1' and V1' through the buffer 1 circuit 27.
Output as 4'.

The above analog multiplexer 25, resistor divider circuit 26
, the buffer 7 circuit 21 will be further explained in detail with reference to FIGS. 6 and 7. FIG. 6 shows a circuit configuration when used in the non-select voltage control circuit 11 in FIG. 1, and FIG. 7 shows the non-select voltage control circuit 11A in FIG.
This figure shows the circuit configuration when used in

First, the circuit configuration when used in the non-selection voltage control circuit 11 will be explained with reference to FIG. Resistance divider circuit 26
The first. It consists of second divided circuits 26a and 26b. The first dividing circuit 26a has 2n resistors r connected in series, and voltages V5 and V3 from the LCD drive voltage generation circuit 6 are supplied to both ends of the resistors r through respective resistors R.
Voltage ■4 is supplied to the midpoint. In this case, the resistor R is set to a larger value than the resistor r, and the voltage rV4± changes slightly from the dividing point of each resistor r around the voltage v4.
nΔVJ can be obtained. The second dividing circuit 26b has 2n resistors r connected in series, and the voltage VO from the LCD driving vJ voltage generation circuit 6 is applied to both ends of the resistor r.
V2 is supplied via a resistor R, and a voltage v1 is supplied to the midpoint. From this second dividing circuit 26b, a voltage r that slightly changes around the voltage vl from the dividing point of each resistor r
V1±nΔV" can be obtained. and,
The voltage divided by the resistive divider circuit 26 is sent to the analog multiplexer 25. This analog multiplexer 25 includes first and second multiplexers 2
5a and 25b, and the first multiplexer 25a receives the voltage rV separated by the first dividing circuit 26a.
4±nΔV” is given, and the second multiplexer 25b
is the voltage divided by the second dividing circuit 26b [
v1±nΔVJ is given.

The first multiplexer 25a is connected to the data selector 2
According to the data given from 4, the first dividing circuit 26a
The divided voltage is selected and outputted as voltage V4' via the buffer circuit 27a. Further, the second multiplexer 25b selects the divided voltage of the second dividing circuit 26t) according to the data given from the data selector 24, and outputs it as a voltage Vl' via the buffer circuit 27b.

Next, as shown in FIG. 7, the analog multiplexer 25° resistor divider circuit 26 when used in the non-select voltage control circuit 11A. The circuit configuration of the buffer circuit 27 will be explained. The resistance divider circuit 26 is made up of n resistors r connected in series, and the LCD drive initial voltages V- and V+ from the LCr drive voltage generation circuit 6A are supplied to both ends of the resistor r through the resistors R, respectively. Voltage VM is supplied to the midpoint. This resistor divider circuit 26 extracts a voltage [VM1nΔVJ] which slightly changes with the VM lightning voltage at the center from the dividing point of each resistor r, and sends it to the analog multiplexer 25. The analog multiplexer 25 selects the voltage rVM+nΔVJ divided by the resistance divider circuit 26 according to the data from the data selector 24, and outputs it as VM' via the buffer circuit 27.

Next, the non-selection voltage control circuit 11 configured as described above.
The operation of 11A will be explained. In FIG. 5, a decoder 21 is supplied with, for example, 3-bit digital display data D1 to D3 from the display control circuit 1. The decoder 21 operates according to the chip enable signal CE given from the display control circuit 1, and the decoder 21 operates according to the chip enable signal CE given from the display control circuit 1, and outputs the display data D1 to D3.
are classified into data 1 to data 6, and the counters 22a to 22
Count up f. That is, the decoder 21
For example, display data D1 to D3 is data 1 (001)
If so, the content of the counter 22a is r+1JL, and if the data is 2 (002), the content of the counter 22b is "+1".
do. As described above, during 1H, the display data D1 to D3 sent from the display control circuit 1 are classified, and the number thereof is counted by the counters 22a to 22f. Then, when the classification and counting operation for 1N worth of data is completed, a display 111 [timing signal I from 1 circuit 1]
N is given, the count values of the counters 22a to 22f are latched by the latch circuits 23a to 23f, and then reset. The data latched in the latch circuits 23a to 23f are sequentially read out by the data selector 24 in synchronization with the gradation signal generation pulse 7C, and sent to the analog multiplexer 25 whose details are shown in FIGS. 6 and 7. .

In the circuit shown in FIG. 6, multiplexer 25a is selected based on data from data selector 24.

25b operates, selects the voltage rVd±nΔV divided by the first dividing circuit 26a and the voltage rVI±nΔV divided by the second dividing circuit 26b, and outputs V4' through the buffer circuits 27a and 27b. , output as Vl'. In this case, the counter 22a in FIG.
If the LCD panel 7 has, for example, 160 segment electrodes, the count value of ~22f is at most 1.
It is possible to count up to 60. Therefore, it would be ideal if 160 voltages were prepared in the first dividing circuit 26a and the second dividing circuit 26b constituting the resistance dividing circuit 26, but the circuit configuration would become very complicated and most There are a large number of unused voltage values. Therefore, in the first dividing circuit 26a and the second dividing circuit 26b, when the counters 22a to 22f each have an 8-bit configuration,
I decided to look at the top 3 bits, rooOJ~rl
Divide into 5 ways oOJ. That is, in the first division circuit 26a in FIG. 6, rV4±ΔVJ, rV4
+2ΔVJ, rV4 +3ΔV−J.

Create 5 voltages of rV4±4ΔVJ and rV4±5ΔVJ. Similarly, in the second division circuit 26b, “V
1±ΔVJ, rV1±2ΔVJ.

rVl +3ΔVJ, rVl +4ΔVJ, rV1
Create five types of voltages of '+5Δ■'. Then, the five voltages respectively created by the first dividing circuit 26a and the second dividing circuit 26b are transferred to the multiplexer 25a.

25b selects according to the data from the data selector 24, and outputs V4 via the buffer circuits 27a and 27b.
', Vl'. As a result, the voltage v4' is output from the buffer 1 circuit 27a, 2N).

Vl' changes depending on the display data as shown in FIGS. 3(A) and (F3) above. Then, the voltage V4 output from the buffer circuits 27a and 27b is
', Vl' are sent to the common side analog multiplexer 5 in FIG. This analog multiplexer 5 receives the voltages Vl', V4' and +-CO supplied from the non-selection voltage ml It1 circuit 1.
The voltages VO and V5 supplied from the drive voltage generation circuit 6 are selected according to the output signal of the common side drive circuit 4, and the common electrode of the LCD panel 1 is driven. As a result, the voltage level of the non-selection signal waveform of the common electrode corresponding to the spike increases as shown in FIGS. 4(A) and (8), and is corrected in terms of effective value.

On the other hand, the analog multiplexer 25. shown in FIG.
Also in the resistance divider circuit 2G and the buffer 1 circuit 27, the sixth
The same processing as in the circuit shown in the figure is performed, and
), the voltage VM changes according to the displayed data.
' is created. This voltage VM' is then sent to the common-side analog multiplexer 5 in FIG. 2, as shown in FIG. 4(A).

As shown in (B), the spike portion in the non-selection signal waveform of the common electrode is corrected in terms of effective value.

[Effects of the Invention] As detailed above, according to the present invention, the non-selection voltage value supplied to the common electrode of the liquid crystal display panel is slightly changed in accordance with the display data for each modulation period for controlling the gradation. Therefore, the influence of spikes occurring on the common electrode when not selected can be eliminated, and the trailing phenomenon can be reliably prevented.

[Brief explanation of the drawing]

1 to 7 show embodiments of the present invention. FIG. 1 is a block diagram showing the circuit configuration when both the common signal and the segment signal are 411, and FIG. 2 is a block diagram showing the circuit configuration when the common signal is 31i1 and the segment signal is 411. A block diagram showing the circuit configuration when the signal is 21 shifts, Figures 3 and 4 are common signal waveform diagrams to explain the non-selection voltage correction operation for the common electrode, and Figure 5 is a diagram showing the circuit configuration when the signal is 21 times. Figure 3 is a block diagram showing details of the non-select voltage control circuit, Figures 6 and 7 are circuit diagrams showing details of the main parts of Figure 5, and Figure 8 is a common signal and segment in the conventional liquid crystal drive system. A block diagram showing the circuit configuration when both signals are 41i11, FIG. 9 is a block diagram showing the circuit configuration when the common signal is 31a and the segment signal is binary in the conventional liquid crystal drive system, and FIG. 11 is a diagram showing an equivalent circuit of a liquid crystal display panel, and FIG. 12 is a diagram showing an ideal liquid crystal drive signal waveform in the liquid crystal driving method shown in FIG. 8 and FIG. 9. FIG. 13 is a diagram showing a gradation signal waveform when display data is 3 bits. DESCRIPTION OF SYMBOLS 1... Display control circuit, 2... Segment side drive circuit, 3... Segment side analog multiplexer, 4
・・・Common side drive circuit, 5...Common side analog・
Multiplexer, 6,6A...LCD drive voltage generation circuit, 7...LCD panel, 11. IIA...Non-selection voltage control circuit, 21...Decoder, 22a to 22f
...Counter, 23a-23f...Latch circuit, 2
4...Data selector, 25...Analog multiplexer, 26...W1 division circuit, 27...Buffer circuit. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 9 Figure 11 Figure 0O Figure 13

Claims (1)

[Claims] A liquid crystal display panel including a plurality of common electrodes and segment electrodes arranged in a matrix, a segment electrode driving means for driving the segment electrodes of the liquid crystal display panel according to display data, and a common electrode of the liquid crystal display panel that sequentially drives the segment electrodes of the liquid crystal display panel in accordance with display data. It is characterized by comprising a common electrode drive means for selectively driving, and a non-selection voltage control means for correcting the common electrode non-selection voltage supplied to the common electrode drive means in accordance with the display data for each common electrode scanning period. LCD drive system.