JPH05265402A - Method and device for driving liquid crystal display device - Google Patents

Abstract

(57) [Abstract] [Purpose] It is possible to obtain a liquid crystal display of good display quality in which uneven display brightness does not occur in a simple matrix liquid crystal display device. A liquid crystal cell at an intersection of a scanning electrode (Y electrode) and a data electrode (X electrode) is applied with a voltage having a potential difference between a scanning voltage from a Y driving circuit and a display voltage from an X driving circuit,
In a method of driving a liquid crystal display device for performing display according to display data, a correction period for correcting the display voltage output from the X drive circuit is provided at least once for each line scanning period, and within the correction period, Instead of the display voltage, the X drive circuit outputs a correction voltage having a voltage level intermediate between the ON display voltage level and the OFF display voltage level. [Effect] It is possible to reduce the variation in the effective value of the applied voltage of the liquid crystal cell depending on the display pattern, and it is possible to eliminate the unevenness in the display brightness caused by this variation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device having at least a substrate having scan electrodes and a substrate having signal electrodes and a dielectric liquid crystal or a dielectric material sandwiched between the substrates, and more particularly, a matrix type liquid crystal display device. The present invention relates to a driving method and a device for a liquid crystal display device that can reduce unevenness in display brightness and obtain a high-quality display.

[0002]

2. Description of the Related Art In a conventional liquid crystal display device, a voltage is applied to the liquid crystal by a time division driving method, and the configuration and operation thereof are disclosed in, for example, Japanese Patent Application Laid-Open No. 2-250030. Such a conventional liquid crystal display device is shown in FIGS.
This will be described with reference to FIG. 73.

FIG. 71 is a block diagram showing a conventional liquid crystal display device. In FIG. 71, the matrix type liquid crystal display panel 1 (hereinafter referred to as the liquid crystal panel 1) performs display by changing the state of the liquid crystal in each display dot due to the difference in the output potentials of the X driver 2 and the Y driver 3. The X driver 2 responds to display data and control signals,
The Y driver 3 responds to the control signal by the power supply circuit 1
The output power supply voltage from 57 is switched and output to the liquid crystal panel 1.

FIG. 72 shows an internal configuration diagram of a conventional liquid crystal display device, particularly a power supply circuit. Output voltage V of power supply circuit 157
1, V6, V3, V4, V5 and V2 are V1>V6> V
It has a relationship of 3>V4>V5> V2. V1, V3, V4, V2 to the X driver 2, V1 to the Y driver 3,
V6, V5 and V2 are supplied. Now, the output of the X driver 2 (X1 to Xm) and the output of the Y driver 3 (Y1 to Ym)
FIG. 73 shows a conventional liquid crystal applied voltage waveform when the output Y2 of the Y driver 3 is selected (scanned) by n). In the figure, one line (horizontal line) is alternately turned on and the display is turned off on the entire liquid crystal display screen.

In the conventional liquid crystal display device, generally, as shown in the figure, the ideal liquid crystal driving voltage waveform is distorted in the liquid crystal applied voltage waveform due to the impedance of the circuit such as liquid crystal and wiring. That is, the amount of distortion of the liquid crystal applied voltage waveform changes at ON / OFF or OFF / ON of the display data or at the change point of the alternating signal M. The greater the dullness of the waveform,
The effective value of the applied voltage decreases. Therefore, the degree of decrease in the effective value is large for the data electrode having a large number of ON / OFF times, and the degree of decrease in the effective value is small for the data electrode having a small number of ON / OFF times. As a result, display brightness unevenness (shadowing) occurs depending on the display pattern.

Further, the display data and the AC signal are changed to X by the change point of the voltage waveform of the output (X1 to Xm) of the X driver 2.
On the output (Y1 to Yn) wirings of the Y driver 3 which are orthogonal to the output (X1 to Xm) wirings of the driver 2, a voltage fluctuation due to electric induction occurs due to the electric capacitance property of the liquid crystal layer, and the liquid crystal applied voltage waveform The amount of strain changes, and the effective value of the liquid crystal applied voltage changes.

As described above, the amount of distortion of the liquid crystal applied voltage waveform, that is, the effective value of the liquid crystal applied voltage changes depending on the display pattern, which causes a difference in display brightness on the liquid crystal on the display screen, resulting in uneven display brightness.

On the other hand, a method for reducing display luminance unevenness depending on a display pattern in a liquid crystal display device having a simple matrix type liquid crystal display panel is disclosed in, for example, Japanese Patent Application Laid-Open No. 2-6921. .. In this conventional technique, a Y electrode is provided in a liquid crystal cell at an intersection of a scanning electrode (hereinafter, referred to as Y electrode) and a data electrode (hereinafter, referred to as X electrode).
In a liquid crystal display drive system in which a voltage difference between the scan voltage from the drive circuit and the data voltage from the X drive circuit is applied to perform display, the voltage applied to the liquid crystal cell ( A period in which the voltage of the difference) is 0 V is provided so that the display according to the display data is performed. Hereinafter, this method will be described in more detail with reference to the drawings.

FIG. 65 shows a block diagram of a conventional liquid crystal display device. In the figure, 1 is a liquid crystal panel, and 2 is a column-side drive X typified by Hitachi HD66107T.
The drive circuit 3 is represented by Hitachi HD66107T,
A row-side driving Y drive circuit 4 is a mono-multivibrator. Further, reference numeral 5 is display data, which is 4-dot or 8-dot parallel data in the example in which Hitachi HD66107T is used as the X drive circuit, but it will be described as serial data for convenience of explanation. 6 is a data latch clock, 7 is a line clock, 8 is an alternating signal, 9 is a head line clock, 10 is an enable signal,
11 to 16 are liquid crystal driving power supply voltages. The serial display data 5 for one scanning electrode and the data latch clock 6 for one scanning electrode are added to the X drive circuit 2 to shift-in the display data 5, and the display data 5 for one scanning electrode 5 is input. Is accumulated, the line clock 7 is applied to the X drive circuit 2, and the accumulated display data 5 is loaded on the output side of the X drive circuit 2.

Then, depending on the combination of the loaded display data 5 and the alternating signal 8, the data electrodes 4
Level liquid crystal drive power supply voltage V1 voltage 11, V3 voltage 1
One of the three levels of voltage is selected from among 3, V4 voltage 14, and V2 voltage 16. In this way, the X drive voltage for one scan electrode is applied in parallel to the X electrodes Vx1 to Vxi.

On the other hand, in the Y drive circuit 3, the head line clock 9 is fetched in accordance with the line clock 7, the head line is first selected, and then the selected line is sequentially moved according to the line clock 7. In accordance with the combination of the scanning signal for selecting the sequential line and the alternating signal 8, the four-level liquid crystal drive power supply voltage V1 voltage 11, V6 voltage 12, V5
One of the voltages of the voltage 15 and the V2 voltage 16 is selected and applied to the selected line of the Y electrodes Vy1 to Vyj.

The mono-multivibrator 4 is triggered by the line clock 7 and applies the enable signal 10 for a period shorter than one line scanning period to the X drive circuit 2 and the Y drive circuit 3. In response to this, X drive circuit 2 and Y
The drive circuit 3 outputs 0V when the enable signal 10 from the mono multivibrator 4 is "0", and outputs a voltage of the selected level when the enable signal 10 is "1".

67 and 68 show the X drive circuit 2 and the X drive circuit 2, respectively.
FIG. 6 is a diagram showing an operation of the Y drive circuit 3. FIG. 67 shows the X drive circuit 2 according to the alternating signal, the enable signal and the display data.
Shows the state of the output voltage Vx that is output by operation, and FIG. 68 shows the state of the output voltage Vy that is output by operation of the Y drive circuit 3 according to the AC signal, the enable signal, and the scanning signal.

It should be noted that 6-level liquid crystal drive voltages (V1 to V
6) is the external supply voltage V0 voltage 17 as shown in FIG.
Is divided by resistances R1 to R5.
This voltage dividing resistance is P395 of the liquid crystal device handbook (published by Nikkan Kogyo Shimbun, September 29, 1989, first edition, 1st edition).
When driven by the time division driving method described in (1), there is a relationship of R1 = R2 = R4 = R5 = R R3 = (a-4) R. However, a is a bias ratio.

These six-level liquid crystal drive voltages have a relationship of V1> V6> V3> V4> V5> V2 V1-V6 = V6-V3 = V4-V5 = V5-V2.

Next, taking the display pattern of FIG. 69 as an example,
The voltage applied to the liquid crystal cell will be described with reference to FIG.

In the display pattern shown in FIG. 69, X
The liquid crystal cells at the intersections of the electrode Vx1 and the Y electrodes Vy1 to Vy4 are all ON display cells indicated by black circles (including the liquid crystal cell A). Further, the liquid crystal cell at the intersection of the X electrode Vx2 and the Y electrodes Vy1 to Vy4 is a pattern in which ON display cells (including the liquid crystal cell B) indicated by black circles and OFF display cells indicated by white circles are alternately arranged.

When this display pattern is driven by a frame AC alternating signal 8 for inverting the polarity for each frame, the voltages applied to the liquid crystal cells A and B are as shown in FIG. That is, since the liquid crystal cell A is a cell located between the Y electrode Vy1 and the X electrode Vx1, the voltage VA applied to this cell is the potential difference (Vy1-Vx1) between the Vy1 applied voltage and the Vx1 applied voltage. Become. Similarly, since the liquid crystal cell B is a cell located between the Y electrode Vy1 and the X electrode Vx2, the voltage VB applied to this cell is Vy.
1 applied voltage and Vx2 applied voltage potential difference (Vy1-Vx
2).

As can be seen from FIG. 70, the enable signal 10 is applied to the X and Y electrode applied voltages according to the enable signal 10.
By providing the period of 0V, the period of 0V is also formed in the applied voltages VA and VB of the liquid crystal cells A and B.

According to this method, the number of times the applied voltages VA and VB fall from the indicated voltage to 0V and rise from 0V to the indicated voltage is the same regardless of the display pattern. Therefore, variations in the effective value of the voltage applied to the liquid crystal cell depending on the display pattern are reduced.

[0021]

However, when the voltage output from the X drive circuit 2 and the Y drive circuit 3 is set to 0V based on the enable signal, the voltage level is large or small, and the liquid crystal panel is turned off. / ON change and O
Due to the difference in N / OFF change characteristics (transient characteristics, etc.), there is still a difference in waveform blunting for each X electrode depending on the display pattern. For example, when the V2 voltage is changed to 0 V, there is almost no waveform dullness (generally, the V2 voltage is 0 V),
When the highest level V1 voltage is changed to 0V, the waveform becomes dull. Due to the difference in the waveform dullness, the effective value of the applied voltage still slightly varied depending on the liquid crystal display pattern.

Further, a large change in the applied voltage causes so-called crosstalk, which also hinders the improvement of display quality in the liquid crystal display. For example, when the driving force of the Y drive circuit is low, there is a problem that the output change of the X drive circuit distorts the output of the Y drive circuit through the liquid crystal. This problem will be briefly described below.

In FIG. 14, the output V _X of the X drive circuit 2 is a
An example is shown in which all are rising at point, all are falling at point b, and there are the same number of rising and falling at point c. At each such point, the output operation of the X drive circuit 2 distorts the output of the Y drive circuit 3 through the liquid crystal in the upward direction at the point a and in the downward direction at the point b. On the other hand, almost no distortion occurs at point c. That is, depending on the display state for one scan of all X electrodes (the difference between the number of rising edges and the number of falling edges of the output of the X drive circuit 2 during the correction period), Y
The distortion of the output of the drive circuit 3 is different. This also caused uneven display brightness.

It is an object of the present invention to provide a driving method and device of a liquid crystal display device in which variations in effective value of liquid crystal applied voltage depending on a display pattern are further reduced to improve display quality.

[0025]

A method of driving a liquid crystal display device according to the present invention comprises a scan electrode (Y electrode) and a data electrode (X electrode).
Driving a liquid crystal display device in which a voltage according to the potential difference between the scanning voltage from the Y drive circuit and the display voltage from the X drive circuit is applied to the liquid crystal cell at the intersection with the electrode) to display according to the display data. In the method, a correction period for correcting the display voltage output from the X drive circuit is provided at least once every one line scanning period, and within the correction period, the X drive circuit replaces the display voltage with the ON display voltage. Level and OF
A correction voltage having an intermediate voltage level to the voltage level during F display is output.

According to another driving method of the liquid crystal display device of the present invention, the scanning voltage from the Y driving circuit and the driving voltage from the X driving circuit are applied to the liquid crystal cell at the intersection of the scanning electrode (Y electrode) and the data electrode (X electrode). In a method of driving a liquid crystal display device which applies a voltage having a potential difference from a display voltage to display according to display data, a display voltage output from the X drive circuit is corrected at least once in each screen scanning period. And a correction voltage to be applied to the data electrode is determined in accordance with the content of the display data given to each data electrode within one screen scanning period. In addition, the correction voltage is output from the X drive circuit to each data electrode instead of the display voltage.

Further, in the liquid crystal display driving device according to the present invention, a voltage is applied to the liquid crystal cell at the intersection of the scanning electrode (Y electrode) and the data electrode (X electrode) to perform display according to the display data. In a driving device for a liquid crystal display device, a scan voltage is applied by sequentially selecting one of the scan electrodes for each predetermined one-line scan period, and another scan not selected at that time is applied. Scan electrode driving means for applying a non-scanning voltage to the electrodes, data electrode driving means for applying a display voltage corresponding to the content of display data input from the outside to the data electrodes, and each of the scan electrode driving means. Each time the scanning electrodes are selected, the ON display voltage level and the OFF display voltage level are replaced by the display voltage output from the X drive circuit only for a preset correction period. It is obtained by a voltage control means for applying a voltage level of the correction voltage between all of the data electrodes.

In another liquid crystal display driving device according to the present invention, a voltage is applied to the liquid crystal cell at the intersection of the scan electrode (Y electrode) and the data electrode (X electrode) to perform display according to the display data. In a driving device for a liquid crystal display device, a frame memory that stores display data for one screen and one of the scan electrodes are sequentially selected and a scan voltage is applied for each predetermined one-line scan period. In addition, a scan electrode driving unit that applies a non-scan voltage to the other scan electrodes that are not selected at that time, and applies a non-scan voltage to all the scan electrodes during the correction period provided after the one screen scan,
Data electrode driving means for applying a display voltage corresponding to the content of the display data input from the frame memory to the data electrodes, and the content of the display data given to each data electrode within one screen scanning period Calculating means for calculating the magnitude or application time width of the correction voltage to be applied to the data electrode during the correction period, and a voltage for outputting the correction voltage instead of the display voltage to each data electrode during the correction period And a control means.

[0029]

The operation of the typical structure of the present invention will be described below.

In order to make the number of changes of the voltage applied to the X electrodes within one screen scanning period constant regardless of the contents of the display data,
A correction period is provided at least once for each line scanning period. Further, in the present invention, in order to reduce the difference in the dullness of the voltage waveform of the voltage applied to each electrode depending on the content of the display data, the ON display voltage is replaced with the display voltage from the X drive circuit during the correction period. Since the correction voltage of a voltage level intermediate between the level and the voltage level during OFF display is output, it is possible to further reduce the variation in the effective value of the liquid crystal applied voltage.

The voltage applied to the liquid crystal cell is the voltage difference between the Y electrode applied voltage and the X electrode applied voltage. In order to make the liquid crystal cell applied voltage 0 V during the correction period, the Y electrode applied voltage and the X electrode applied voltage are set. The applied voltages may be equal. In one aspect of the present invention, the control of the Y electrode applied voltage during the correction period is eliminated, and the X electrode applied voltage is set to the same level as the Y electrode applied voltage during the correction period. Therefore, the voltage value of the X electrode applied voltage that fluctuates during the correction period becomes constant irrespective of the voltage level according to the display data, and the difference in the waveform blunt of the X electrode applied voltage depending on the display data during the correction period decreases.
It is also possible to reduce variations in the effective value of the voltage applied to the liquid crystal cell.

From a different point of view, in order to reduce the variation in the effective value depending on the display pattern of the voltage applied to the liquid crystal cell, the display pattern is ON-displayed and OF is displayed.
The number of times the applied voltage fluctuates as the F display is switched may be constant regardless of the display pattern. From this, it is considered that the voltage applied to the liquid crystal cell in the correction period for each one-line scanning period does not need to be 0 V in particular, and it may be set to the correction voltage such that the effective value of the applied voltage does not vary. Therefore, in another aspect of the present invention, other than the method of setting the voltage level switched in the correction period in the voltage selector to the same level as the Y electrode applied voltage, the Y electrode applied voltage level is set so that the applied voltage effective value does not vary. The voltage should be close.

Further, the liquid crystal cell has electrostatic capacity and is turned on.
The voltage effective value in the non-scanning period may slightly vary between the display and the OFF display due to the difference in the transient characteristics. In order to reduce this variation, it is possible to change the correction voltage value during ON display and during OFF display.

When the driving capability of the Y drive circuit is low,
To solve the problem that the output change of the X drive circuit during the correction period distorts the output of the Y drive circuit through the liquid crystal, the difference between the ON display pixel number and the OFF display pixel number of the display data for one line scanning causes Y Since the voltage distortion of the drive circuit is different, this ON
It is possible to correct the distortion of the output of the Y drive circuit by counting the number of displays and the number of OFF displays and controlling the correction period width based on the difference. Further, a device having a relatively large number of display lines of 400, 480, and 780 is a liquid crystal display device having a screen divided into two parts.
It is possible to correct the distortion of the drive circuit output.

That is, in general, the Y drive circuit of the liquid crystal display device having the upper and lower two-screen structure can be roughly classified into two types. One is a method of simultaneously scanning the upper and lower screens of a liquid crystal panel with two upper and lower screens by one Y drive circuit.
The number of display dots scanned by one Y drive circuit in one line scanning period is twice as many as that in one screen. The other is up and down 2
This is a system in which the liquid crystal panel of the screen is scanned by dedicated Y drive circuits for the upper screen and the lower screen, respectively, and the number of display dots scanned by one Y drive circuit during one line scanning period is the same as that for one screen. The present invention is, in contrast to the former, two in one screen.
The number of ON display and the number of OFF display of double display data (upper screen display data + lower screen display data) are counted, the correction period is controlled by the difference between the count values, and the output distortion of one Y drive circuit is corrected. I did it. For the latter, the same as in the case of one screen, the ON display number and the OFF display number of each display data are counted on the upper screen and the lower screen, and the correction period is controlled by the difference between the count values. screen,
The output distortion of the Y drive circuit on each lower screen is corrected.

By making the waveform of the correction voltage triangular, it is possible to reduce the influence of the voltage change at the X electrode on the Y electrode voltage.

[0037]

First, a first embodiment of the present invention will be described.

FIG. 1 shows the configuration of a liquid crystal display device according to the first embodiment of the present invention. In the figure, 1-3, 5-9, 1
1 to 16 are the same as those described with reference to FIG. Reference numeral 18 is a counter, which is reset by the line clock 7 and counts the data latch clock 6 by a predetermined number to generate a correction clock 19 for a period shorter than one scanning period. The correction clock 19 is a signal similar to the enable signal 10 described in the related art. However, unlike the case of the conventional enable signal 10, the correction clock 19 is supplied only to the voltage selector 20 described below, and X
It is not supplied to the drive circuit 2 and the Y drive circuit 3. The voltage selector 20 controls the X drive circuit 2 according to the correction clock 19.
Select the power supply voltage to be applied to. 21 to 24 are power supply voltages Vs given to the X drive circuit 2 from the voltage selector 20.
1, Vs3, Vs4, and Vs2.

FIG. 2A shows an internal configuration example of the counter 18. The counter 18 compares two 4-bit counter ICs forming an 8-bit counter, a switch group SW for setting a target count value, a target count value and a current count value, and generates a correction clock 19 when they match. And a group of gates. The correction clock 19 is shown in FIG.
As shown in, the data latch clock 6 rises in synchronization with the fall of the line clock 7 and reaches the target count value.
Falls after counting. The low period of the correction clock 19 is the correction period in which the correction pulse is generated. Although the switch group SW is manually set in this embodiment, an embodiment in which a signal equivalent to the output of the switch group SW is automatically generated will be described later.

FIG. 3 is a block diagram showing the structure of the voltage selector 20. The voltage selector 20 includes four selector elements 25 to 2 that perform a selection operation according to the correction clock 19.
It consists of eight. As shown in the operation description of FIG. 4, when the correction clock 19 is “1”, the selector elements 25 to 28 respectively cause the V1 voltage 11, the V3 voltage 13, and the V4 voltage 1 respectively.
4, V2 voltage 16 is selected, Vs1 voltage 21 and Vs3
It is output as a voltage 22, a Vs4 voltage 23, and a Vs2 voltage 24. Further, when the correction clock 19 is "0", the V6 voltage 12 is changed to the Vs1 voltage 2 by the selectors 25 and 26.
1, Vs3 voltage 22 is output, and V5 voltage 15 is output from selectors 27 and 28 as Vs4 voltage 23 and Vs2.
The voltage 24 is output.

In the X drive circuit 2, as shown in FIG. 5, when the alternating signal 8 is "0", the display data (pixel) 5 is ON.
If so, the Vs2 voltage 24 is selectively output, and the display data 5
Is OFF, the Vs4 voltage 23 is selectively output. Further, when the alternating signal 8 is "1", the Vs1 voltage 21 is selectively output if the display data 5 is ON, and the Vs3 voltage 22 is selectively output if the display data 5 is OFF. In addition, Vs2 voltage 24, Vs4 voltage 23, Vs1 voltage 2
1, and each of the Vs3 voltage 22 is as described in FIG.
One voltage value is selected from the two voltage values according to the correction clock 19.

On the other hand, in the Y drive circuit 3, as shown in FIG. 6, when the alternating signal 8 is "0" and the scanning signal is "scan", the V1 voltage 11 is selectively output and the scanning signal is " In the case of "non-scan", the V5 voltage 15 is selectively output. When the alternating signal 8 is "1", the V2 voltage 16 is selectively output if the scanning signal is "scan", and the V6 voltage 12 is selectively output if the scanning signal is "non-scan".

The operation of the liquid crystal display device shown in FIG. 1 will be described.

In the X drive circuit 2, serial display data 5 for one scanning electrode is sent to a data latch clock 6 for one scanning electrode.
Shift input according to. When the display data 5 for one scanning electrode is accumulated, the line clock 7 is applied to the X drive circuit 2, and the shift-input display data 5 is loaded on the output side of the X drive circuit 2. As described with reference to FIG. 5, the combination of the loaded display data 5 and the alternating signal 8 causes the four-level liquid crystal drive power supply voltage Vs1 voltage 21, Vs3 voltage 22, Vs4 supplied from the voltage selector 20.
One level voltage is selected from the voltage 23 and the Vs2 voltage 24, and the X drive voltage for one scan electrode (i in the figure) is applied in parallel to the X electrodes Vx1 to Vxi.

On the other hand, the Y drive circuit 3 takes in the head line clock 9 by the line clock 7 and selectively scans the head line. Then, according to the line clock 7, the line to be sequentially scanned is moved. As described with reference to FIG. 6, the combination of the line scanning signal and the alternating signal 8 causes the liquid crystal drive power source voltage V1 of the four levels, the voltage V6 of the voltage 12, the voltage V5 of the voltage 15, and the voltage V2 of the one level to be the voltage of one level. Is selected and applied to the Y electrodes Vy1 to Vyj. The 6-level liquid crystal drive voltage is the same as in the conventional technique. This voltage dividing resistor has a relationship of R1 = R2 = R4 = R5 = R R3 = (a-4) R as described above with reference to FIG. However, a is a bias ratio, and these 6 levels of liquid crystal drive voltages have a relationship of V1>V6>V3>V4>V5> V2, V1-V6 = V6-V3 = V4-V5 = V5-V2. ..

Next, an example of the voltage applied to the liquid crystal cell will be described with reference to FIG. 7 using the display pattern of FIG. Figure 7
Shows the waveform of the voltage applied to the liquid crystal cell when the liquid crystal display pattern shown in FIG. 69 is displayed. The display pattern shown in FIG. 69 is an ON display cell in which all liquid crystal cells at the intersections of the X electrode Vx1 and the Y electrodes Vy1 to Vy4 are black circles (including the liquid crystal cell A), and the X electrode Vx2 and the Y electrodes Vy1 to Vy4. The liquid crystal cell at the intersection of and is a pattern in which ON display cells (including the liquid crystal cell B) indicated by black circles and OFF display cells indicated by white circles are alternately arranged. When this display pattern is driven by a frame AC alternating signal 8 for reversing the polarity for each frame, the voltages applied to the liquid crystal cells A and B are as shown in FIG. That is, the liquid crystal cell A has the Y electrode Vy1 and
Since the cell is located between the X electrode Vx1, the voltage VA applied to the cell is the voltage difference (Vy1-Vx1) between the Vy1 applied voltage and the Vx1 applied voltage, and the liquid crystal cell B is the Y electrode Vy1. And the X electrode Vx2, the voltage VB applied to the cell is Vy1.
Voltage difference between applied voltage and Vx2 applied voltage (Vy1-Vx2)
Becomes

By providing the voltage selector 20, the X electrode applied voltage becomes the same level as the Y electrode applied voltage during non-scanning during the correction period in which the correction clock 19 is "0". That is, when the AC signal 8 is “0” and the display data 5 is ON, the V2 voltage (p in FIG. 7) is selected, but during the correction period, this V2 voltage is the V5 voltage (q).
Can be switched to. V4 when display data 5 is OFF
The voltage (r) is selected, but this V
The 4th voltage is switched to the V5 voltage (s). Since the voltage applied to the Y electrode when the Y electrode is not scanned is V5 voltage (t), the voltage applied to the liquid crystal cell (difference voltage) during the correction period.
Is 0 V (u). At the time of scanning the Y electrode, when the display data 5 is ON, the applied voltage to the liquid crystal cell is V1-V2 = V
1 (w), but V1−V5 = V6 during the correction period
(X). Although not shown in FIG. 7, when the display data 5 is OFF, the applied voltage to the liquid crystal cell changes from V1−V4 = V3 to V1−V5 = V6 during the correction period.

Therefore, the applied voltage to the liquid crystal cell during the correction period during scanning does not become 0V, but becomes the ON display voltage (V1 when the alternating signal 8 is "0", -V1 when "1"). O
FF display voltage (V3 when AC signal 8 is "0", "1"
When the AC signal 8 is "0", it is V6, and when it is "1", it is -V6. Therefore, the voltage fluctuation values of the X electrode applied voltage and the Y electrode applied voltage are smaller than those in the conventional technique. In the conventional technology, the maximum voltage V1 to the voltage V2 (0
However, in the present embodiment, a slight voltage fluctuation (difference between the V1 voltage and the V6 voltage) is caused by the fluctuation. Further, in this embodiment, the voltage variation of the Y electrode applied voltage during the correction period disappeared. The correction voltage widths of the four power supply voltages output from the voltage selector 20 all have the same value (the same voltage fluctuation value that changes from the V1 voltage to the V6 voltage).

As a result, the voltage value range in which the X electrode applied voltage fluctuates during the correction period becomes constant regardless of the voltage level selectively output according to the display data. As a result, the difference in the dullness of the liquid crystal applied voltage waveform during the correction period is reduced regardless of the display pattern. As a result, there is less variation in the effective value of the voltage applied to the liquid crystal cell,
It is possible to improve the display quality.

The X drive circuit 2 shown in FIG. 1 is a Hitachi LCD driver LSI data book manufactured by Hitachi, Ltd.
It can be realized in the form shown in "Fig. 8 Application circuit example" described on page 286 of the "edition". However, although the display data is described as serial in FIG. 1 for convenience of explanation, it is 8 bits in the “application circuit example of FIG. 8”. Further, the Y drive circuit 3 can be similarly realized in the form shown in "Example of application circuit of FIG. 8". Also, the counter 18 is a 74 series T like the circuit shown in FIG.
Can be realized with TL. Furthermore, the circuit of FIG. 2 may be used as a gate array. Although not shown in this embodiment, it is also possible to combine it with the circuit for generating the alternating signal 8 shown in FIG. 1 and put it in the same gate array.

From a different viewpoint, in order to reduce the variation in the effective value depending on the display pattern of the voltage applied to the liquid crystal cell, the number of times the applied voltage fluctuates due to display / non-display switching of the display pattern is changed. It may be fixed regardless of the display pattern.

Therefore, it is not always necessary to set the differential voltage applied to the liquid crystal cell to 0 V in the correction period for each scanning period, and it is conceivable to set the correction voltage so that the effective value of the applied voltage does not vary. .. Therefore, in the second embodiment, the voltage level switched in the correction period in the voltage selector is not set to the same level as the Y electrode applied voltage, but a voltage close to the Y electrode applied voltage level such that the applied voltage effective value does not vary. And

The second embodiment of the present invention will be described below with reference to FIGS.

FIG. 8 shows the structure of the liquid crystal display device of the second embodiment of the present invention, and FIG. 9 shows the voltage dividing circuit for generating the liquid crystal power supply voltage and the correction voltage in this embodiment.

As shown in FIG. 9, the 6-level liquid crystal drive voltages 11 to 16 are the same as those in the conventional technique and the first embodiment, and V1>V6>V3>V4>V5> V2, V1-V6. = V6-V3 = V4-V5 = V5-V2.

Further, the correction voltages 31 to 34 are generated by the voltage dividing resistor R
It is generated by setting the internal resistances of 1, R2, R4, and R5 to r1 = r2 = r4 = r5, and the voltage satisfies the following conditions.

V1> V10, V3 <V30, V4> V40, V2 <V
20 V1-V10 = V30-V3 = V4-V40 = V20-
V2 = ΔV The block diagram shown in FIG. 8 is the same as FIG. 1 except how to apply the correction voltage to the voltage selector 20.

The voltage selector 20 is composed of four selector elements 25 to 28 which perform a selecting operation according to the correction clock 19 as shown in FIG. 10. From each selector 25 to 28, as shown in the operation explanation of FIG. Correction clock 19
Is "1", V1 voltage 11, V3 voltage 13, V4 voltage 14, V2 voltage 16 are Vs1 voltage 21, Vs3, respectively.
It is output as a voltage 22, a Vs4 voltage 23, and a Vs2 voltage 24. When the correction clock 19 is “0”, the correction voltages V10 voltage 31, V30 voltage 32, V40 voltage 33, and V20 voltage 34 are Vs1 voltage 21, Vs, respectively.
3 voltage 22, Vs4 voltage 23, and Vs2 voltage 24 are output.

As shown in FIG. 12, the X drive circuit 2 is supplied from the voltage selector 20 according to the combination of the display data 5 loaded on the output side and the AC signal 8.
The liquid crystal driving power supply voltage Vs1 voltage 21, the Vs3 voltage 22, the Vs4 voltage 23, and the Vs2 voltage 24 of the level are selected to select one level voltage, and i scan driving voltages for one scanning electrode are arranged in parallel. It is applied to Vx1 to Vxi. That is, when the alternating signal 8 is "0", if the display data 5 is ON, the Vs2 voltage (V2 voltage in the non-correction period, V20 voltage in the correction period) is selectively output, and if the display data 5 is OFF. The Vs4 voltage (V4 voltage during the non-correction period and V20 voltage during the correction period) is selectively output. Further, when the alternating signal 8 is "1", if the display data 5 is ON, the Vs1 voltage (V1 voltage in the non-correction period, V10 voltage in the correction period) is selectively output, and if the display data 5 is OFF. The Vs3 voltage (V3 voltage during the non-correction period and V30 voltage during the correction period) is selectively output.

Next, using the display pattern of FIG. 69, the second
The liquid crystal applied voltage according to this embodiment will be described with reference to FIG. The display pattern shown in FIG. 69 is as described above. FIG. 13 shows the difference voltages VA and VB applied to the liquid crystal cells A and B when this display pattern is displayed. The applied voltage always fluctuates once during one scanning period, and the number of fluctuations is VA and VB. It will be the same number. In addition, the amount of fluctuation when it fluctuates (correction amount ΔV)
Is the same, and the effective value of the applied voltage is also the same value.

The first embodiment is equivalent to the case where the correction amount ΔV in the second embodiment is V5-V2 (= V5).

Further, the liquid crystal cell has electrostatic capacity and is turned on.
The voltage effective value in the non-scanning period may slightly vary between the display and the OFF display due to the difference in the transient characteristics. In the above-described embodiment, ideally, when ON is displayed and when OFF
It was thought that there was no difference in transient characteristics between the display and the value of ΔV was set to the same value during ON display and OFF display. However, the variation in effective voltage value during ON display and OFF display during the above non-scanning period. It is also possible to change the value of ΔV between the ON display and the OFF display in order to reduce the value. That is, in the case of ON display, the voltage V1 voltage 11 (or V2 voltage 16) applied to the X electrode during the non-correction period and the voltage V10 voltage 31 (or V20) applied to the X electrode during the correction period.
The difference ΔV with the voltage 34) is ΔVon, and in the case of OFF display, the voltage V3 applied to the X electrode during the non-correction period, and the voltage 1
3 (or V4 voltage 14) and the difference between the voltage V30 applied to the X electrode during the correction period V30 voltage 32 (or V40 voltage 33) is ΔVoff, ΔVon and ΔVo
Give ff a slight difference. This can be realized by setting the internal resistances r1, r2, r4, r5 of the voltage dividing circuit shown in FIG. 9 as follows.

R1 = r5 = Ron, r2 = r4 = Roff Further, in order to correct the variation in the effective voltage value in the non-scanning period between the ON display and the OFF display, these Ron and Ro are corrected.
A method of finely adjusting the semi-fixed resistance by adjusting the value of ff to the display states of ON display and OFF display is also conceivable. In the case of a liquid crystal display panel that is normally OFF display, Ro
By setting n <Roff, ΔVon <ΔVo
It is possible to optimize the display when the OFF display is used as the background.

By the method described above, it is possible to reduce the variation of the effective value of the applied voltage of the liquid crystal cell depending on the display pattern, and it is possible to improve the display quality.

Next, a third embodiment will be described with reference to FIGS.

In this embodiment, when the drive capability of the Y drive circuit 3 is low, the output change point of the X drive circuit 2 during the correction period as shown in FIG. This is to solve the problem of distorting the output. The output of the correction period of the X drive circuit 2 is determined to be a rising edge or a falling edge depending on whether it is an ON display or an OFF display. The degree of distortion of the output of the Y drive circuit 3 varies depending on the number of rising edges and the number of falling edges of the output 2).

FIG. 15 is a block diagram of a liquid crystal display device for preventing the distortion of the output of the Y drive circuit. In the figure, 50 is a correction clock generation circuit that controls the time width of the correction clocks 35 and 36 that are separately provided for ON display and OFF display, and 37 is an ON display of the power supply voltage applied to the X drive circuit 2. 2 is a voltage selector for selecting an applied voltage to the X drive circuit 2 in accordance with the correction clock 35 for OFF and the correction clock 36 for OFF display. The other components are the same as those in the first embodiment (FIG. 1).

FIG. 16 shows an example of the configuration of the correction clock generation circuit 50. Reference numeral 51 is an O that counts the number of ON displays by fetching the display data 5 with the data latch clock 6.
An N display counter 53 receives the display data 5 with the data latch clock 6 and counts the number of OFF displays.
It is an FF display counter. 55 is OF from 52 ON number
It is a difference circuit for subtracting the F number 54. 57 is a difference circuit 55
This is a difference latch that latches the display difference 56 output from the line clock 7 with the line clock 7. Reference numeral 59 is an ON display decoder circuit, which decodes the difference data 58 and outputs an ON display correction clock position 60 which indicates the falling position of the ON display correction clock 35. Reference numeral 61 denotes an ON display horizontal counter, which sets the ON display correction clock 35 to "1" by the line clock 7 and then counts the data latch clock 6 so that the count value matches the value of the ON display correction clock position 60. Then, the correction clock 35 is set to "0". Similarly, 79 is an OFF display decoder circuit, which decodes the difference data 58 and indicates the falling position of the OFF display correction clock 36.
The corrected clock position for display 80 is output. 81 is OF
It is a horizontal counter for F display and is OF by line clock 7.
The F display correction clock 36 is set to "1", the data latch clock 6 is counted thereafter, and when the count value matches the value of the OFF display correction clock position 80, the correction clock 36 is set to "0".

FIG. 17 is a block diagram of an example of the ON display counter 51. This counter 51 displays the O of the display data 5.
ON decoder 62 for decoding N number, ON display number 63
And an ON latch 66 for latching an addition ON number 65. ON adder 64 is display ON
The number 63 and the number 52 of ON are added. The addition ON number 65 of the addition result is latched by the ON latch 66 at the data latch clock 6. The ON latch 66 is "0" at the line clock 7.
Since the display ON number is sequentially latched by the data latch clock 6 and the result is given to the ON adder 64, when the data latch clock 7 for one scan is output, all the ON signals within one line scan period are output. It will latch the display number. The OFF display counter 53 is also shown in FIG.
This can be realized by the same configuration as the ON display counter 51 of 7 (however, the operation of the decoder of FIG. 18 is made to decode the number of “0”).

The difference circuit 55 has an ON number 52 to an OFF number 54
Is subtracted and the result is output as the display difference 56.

FIG. 18 is a table showing the operation of the ON decoder 62 constituting the ON display counter 51. It is assumed that the display data 5 is 4-bit parallel, and the display during one line scanning period is 640 dots. ON of display data 5
The number of bits indicating the display is output as the decode output 63.

FIG. 19 shows the decoder circuit 5 shown in FIG.
9 is a table showing the operation of 9, which is "number of ON-OFF.
Decode value 60 for ON display and OF for each "number" range
The F display decode value 80 is predetermined. In this example, one line scanning period includes 159 data latch clocks, and the time width of the correction clock is given by a value obtained by subtracting the decode value 20 (or 30) from "159". For example, when the "ON number-OFF number" is in the range of "640 to 321", the ON display decode value 60 is "139", and the time width of the correction clock is "20".

FIG. 20 is a timing chart showing the operation of the horizontal counter 61, and shows an example corresponding to the range of "-11 to -320" in FIG. That is, the ON display correction clock 30 rises in synchronization with the pulse of the line clock 7, and the count value of the data latch clock 6 is “12”.
It falls at the time when it becomes 4 ". The period from this time to the pulse of the next line clock 7 is the correction clock 3
It is a time width of 5. The OFF display correction clock 36 is turned ON except that the falling time is the time when the count value of the data latch clock 6 becomes “129”.
It is similar to the display correction clock 35.

By the operation of the correction clock generation circuit 50 described above, the correction clock is divided into the ON display 35 and the OFF display 36, and the period of "0" in each is displayed as the number of ON display and OFF display in one line scanning period. Since the control can be performed according to the difference in the number, the output distortion of the Y drive circuit 3 due to the output of the X drive circuit 2 in the correction period can be corrected, and the display without unevenness in display brightness can be performed.

In this embodiment, the difference between the ON display number and the OFF display number is simply calculated. However, the present invention is not limited to this, and the ON display number and the OFF display number may be weighted respectively. .. Further, the circuit configuration in the embodiment is not limited to the circuit described here, and the correction clocks 35 and 36
Any circuit can be used as long as it can control the width of "0".

In the voltage selector 20, the voltage of the correction period is set to the same level as the output voltage of the Y drive circuit 3, but the voltage is not limited to this and can be set to a value close to the voltage value. Further, it is possible to set different voltage levels for ON display and OFF display.

FIG. 21 shows another example of the correction clock generation circuit 50 of FIG. The same elements as those shown in FIG. 16 are designated by the same reference numerals. Reference numeral 64-1 is an adder that adds the number of ONs 52 and outputs the total number 65-1 of ONs. Reference numeral 57-1 is a latch that latches the total number of ON indications 65-1 by the line clock 7. 57-2
Is the output, and shows the total data of ON display. The operation of the correction clock generation circuit 50 is the same as that of the circuit in FIG. 16 except that the OFF display counter is not used and the correction clock is generated based on the total number of ON displays by the ON display counter.

A circuit when the correction clock generation circuit 50 of FIG. 21 is configured by 74 series TTL is shown in FIGS.
It shows in FIG.

FIG. 22 is a circuit diagram when the ON display counter 51 is configured by the 74 series TTL, and shows the configuration when the input display data is 4-bit parallel.

FIG. 23 shows the O output of the ON display counter 51.
Adder 64-1 that adds N number 52 to 74 series T
It is a circuit diagram when it comprises by TL.

In FIG. 24, the latch 57-1 is a 74374, the ON display decoder circuit 59 (or the OFF display decoder circuit 79) is a ROM HD 27128, and the ON display horizontal counter 61 (or the OFF display horizontal counter 81). ) 74161, 7404, 748
6, 7420, and 7402 show the circuits respectively configured. The output of 7402 becomes the correction clock 35 or 36. In FIG. 24, the decoder and the horizontal counter are shown only for one set for ON display, but they are omitted here because they can be configured for OFF display by the same circuit.

As shown in FIG. 25, ON shown in FIG.
Display counter 51, OFF display counter 53, difference circuit 5
ON / OFF display difference counter 55 with the same function as 5
-1 can also be used.

FIG. 26 shows another structure of the voltage selector 20. In FIG. 26, 67 to 74 are operational amplifiers, and the rest is the same as the configuration of the voltage selector 20 of FIG.
The operational amplifier circuits 67 to 70 (voltage follower circuits, respectively) are of a type having a low slew rate and cannot cope with the switching of the selectors 25 to 28, which causes a delay. As a result, the voltage change can be made into a triangular wave (see FIG. 27). In order to stabilize this output, an output voltage is applied to the X drive circuit 2 via operational amplifier circuits 71 to 74 (each a voltage follower circuit) having a higher slew rate. Since the voltage change is a triangular wave, as shown in FIG. 28, as compared with the case of the square wave, the Y of the output of the X drive circuit 2 is increased.
The influence on the output of the drive circuit 3 can be reduced. FIG. 29 shows how the liquid crystal applied voltage waveform (FIG. 7) of the first embodiment is changed by this configuration.

In the example of FIG. 26, the triangular wave is generated by using the operational amplifier having a low slew rate, but the present invention is not limited to this, and it may be generated by a time constant circuit using a resistance element and a capacitance element. Further, the voltage change during the correction period is not limited to the triangular wave, and a similar effect can be obtained with a waveform having few high frequency components, a sine wave, or the like.

The circuit configuration of the voltage selector shown in FIG. 26 can also be applied to the voltage selector 37 in the embodiment of FIG.

The liquid crystal display device described above uses the liquid crystal panel 1 having a single screen with a small display line number j as shown in FIGS.
The application of the present invention to a liquid crystal display device using a liquid crystal panel having an upper and lower two-screen configuration having a relatively large number of display lines of 80 and 780 dots will be described with reference to FIGS.

FIG. 30 is a block diagram of a conventional liquid crystal display device having an upper and lower two-screen configuration. Reference numeral 101 denotes an upper and lower two-screen liquid crystal panel, and reference numerals 102 and 103 denote upper screen and lower screen X drive circuits, respectively, which operate in the same manner as the single screen X drive circuit 2. 104 is a Y for scanning the upper and lower two screens simultaneously
It is a drive circuit. Reference numerals 113 and 114 denote upper screen display data and lower screen display data, respectively. Others are the same as in the case of using a liquid crystal panel having one screen.

For example, when the number of display lines is 400 lines (the upper and lower one screens are each 200 lines), the Y drive circuit 104 fetches the start line clock 9 by the line clock 7 and sets the start line of the upper screen (Y1). )When,
The top line (Y201) of the lower screen is simultaneously selected and scanned, and then the scanning lines of the upper screen and the lower screen are moved simultaneously in accordance with the line clock 7. With such a configuration, the upper and lower two screens can be displayed in one screen display time (one frame time). From a different point of view, the number of display dots scanned by one Y drive circuit in one scanning period is double that in the case of one screen display. That is, when the number of display dots in one line is 640, the number of display dots in one line scanning period is 1280.

In this liquid crystal display device, a method of changing the time width of the above-described correction clock according to display data (third embodiment)
3) is applied to the configuration of FIG. 3 as a fourth embodiment.
Shown in 1.

In FIG. 31, reference numeral 107 denotes a correction clock generation circuit for controlling the time width of each of the correction clocks 115 and 116 divided into ON display and OFF display according to the display state. Reference numeral 108 denotes a voltage selector that selects the power supply voltage to be applied to the upper screen X drive circuit 102 and the lower screen X drive circuit 103 by the ON display correction clock 115 and the OFF display correction clock 116. The other components are the same as those in FIG. The correction clock generation circuit 107 displays the display state in one line scanning period,
In other words, if the number of display dots on one line is 640 dots,
The number of display dots in one line scanning period is 1280 dots.
The difference between the FF display numbers is detected, and the correction clocks 115 and 116 are detected.
Is a circuit that generates.

From the voltage selector 108, the X for upper screen is displayed.
The same set of power supply voltages is applied to the drive circuit 102 and the lower screen X drive circuit 103.

Next, FIG. 32 shows another constitutional view of a conventional liquid crystal display device having an upper and lower two-screen constitution. Reference numeral 101 is a liquid crystal panel having an upper and lower two-screen configuration, and 102 and 103 are X drive circuits for upper and lower screens, respectively, and an X drive circuit 2 for one screen.
Works the same as. Reference numerals 105 and 106 denote Y drive circuits for upper screen and lower screen, respectively, which operate in the same manner as the Y drive circuit 3 for one screen. 113 and 114 are upper screen display data and lower screen display data, respectively. Others are the same as in the case of using a liquid crystal panel having one screen. For example, when the number of display lines is 400 lines (each screen has 200 lines), the upper screen Y drive circuit 105 takes in the leading line clock 9 by the line clock 7.
The leading line of the upper screen is selectively scanned, and then the scanning line is moved sequentially according to the line clock 7. On the other hand, in the lower screen Y drive circuit 106, the leading line clock 9 is fetched by the line clock 7, the leading line of the lower screen is selectively scanned, and then the scanning lines are sequentially moved according to the line clock 7. With such a configuration, the upper and lower two screens can be displayed in one screen display time (one frame time).

A configuration in which the third embodiment is applied to this liquid crystal display device is shown in FIG. 33 as a fifth embodiment.

In FIG. 33, reference numeral 109 denotes an upper screen correction clock generation circuit for controlling the time width of each of the correction clocks 117 and 118 divided into ON display and OFF display according to the display state of the upper screen. is there. Reference numeral 110 denotes an ON display correction clock 117 and an OFF display correction clock 118 for supplying a power supply voltage to the upper screen X drive circuit 102.
It is an upper screen voltage selector that is selected by. Similarly,
111 is for ON display and OF depending on the display state of the lower screen
Reference numeral 112 denotes a lower screen correction clock generation circuit for controlling the correction width of each of the correction clocks 119 and 120 divided for F display. Reference numeral 112 denotes the ON display correction clock 119 for supplying the power supply voltage to the lower screen X drive circuit 103. And a lower screen voltage selector selected by the OFF display correction clock 120. Since the Y drive circuit is configured to be independent for the upper screen and the lower screen, each correction clock generation circuit 109 and 111 is in a display state in one line scanning period, that is, when the number of display dots in one line is 640 dots. The number of dots displayed by one Y drive circuit in one line scanning period is 640 dots, and the difference between the ON display number and the OFF display number at this 640 dot is detected, and the correction clocks 117, 118 and 119, 120 are generated. ..

Therefore, since the upper screen and the lower screen are driven completely independently, the power supply voltage supplied from the upper screen voltage selector 110 to the upper screen X drive circuit 102 is the lower screen voltage selector 111. From the X drive circuit for lower screen 1
03, which is a voltage different from the power supply voltage. On the other hand, the power supply voltage applied to the upper screen Y drive circuit 105 and the lower screen Y drive circuit 106 are the same voltage.

The sixth embodiment of the present invention will be described below with reference to FIGS.
This will be described with reference to FIG.

In this embodiment, the amount of distortion of the liquid crystal applied voltage waveform is calculated from the display ON / OFF state of the display data for one horizontal display period (one line scanning period), and the correction period is set for each horizontal period. By applying a correction voltage for correcting this, unevenness in display brightness is eliminated.

FIG. 34 is a block diagram showing a liquid crystal display device of the sixth embodiment. In the figure, as in the above-described embodiment, the liquid crystal panel 1 performs display by displacing the liquid crystal state due to the difference in the output potentials of the X driver 2 and the Y driver 3.
The arithmetic circuit 135 detects the change point of the display data and the change point of the AC signal, which cause the distortion of the liquid crystal applied voltage, and calculates the distortion amount of the liquid crystal applied voltage based on the number of the change points. Based on this distortion amount, the output power supply voltage from the power supply circuit 136 is switched to the correction voltage. X driver 2
On the other hand, the Y driver 3 switches the output power supply voltage from the power supply circuit 136 according to the control signal composed of the data latch clock, the line clock, and the alternating signal and the display data, and outputs it to the liquid crystal panel 1. To do.

FIG. 35 shows a liquid crystal applied voltage waveform of the sixth embodiment. As can be seen from this figure, one line scanning period is divided into a display period and a correction period each having a predetermined length, and the arithmetic circuit 1 is further divided within the correction period.
The time width for applying the correction voltage (V complementary 2) is determined according to the output of 35. During the period other than the correction voltage application time within the correction period, V5 is applied and the liquid crystal applied voltage (VY-VX) is 0V.
So that Note that FIG. 35 shows a state when the alternating signal is low (L), and when it is high (H), V2, V
5, V4, V Supplement 2 instead of V1, V6, V respectively
3 and V complement 1.

FIG. 36 shows an internal block diagram of the arithmetic circuit 135. The arithmetic circuit 135 includes a display data change point detection circuit 137 that detects a change point of display data, an AC signal M change point detection circuit 138 that detects a change point of the AC signal M in the control signal, and these. It comprises a decoder 139 which obtains a correction amount from the output of the detection circuit.

The display data change point detection circuit 137 is shown in FIG.
Display OFF with 1 line of display data as shown in 7
Display data OFF / to detect the number of changes from ON to ON
ON change point detection circuit 140, as well as display ON to OF
The display data ON / OFF change point detection circuit 141 detects the number of changes to F. Display O with display data
The number of times it changes from FF to ON and the display ON to O
Circuits for detecting the number of changes to the FF and the number of changes to the FF are provided to increase the accuracy of correction because the amount of voltage waveform distortion when changing the display from ON to OFF of the liquid crystal applied voltage waveform is different. Is. If the accuracy of correction of the liquid crystal applied voltage waveform distortion amount may be lower than this, only one of them may be used.

Display data OFF / ON change point detection circuit 1
As shown in FIG. 38, the internal configuration of 40 includes a data shifter 142 that shifts parallel display data by the display data latch clock in the control signal to convert the data into serial display data, and a serial output from the data shifter 142. Rise with display data as clock
The counter 143 is configured to count the F / ON change.

Display data ON / OFF change point detection circuit 1
As shown in FIG. 39, the internal configuration of 41 includes a data shifter 142 and a counter 144 that counts ON / OFF changes by falling with serial display data output from the data shifter 142 as a clock. The counter 143 and the counter 144 have the line clock CL1.
It is reset by the high part ("H" or "1") of the pulse of. The count value of these counters is the decoder 1
It is output to 39.

FIG. 40 shows an alternating signal M change point detection circuit 13
8 shows an internal configuration of No. 8. The state displacement detection unit 145 inputs the alternating signal M and outputs H when it changes from H (or “1”) to L (or “0”) or from L to H. Further, it is reset by the high portion of the pulse of the line clock CL1.

FIG. 41 shows the internal structure of the decoder 139. This decoder 139 includes comparators 146 to 14
8 and switches SW0 to SW2 for generating comparison data
And a counter 149. The output of the display data OFF / ON change point detection circuit 140 and the output of the switch SW0 are input to the comparator 146, and the comparator 1
47 is a display data ON / OFF change point detection circuit 141
And the output of the switch SW1 are input. Similarly, the output of the alternating signal M change point detection circuit 138 and the output of the switch SW2 are input to the comparator 148. Each comparator compares the output of the change point detection circuit and the set value of the switch on a bit-by-bit basis, and outputs "1" for each matched bit. In the counter 149, as shown in (b) of the figure, a logical sum is calculated for each of the same-order bits of the comparators 146 to 148. The counter element CNT in the counter 149 counts the data latch clock during the correction period. This count value is compared with the result of the logical sum of the outputs of the comparators, and when they match each other, the output of the counter 149 is changed from "0" to "1". In addition, counter 1
The output of 49 is cleared to "0" by the high part of the pulse of the line clock CL1.

As a result, the arithmetic circuit 135 detects the number of change points of the display data displayed on the liquid crystal display from ON to OFF or OFF to ON, and the number of change points of the AC signal M in the control signal. Is converted into data of the correction voltage application time corresponding to the amount of distortion of the liquid crystal applied voltage waveform, and is output to the power supply circuit 136 as a correction voltage application signal counted in display data latch clock units.

FIG. 42 shows an internal configuration diagram of the power supply circuit 136. The power supply voltage dividing circuit 150 supplies the liquid crystal drive power supply VLCD with voltages V1, V6, V correction 1, V3, V4, V correction 2, and V.
5, when the output of the counter 149 is L, the selectors 151 and 152 select V correction 1 and V correction 2 as the correction voltage of the distortion amount of the liquid crystal applied voltage waveform, and when the output of the counter 149 is H. Selects V6 and V5 so that the liquid crystal applied voltage becomes 0V. Selector 153,
154, 155, and 156 are display / correction switching signals. When the display / correction switching signal L is displayed during the display period, the X driver 2 is supplied with power supply voltages V1, V3, V4, V2 for normal display.
Is selectively supplied, and the voltage selected by the selectors 151 and 152 is output when the display / correction switching signal H is supplied during the correction period. As a result, in addition to applying the voltage for normal display, a correction voltage that corrects the amount of distortion of the liquid crystal applied voltage waveform is output, and the effective voltage value of the liquid crystal applied voltage is always kept constant, realizing a liquid crystal display with no display brightness unevenness. To do.

Output voltages V1, V6, V of the power supply circuit 136
Correction 1, V3, V4, V correction 2, V5, V2 is V1>
V6>V3>V4>V5> V2, and V6 ≧ V correction 1 ≧ V4 and V3 ≧ V correction 2 ≧ V5.

The data shifter 142, the counters 143, 144, 149, and the state displacement detection unit 145 shown in FIGS. 38 to 41 are 74 series TTL 7474, and the comparators 146, 147, 148 are 74 series TTL 7486. 7400.

For reference, FIGS. 43A and 43B show two types of internal circuit diagrams of the power supply voltage dividing circuit 150.

The seventh embodiment of the present invention will be described below with reference to FIGS.
It demonstrates using FIG. In this embodiment, the liquid crystal applied voltage is not corrected every one line scanning period, but is corrected every one screen display period (frame).
That is, display ON / OFF of the display data of one frame
The amount of distortion of the liquid crystal applied voltage waveform is calculated according to the state of (1) and stored in the memory, and the correction data is read from the memory during the correction period provided for each one-screen display period, and the correction voltage is applied. This is to eliminate uneven display brightness.

FIG. 44 is a block diagram showing a liquid crystal display device of the seventh embodiment of the present invention. In the figure, as described above, the liquid crystal panel 1 includes an X driver 2 and a Y driver 3.
Display is performed by displacing the state of the liquid crystal due to the difference in the output potential of. The X driver 2 switches the output power supply voltage from the power supply circuit 157 according to the display data and a control signal including a data latch clock, a line clock, and an AC signal, and the Y driver 3 switches the liquid crystal by switching the output power supply voltage. Output to panel 1.

The frame memory 160 stores display data for one screen, and the data from the frame memory 160 is converted by the arithmetic circuit 161 into correction data for correcting the applied voltage waveform distortion amount due to the display data. It is stored in the memory 162. The frame memory 160 and the correction data memory 162 can be configured using a memory IC (for example, HM6264A) described in Hitachi IC Memory Data Book. Regarding the read cycle and the write cycle of this memory IC, the control signal conversion 163
A control signal that satisfies the access timing described in the Hitachi IC memory data book is generated. The display data for one screen is read from the frame memory 160, transferred to the X driver 2, and displayed. After that, the correction data memory 1
The correction data is read from 62 and transferred. Selector 15
Reference numeral 9 switches between the display data for one screen from the frame memory 160 and the correction data from the correction data memory 162 by a display / correction switching signal, and transfers it to the X driver 2 as display data for each line in the horizontal direction of the screen. To do.

The control signal converter 163 responds to a control signal composed of a data latch clock, a line clock, and an AC signal, to the frame memory 16.
0, the correction data memory 162, the selector 159, the X driver 2, the Y driver 3, and the control signal for controlling the power supply circuit 157 are converted and output.

FIG. 45 shows the switching timing of the display data and the correction data output to the X driver 2. FLM of control signal from control signal conversion unit 163
Display data for one screen for displaying the liquid crystal panel 1 in accordance with the display / correction switching signal of the control signal from the control signal conversion unit 163 during the period for displaying the liquid crystal panel 1 by (one screen, frame synchronization signal). And the correction data for correcting the distortion amount of the liquid crystal applied voltage waveform generated by the display data are transferred to the X driver 2 by switching the selector 159. Although the display period and the correction period are shown as being substantially equal in the figure, the correction period does not have to be the same length as the display period.

A method of generating and transferring display data and correction data will be described with reference to FIG. When the screen size of the liquid crystal panel 1 is X1 to Xm dots in the horizontal direction and Y1 to Yn dots in the vertical direction, the memory size of the frame memory 160 has a maximum column address Xm and a maximum row address Yn. On the other hand, the memory size of the correction data memory 162 is set to the maximum column address Xm, which is the same as the frame memory 160, and the maximum row address Yb. The display data of the column address Xa of the frame memory 160, that is, the display data of (column address, row address) = (Xa, Y1) to (Xa, Yn) is read, and the difference between the numbers of ON and OFF and O
The correction data for correcting the distortion amount of the liquid crystal applied voltage waveform generated by the arrangement of N and OFF is generated by the arithmetic circuit 161, and the column address X of the correction data memory 162 is generated.
a, that is, (column address, row address) = (Xa, Y
Store from 1) to (Xa, Yb).

FIG. 47 shows the internal structure of the arithmetic circuit 161 and the correction data generating method. As the internal configuration of the arithmetic circuit 161, (a) a correction data conversion circuit using an integration circuit,
(B) There are two types of correction data conversion circuits using a counter. (A) is the column address Xa of the frame memory 160
Display data, ie (column address, row address) =
With respect to the display data from (Xa, Y1) to (Xa, Yn), the display data integration circuit 161-1 integrates the display amount. This integrated value is A / D (analog /
The digital) conversion circuit 161-2 converts the correction data into the correction data, and the address (Xa, Y1) of the correction data memory 162.
To (Xa, Yb). (B) shows the column address X of the frame memory 160 by the counter 161-3.
The number of ON and OFF of the display data of a is counted, this is converted into correction data by the decoder 161-4, and similarly output from the address (Xa, Y1) to (Xa, Yb) of the correction data memory 162. To do.

As described above, the arithmetic circuit 161 displays the liquid crystal display data from ON to OFF or from OFF to O.
The number of change points to N and the number of change points of the AC signal M in the control signal are detected, and the data of the correction voltage application time or the correction voltage potential setting data corresponding to the amount of distortion of the liquid crystal application voltage waveform due to these is detected respectively. Is converted into the correction data memory 162, is temporarily stored in the correction data memory 162, and is output to the power supply circuit 158 as signal data for applying the correction voltage during the correction period. As a result, the fluctuation of the applied voltage effective value due to the liquid crystal applied voltage waveform distortion depending on the display pattern can be applied by controlling the correction voltage application based on the correction voltage application time data or the correction voltage potential setting data during the correction period. It is possible to correct unevenness in display brightness by eliminating the unevenness in display brightness.

The display data and the correction data transferred to the X driver 2 are output from the frame memory 160 and the correction data memory 162 in row address units. Then, the Y driver 3 receives the horizontal synchronizing signal (line clock CL1) of the control signal from the control signal converting unit 163.
The lines are sequentially scanned in synchronization with. Therefore, the period for displaying the liquid crystal panel 1 by the frame synchronization signal (hereinafter, FLM) of the control signal is displayed by the horizontal scanning period of the total (Yn + Yb) lines.

FIG. 48 shows a block diagram of the eighth embodiment of the present invention. This embodiment is almost the same as the seventh embodiment shown in FIG. 44, except that the output of the correction data memory 162 is applied not only to the X driver 2 but also to the power supply circuit 158. Frame memory 160, correction data memory 16
The configuration of No. 2 is as described above.

One screen of the liquid crystal panel 1 is displayed according to the display / correction switching signal of the control signal from the control signal converter 164 during the period of displaying the liquid crystal panel 1 by the FLM of the control signal from the control signal converter 164. Display data and correction data for correcting the distortion amount of the liquid crystal applied voltage waveform generated by this display data are switched by the selector 159 and transferred to the X driver 2, and the drive voltage of the power supply circuit 158 to the X driver 2 is changed. Is also switched and output.

FIG. 49 shows a first internal structural block example of the power supply circuit 158 in the eighth embodiment.

The power source voltage dividing circuit 165 has a liquid crystal drive power source VL.
CD is V1, V6, V correction 1, V3, V4, V correction 2,
The voltage is divided into V5 and V2, and V1, V6 and V are applied to the Y driver 3.
5, V2 is output, and the selector 16 is supplied to the X driver 2.
6 and 167 are correction voltages V correction 1 and V correction 2 of the distortion amount of the liquid crystal applied voltage waveform when the correction data L is output from the correction data memory 162, and liquid crystal applied voltage when the correction data H is output from the correction data memory 162. So that V becomes 0V
6. Select V5. Selectors 168, 169, 1
Reference numerals 70 and 171 denote the power supply voltage V for the normal display in the X driver 2 during the display period during the normal display data display (when the display / correction switching signal L) according to the display / correction switching signal.
1, V3, V4, and V2 are selectively supplied, and the select voltage of the selectors 166 and 167 is output during the correction period when the correction data is transferred (when the display / correction switching signal is H).

Output voltages V1, V6, V of the power supply circuit 158
Correction 1, V3, V4, V correction 2, V5, V2 is V1>
V6>V3>V4>V5> V2, V1 ≧ V correction 1 ≧ V
4, V3 ≧ V correction 2 ≧ V2.

FIG. 50 shows an example of the applied voltage waveform of the liquid crystal panel 1.

During the normal display data display period by the display / correction switching signal (when the display / correction switching signal is L)
Driving with the same drive voltage waveform as before, during the correction period when transferring the correction data (when the display / correction switching signal is H)
Means that when the correction data output from the correction data memory 162 is H, the applied voltage (VY-VX) of the liquid crystal panel 1 is (V
6-V Complementary voltage 2) is applied to correct the distortion amount of the liquid crystal applied voltage waveform generated during the display period, and the liquid crystal applied voltage is 0 V when the correction data is L during the subsequent correction period. So that

FIG. 51 shows an example of the second internal configuration block of the power supply circuit 158.

The power supply voltage dividing circuit 172 is a liquid crystal drive power supply VLC.
D is V1, V6, V correction 1, V3, V4, V correction 2, V
5 and V2, and the Y driver 3 is divided into V1, V6, V5,
Output V2. Selector 173 to X driver 2
Via the reference numeral 176, during the display period during the normal display data display (when the display / correction switching signal L), the power supply voltages V1, V3, V4 and V2 for normal display are selectively supplied to the X driver 2 to correct the correction data. During the correction period during transfer (when the display / correction switching signal H), V correction 1 and V correction 2 are output.
At this time, the output voltages V1, V6, V correction 1, V3, V4, V correction 2, V5, V2 of the power supply circuit 158 are V1> V6.
>V3>V4>V5> V2, V correction 1, V
The potential of the correction 2 is controlled by the correction data in the relationship of V correction 1 ≧ V correction 2, and each potential is selectively controlled by the correction data value and output.

FIG. 52 shows an example of a voltage waveform applied to the liquid crystal panel 1.

The display / correction switching signal is used to drive the same drive voltage waveform as in the prior art during the normal display data display period (when the display / correction switching signal L), and during the correction period during the correction data transfer (display / When the correction switching signal H)
The correction voltages Vcorrection 1 and V selected in the power supply voltage dividing circuit 172 based on the correction data output from the correction data memory 162.
Correction 2 is selected, and the applied voltage (VY-
VX) applies a voltage of (V6-V complementary 2) to correct the distortion amount of the liquid crystal applied voltage waveform generated during the display period.

FIG. 53 shows a block diagram of the ninth embodiment.
In this embodiment, the frame memory 160 in the seventh embodiment of FIG. 44 is replaced with a line memory 178, and the correction data memory 162 is replaced with the correction data line memory 18.
It is replaced with 0.

The line memory 178 stores one horizontal display data, and the arithmetic circuit 179 compares the data from the line memory 178 with the display data to be input next, and the applied voltage waveform distortion amount by the display data is calculated. Is converted into correction data, and the correction data line memory 180
To memory. The X driver 2 includes the line memory 1
One horizontal display data is read from 78 and is transferred and displayed. After that, the correction data is read from the correction data line memory 180 and transferred. The selector 181 switches the display data for one horizontal from the line memory 178 and the correction data from the correction data line memory 180 by a display / correction switching signal, and transfers it to the X driver 2 as display data for each line in the horizontal direction of the screen. ..

The line memory 178 and the correction data line memory 180 can be configured by using a memory IC described in Hitachi IC Memory Data Book (for example, the line memory HM63021 or the multiport memory HM534251), and the read cycle and the write cycle of the memory IC are It is controlled by a control signal that satisfies the access timing described in the Hitachi IC memory data book. Further, the line memory 178 and the correction data line memory 180 are 74 series TTL 7474, and can also be realized by configuring a data shifter.

Line clock CL1 of control signal
According to the display / correction switching signal of the control signal from the control signal conversion unit 163, which is not shown in FIG. 53, during the display cycle of the liquid crystal panel 1 by
One horizontal display data for displaying the liquid crystal panel 1 and correction data for correcting the distortion amount of the liquid crystal applied voltage waveform generated by this display data are switched by the selector 181 and transferred to the X driver 2 by the line clock XCL1. Then, the correction is performed in the cycle of the line clock CL1. Line clock X
CL1 has a frequency twice that of the line clock CL1.

FIG. 54 shows the transfer timing of the input display data and the correction data.

When the input display data is stored in the line memory 178 for one horizontal line display, the arithmetic operation circuit 179 compares the input display data with the input display data one horizontal before stored in the line memory 178. Then, it is converted into correction data for predicting and correcting the fluctuation of the effective value of the liquid crystal applied voltage due to the difference between the ON and OFF patterns and the number of display data. This correction data is stored in the correction data line memory 180.
Stored in line clock CL1, line clock X
Input display data and correction data are sequentially output to the X driver 2 in synchronization with CL.

The X driver 2 (or X driving circuit 2) and the Y driver 3 (or Y driving circuit 3) used in the above embodiments are column-side driving X driving represented by Hitachi HD66107T. Circuit 3 is Hitachi HD66107
It is a row-side driving Y drive circuit represented by T,
In the example in which Hitachi HD66107T is used as the X drive circuit, it is 4-dot or 8-dot parallel data, but here it is described as serial data for convenience of explanation.

A tenth embodiment of the present invention will be described below with reference to FIG.
~ It demonstrates using FIG.

As shown in FIG. 74, the conventional liquid crystal driver is a liquid crystal drive circuit inside the liquid crystal drive, and the power supply voltages V1, V2, V3, V are generated in accordance with the display data and the alternating signal M.
Switch 4 to output. "Hitachi LCD driver LSI
As shown in the explanatory diagram of the output terminals of the liquid crystal drive circuit section of the liquid crystal driver HD66104 / HD66104A described in P254 of Data Book '90 .3 (Fifth Edition), the power supply voltages V1, V2, V3, V4
Is switched to output from the X terminal.

In the tenth embodiment of the present invention, the liquid crystal drive circuit section in the liquid crystal driver has the same function as that of the voltage selectors 20 and 37 described above.

FIG. 55 shows an output terminal equivalent circuit diagram of the liquid crystal drive circuit portion of the tenth embodiment according to the present invention. The liquid crystal drive circuit inside the liquid crystal drive has six sets of switches and an on-resistance R _ON.
The power supply voltages V1, V2, V3, V4, V5, and V6 are switched to output from the X terminal. This power supply voltage switching is performed by the alternating signal M18 and the correction clock 19 as in the liquid crystal drive circuit unit according to the present invention shown in FIG.
It enables the operation shown in FIG. 5 or FIG. 27 described above.

FIG. 57 shows an internal block diagram of the liquid crystal driver when the enable signal E of the liquid crystal driver is used as the input correction clock 19 in the liquid crystal drive circuit section of FIG.

Further, in FIG. 58, the liquid crystal drive circuit having the same output terminal equivalent circuit as in FIG. 55 is operated in accordance with the correction clocks 35 and 36 as shown in FIG. 3 shows an internal block diagram of a liquid crystal driver incorporating a generation circuit 50. The amplifier section at the output stage of this liquid crystal drive circuit is replaced by elements 67 and 7 in FIG.
By generating with a buffer equivalent to each combination of 1, 68 and 72, 69 and 73, 70 and 74,
The same operation as that shown in FIG. 27 is possible.

Next, an eleventh embodiment of the present invention will be described with reference to FIG.
~ It demonstrates using FIG.

This embodiment is based on the voltage selectors 20 and 3 described above.
The liquid crystal drive circuit section in the liquid crystal driver is provided with the same function as that of 7.

FIG. 59 shows an output terminal equivalent circuit diagram of the liquid crystal drive circuit section according to the eleventh embodiment of the present invention. The liquid crystal drive circuit inside the liquid crystal drive has four sets of switches and on-resistance R
_When turned on, the power supply voltages V1, V2, V3, and V4 are switched and output from the X terminal. In this embodiment, any one of V1, V2, V3, and V4 is selected and output during normal display, but during the correction period, V1 and V3 are simultaneously output, or V4.
And V2 are simultaneously selected and output. V1 and V3, V4 and V2
Are output simultaneously, the potential of the X terminal output voltage is V1 when V1 and V3 are selectively output.
When V4 and V2 are selectively output to the combined voltage potential V6 of V3 and V3, the combined voltage potential V5 of V4 and V2 is obtained. As a result, this power supply voltage switching is performed by the alternating signal M1 as in the liquid crystal drive circuit unit according to the present invention shown in FIG.
8 and the correction clock 19 enable the operation shown in FIG. 5 or FIG.

FIG. 61 shows an internal block diagram of the liquid crystal driver when the liquid crystal drive circuit unit of FIG. 60 is used and the enable signal E input to the liquid crystal driver is used as the correction clock 19.

FIG. 62 shows an internal block diagram of a liquid crystal driver using the liquid crystal drive circuit section of FIG. 60 and incorporating the counter 18 described above.

Similarly, the liquid crystal drive circuit section inside the liquid crystal drive is provided with eight sets of switches and an on-resistance R _ON , the power source voltages V1, V6, V correction 1, V3, V4, V correction 2, V.
5, V2 is switched and output from the X terminal, and voltage selectors 151 to 156 having the internal configuration of the power supply circuit 136 and voltage selectors 166 to 17 having the internal configuration of the power supply circuit 158 are provided.
It is easily conceivable to have the same function as 1.
At this time, the power source voltages V1, V6, V
Correction 1, V3, V4, V correction 2, V5, V2 and a display / correction switching signal as a control signal for switching them, the output of the counter 149, or correction data is input.

As described above, the correction clocks 19, 35, and 36 of the liquid crystal drive circuit section of the tenth and eleventh embodiments are supplied by the enable signal E input by the liquid crystal driver, the built-in counter 18, and the correction clock generation circuit 50. Correction clocks 19, 35, 3 to be supplied from outside the liquid crystal driver
It is also possible to provide six input terminals.

FIG. 63 shows a liquid crystal driver incorporating the counter 18 and the voltage selector 20 as the correction circuit 182, and FIG. 64 shows the correction clock generation circuit 5 described above.
0 shows the liquid crystal driver which incorporates 0 and the voltage selector 37 as the correction circuit 183.

Finally, FIG. 75 shows a block diagram of an information device using the liquid crystal display device of any one of the above embodiments.

MP is added to the bus 760 for exchanging data.
U761, main memory 762, display controller 76
3 is connected, and the display controller 763 displays the display memory 7
Control for displaying the display data in 64 on the liquid crystal display device 765 is performed. In this way, a general information device is configured. The liquid crystal display device 765 can be configured by the above-described embodiment, but a part of the circuits in the above-described embodiment can be incorporated in the display controller 763 as follows.

First and Second Embodiments (FIGS. 1 and 8)
Then, it is possible to incorporate only the counter or the counter and the voltage selector in the display controller.

Third, fourth and fifth embodiments (FIG. 15,
In FIG. 31 and FIG. 33), only the correction clock generation circuit or the correction clock generation circuit and the selector and the display controller can be incorporated.

In the sixth embodiment (FIG. 34), the arithmetic circuit 1
35 can be built into the display controller.

In the seventh embodiment (FIG. 44), element 159
˜163, or in addition to this, the power supply circuit 157 can be built in the display controller.

In the eighth embodiment (FIG. 48), element 158
˜162 and 164 or elements 159-162 and 164 can be incorporated into the display controller.

In the ninth embodiment (FIG. 53), element 178
~ 181 can be built into the display controller.

[0160]

According to the present invention, a correction period is provided for each line scanning period or one screen scanning period regardless of the display pattern, and the correction period width or the correction voltage level is controlled according to the display data. By doing so, it is possible to reduce the variation in the effective value of the applied voltage of the liquid crystal cell depending on the display pattern, and it is possible to eliminate the display luminance unevenness that has occurred due to this variation.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an internal configuration example of a counter 18 shown in FIG.

3 is a block diagram showing a configuration of a voltage selector 20 shown in FIG.

FIG. 4 is an operation explanatory view of the voltage selector 20 of FIG.

5 is an operation explanatory diagram of the X drive circuit in the embodiment of FIG.

FIG. 6 is an operation explanatory view of the Y drive circuit in the embodiment of FIG.

7 is a timing chart showing a liquid crystal applied voltage waveform in the embodiment of FIG.

FIG. 8 is a block diagram showing a configuration of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 9 is a circuit diagram of a power supply voltage dividing circuit suitable for the second embodiment.

FIG. 10 is a block diagram showing the configuration of a voltage selector 20 suitable for the second embodiment.

11 is an explanatory diagram of the operation of the voltage selector 20 of FIG.

FIG. 12 is an operation explanatory diagram of the X drive circuit according to the second embodiment.

FIG. 13 is a timing chart showing a liquid crystal applied voltage waveform in the second embodiment.

FIG. 14 is an output waveform diagram of an X, Y drive circuit for explaining a third embodiment according to the present invention.

FIG. 15 is a block diagram showing a configuration of a liquid crystal display device according to a third embodiment.

FIG. 16 is a block diagram showing an example of a correction clock generation circuit according to a third embodiment.

17 is a block diagram showing an example of an ON display counter shown in FIG.

18 is an explanatory diagram of an operation table of the ON decoder shown in FIG.

19 is an explanatory diagram of an operation table of the decoder circuit shown in FIG.

20 is a timing chart representing an operation of the horizontal counter shown in FIG.

FIG. 21 is a block diagram showing another example of the correction clock generation circuit in the third embodiment.

22 is a circuit diagram showing an example of an ON display counter 51 shown in FIG.

23 is a circuit diagram showing an example of the adder 64-1 shown in FIG.

24 is a circuit diagram showing an example of an ON display number latch, a decoder, and a horizontal counter shown in FIG.

FIG. 25 is a circuit diagram showing still another example of the correction clock generation circuit in the third embodiment.

FIG. 26 is a voltage selector 20 according to each embodiment of the present invention.
The circuit diagram which shows the other example of (37).

27 is an explanatory diagram of a triangular wave correction output operation of the X drive circuit when the voltage selector of FIG. 26 is used.

28 is an output waveform diagram of the X drive circuit and the Y drive circuit when the voltage selector of FIG. 26 is used.

FIG. 29 is a timing chart showing a liquid crystal applied voltage waveform when the voltage selector of FIG. 26 is used.

FIG. 30 is a conventional top / bottom 2 to which a fourth embodiment of the present invention is applied.
The block diagram which shows the structure of a screen liquid crystal display device.

FIG. 31 is a block diagram showing the configuration of a liquid crystal display device according to a fourth embodiment.

FIG. 32 is a block diagram showing another configuration of a conventional upper / lower dual-screen liquid crystal display device to which the fifth embodiment of the present invention is applied.

FIG. 33 is a block diagram showing the configuration of a liquid crystal display device according to a fifth embodiment.

FIG. 34 is a block diagram showing the configuration of a liquid crystal display device according to a sixth embodiment of the present invention.

FIG. 35 is a timing chart representing an operation in the sixth embodiment.

FIG. 36 is a block diagram showing the internal configuration of an arithmetic circuit 135 according to the sixth embodiment.

FIG. 37 is a display data change point detection circuit 1 shown in FIG.
The block diagram which shows the internal structure of 37.

38 is a circuit diagram showing an internal configuration of the display data off / on change point detection circuit 140 shown in FIG.

39 is a circuit diagram showing an internal configuration of the display data on / off change point detection circuit 141 shown in FIG.

40 is a circuit diagram showing an internal configuration of an alternating signal M change point detection circuit 138 shown in FIG.

41 is a block diagram showing the internal configuration of the decoder 139 shown in FIG.

42 is a block diagram showing an internal configuration of the power supply circuit 136 shown in FIG.

43 is a circuit diagram showing an internal configuration of the power supply voltage dividing circuit 150 shown in FIG. 42.

FIG. 44 is a block diagram showing the configuration of a liquid crystal display device according to a seventh embodiment of the present invention.

FIG. 45 is a timing chart representing an operation in the seventh embodiment.

FIG. 46 is an explanatory diagram of a method of generating and transferring display data and correction data according to the seventh embodiment.

47 is an explanatory diagram of an internal configuration of the conversion circuit 161 shown in FIG. 44 and a correction data generation method.

FIG. 48 is a block diagram showing the configuration of a liquid crystal display device according to an eighth embodiment of the present invention.

49 is a block diagram showing an internal configuration of the power supply circuit 158 shown in FIG. 48.

FIG. 50 is a timing chart showing an example of waveforms of liquid crystal applied voltage to the liquid crystal panel in the eighth embodiment.

51 is a block diagram showing another internal configuration of the power supply circuit 158 shown in FIG. 48.

52 is a timing chart showing an example of a voltage waveform applied to the liquid crystal panel 1 when the power supply circuit 158 of FIG. 51 is used.

FIG. 53 is a block diagram showing the configuration of a liquid crystal display device according to a ninth embodiment of the present invention.

FIG. 54 is a timing chart representing an operation in the ninth embodiment.

FIG. 55 is an equivalent circuit diagram of the output terminals of the liquid crystal drive circuit unit according to the tenth embodiment of the present invention.

FIG. 56 is a block diagram showing the configuration of a liquid crystal drive circuit section according to the tenth embodiment.

FIG. 57 is a block diagram showing the internal structure of a liquid crystal driver using the tenth embodiment.

FIG. 58 is a block diagram showing another internal configuration of the liquid crystal driver using the tenth embodiment.

FIG. 59 is an output terminal equivalent circuit diagram of the liquid crystal drive circuit unit according to the eleventh embodiment of the present invention.

FIG. 60 is a block diagram showing a configuration of a liquid crystal drive circuit section according to an eleventh embodiment.

FIG. 61 is a block diagram showing the internal structure of a liquid crystal driver using the eleventh embodiment.

FIG. 62 is a block diagram showing another internal configuration of the liquid crystal driver using the eleventh embodiment.

FIG. 63 is a block diagram showing still another internal configuration of the liquid crystal driver using the eleventh embodiment.

FIG. 64 is a block diagram showing another internal configuration of a liquid crystal driver using the eleventh embodiment.

FIG. 65 is a block diagram showing a configuration of a conventional liquid crystal display device.

FIG. 66 is a circuit diagram showing a conventional power supply voltage dividing circuit.

67 is an operation explanatory diagram of the conventional X drive circuit. FIG.

FIG. 68 is an operation explanatory diagram of the conventional Y drive circuit.

FIG. 69 is an explanatory diagram of an example of a liquid crystal panel display pattern.

FIG. 70 is a timing chart showing a conventional liquid crystal applied voltage waveform.

FIG. 71 is a block diagram showing the configuration of another conventional liquid crystal display device.

72 is a circuit block diagram showing a specific configuration of the device shown in FIG. 71.

73 is a timing chart of applied voltage waveforms of the liquid crystal display device of FIG. 71.

FIG. 74 is an explanatory diagram of a configuration of a conventional liquid crystal driver.

FIG. 75 is a block diagram of an information device using the liquid crystal display device of the present invention.

[Explanation of symbols]

1 ... Liquid crystal panel, 2 ... X drive circuit, 3 ... Y drive circuit, 4
... mono-multi vibrator, 5 ... display data, 6 ... data latch clock, 7 ... line clock, 8 ... alternating signal, 9 ... head line clock, 10 ... enable signal,
11 to 16 ... Liquid crystal driving power supply voltage, 17 ... External supply voltage,
18 ... Counter, 19 ... Correction clock, 20 ... Voltage selector, 21-24 ... X drive power supply voltage, 25-28 ... Selector, 31-34 ... Correction voltage. 35, 36 ... Correction clock, 37 ... Voltage selector, 50 ... Correction clock generation circuit, 51 ... ON display counter, 52 ... ON number, 53 ... O
FF display counter, 54 ... OFF number, 55 ... Difference circuit, 5
6 ... Display difference, 57 ... Difference latch, 58 ... Difference data, 59 ...
Decoder circuit, 60 ... Correction clock position, 61 ... Horizontal counter, 62 ... ON decoder, 63 ... ON display number, 64
… ON adder, 65… Additional ON number, 66… ON latch,
67 to 74 ... Buffer circuit, 135 ... Operation circuit, 13
6, 157 ... Power supply circuit, 137 ... Display data change point detection circuit, 138 ... Alternation signal M change point detection circuit, 139 ...
Decoder, 140 ... Display data off / on change point detection circuit, 141 ... Display data on / off change point detection circuit, 1
42 ... Data shift, 143 ... Counter, 144 ... Counter, 145 ... State displacement detection, 146, 147, 148
Comparator, 149 ... Counter, 150 ... Power supply voltage dividing circuit, 151, 152, 153, 154, 155, 15
6 ... Selector, 159 ... Selector, 160 ... Frame memory, 161 ... Arithmetic circuit, 161-1 ... Integrating circuit, 16
1-2 ... A / D conversion circuit, 161-3 ... ON / OFF counter, 161-4 ... Decoder, 162 ... Correction data memory, 163, 164 ... Control signal conversion circuit, 1
65 ... Power supply voltage dividing circuit, 166, 167, 168, 16
9, 170, 171 ... Selector, 172 ... Power supply voltage dividing circuit, 173, 174, 175, 176 ... Selector, 17
7 ... Power supply circuit, 178 ... Display line memory, 179 ... Arithmetic circuit, 180 ... Correction data line memory, 181 ... Selector, 182, 183 ... Correction circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (31) Priority claim number Japanese Patent Application No. 4-9000 (32) Priority date Hei 4 (1992) January 22 (33) Country of priority claim Japan (JP) (31) Priority Claim number Japanese patent application No. 4-9006 (32) Priority date 4 (1992) January 22 (33) Country of priority claim Japan (JP) (72) Inventor Satoshi Onuma 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Incorporated company Hitachi Image Information System (72) Inventor Tatsuhiro Inuzuka 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Incorporated Hitachi Image Information System (72) Inventor Koji Takahashi 3300 Hayano, Mobara-shi, Chiba Co., Ltd. Hitachi Ltd. Mobara factory

Claims (22)

[Claims] 1. A voltage having a potential difference between a scanning voltage from a Y driving circuit and a display voltage from an X driving circuit is applied to a liquid crystal cell at an intersection of a scanning electrode (Y electrode) and a data electrode (X electrode). In the method of driving a liquid crystal display device for performing display according to display data, a correction period for correcting the display voltage output from the X drive circuit is provided at least once for each line scanning period, and within the correction period. , Instead of the display voltage from the X drive circuit,
A method for driving a liquid crystal display device, comprising outputting a correction voltage having a voltage level intermediate between the voltage level during ON display and the voltage level during OFF display. 2. The voltage applied to the liquid crystal cell is set by setting the correction voltage output from the X drive circuit within the correction period to the same level as the voltage output from the Y drive circuit during non-scanning. The method of driving a liquid crystal display device according to claim 1, wherein the voltage is set to 0 V during the correction period. 3. The correction voltage for each data electrode output from the X drive circuit within the correction period is set to ON and OFF.
The driving method of the liquid crystal display device according to claim 1, wherein the driving time is different from that during F display. 4. The difference between the level of the ON display voltage output from the X drive circuit and the level of the correction voltage, and the X
4. The method for driving a liquid crystal display device according to claim 1, wherein the difference between the level of the OFF display voltage output from the drive circuit and the level of the correction voltage is made different. 5. The method of driving a liquid crystal display device according to claim 1, wherein the waveform of the correction voltage is triangular. 6. A method of counting at least one of ON display pixels and OFF display pixels included in display data within one line scanning period, and determining the time width of the correction period or the application time width of the correction voltage according to the counting result. The method for driving a liquid crystal display device according to claim 1, wherein the method is controlled. 7. A voltage having a potential difference between a scanning voltage from a Y driving circuit and a display voltage from an X driving circuit is applied to a liquid crystal cell at an intersection of a scanning electrode (Y electrode) and a data electrode (X electrode). In a method of driving a liquid crystal display device for performing display according to display data, a correction period for correcting the display voltage output from the X drive circuit is provided at least once for each screen scanning period, and The magnitude or application time width of the correction voltage to be applied to the data electrode is determined according to the content of the display data given to each data electrode, and the X drive is performed for each data electrode within the correction period. A method for driving a liquid crystal display device, wherein the circuit outputs the correction voltage instead of the display voltage. 8. A driving device of a liquid crystal display device, wherein a voltage is applied to a liquid crystal cell at an intersection of a scanning electrode (Y electrode) and a data electrode (X electrode) to perform display according to display data. A scan electrode that sequentially selects one of the scan electrodes to apply a scan voltage for each one-line scan period and applies a non-scan voltage to another scan electrode that is not selected at that time. A driving unit, a data electrode driving unit that applies a display voltage corresponding to the content of display data input from the outside to the data electrode, and a scanning electrode driving unit that selects each scanning electrode in advance. Only for the set correction period, instead of the display voltage output from the X drive circuit, a correction voltage having an intermediate voltage level between the ON display voltage level and the OFF display voltage level is applied to all the data. Driving device for a liquid crystal display device including a voltage control means for applying to the data electrode. 9. The voltage control means applies a correction voltage applied to each data electrode within the correction period to the data electrode.
9. The drive device for a liquid crystal display device according to claim 8, wherein the display device is made different depending on whether it is N display or OFF display. 10. The driving device for a liquid crystal display device according to claim 8, wherein the correction voltage is a voltage of the same level as a voltage output from the scanning electrode driving means in the non-scanning state. 11. The driving device for a liquid crystal display device according to claim 8, wherein the correction voltage is a voltage of a level close to a voltage output from the scan electrode driving means in a non-scan state. 12. The driving device of a liquid crystal display device according to claim 8, wherein the voltage control means also has a function of controlling a time width of the correction period or a time width of application of the correction voltage. 13. A counter for counting at least one of an ON display pixel and an OFF display pixel included in display data during one line scanning period, further comprising: the voltage control means based on a counting result of the counter. 13. The driving device of the liquid crystal display device according to claim 12, wherein the application time width of the correction voltage in the line scanning period is controlled. 14. The voltage control means separately determines an application time width of a correction voltage applied to each data electrode within the correction period depending on whether the data electrode is ON display or OFF display. Item 14. A drive device for a liquid crystal display device according to item 13. 15. The voltage control means sets the application time width of the correction voltage to the number of ON display pixels in the one line scanning period and O.
14. The drive device of the liquid crystal display device according to claim 13, wherein the control is performed based on a difference from the number of FF display pixels. 16. The driving apparatus for a liquid crystal display device according to claim 8, wherein the voltage control means includes a waveform control means for slowing the slopes of the rising edge and the falling edge of the correction voltage. 17. A change point detection circuit for detecting the number of change points of display data in one line scanning period, wherein the voltage control means sets the application time width of the correction voltage based on the detected number of change points. It controls, It is characterized by the above-mentioned.
2. The drive device for the liquid crystal display device according to 2. 18. Display data for one line scanning period and part 1 thereof
It is further characterized by further comprising a calculating means for comparing and calculating the display data of one line scanning period before the line, and the voltage controlling means controls the application time width of the correction voltage based on the calculation result of the calculating means. The drive device for a liquid crystal display device according to claim 12. 19. A liquid crystal panel divided into two upper and lower screens, two data electrode driving means for applying a display voltage in accordance with the display data respectively applied to the upper and lower screens, and one scanning electrode driving means for simultaneously applying a scanning voltage to the upper and lower screens. 9. The drive device for a liquid crystal display device according to claim 8, wherein the voltage control means is shared by the two data electrode drive means. 20. Two data electrode driving means for giving a display voltage according to display data given to the upper and lower screens of a liquid crystal panel divided into two upper and lower screens, and two scanning electrode drives for giving a scanning voltage to the upper and lower screens respectively. 9. The driving apparatus for a liquid crystal display device according to claim 8, further comprising: means, wherein the voltage control means is separately provided for the two data electrode driving means. 21. The driving device of the liquid crystal display device according to claim 8, wherein the voltage control means is built in the data electrode driving means. 22. A driving device of a liquid crystal display device for applying a voltage to a liquid crystal cell at an intersection of a scanning electrode (Y electrode) and a data electrode (X electrode) to perform display according to display data. A frame memory for storing display data for one minute, and a scanning voltage is applied by sequentially selecting one of the scanning electrodes for each predetermined one-line scanning period, and the other is not selected at that time. Scan electrode driving means for applying a non-scan voltage to all scan electrodes and applying a non-scan voltage to all scan electrodes during a correction period provided after scanning one screen, and contents of display data input from the frame memory. Data electrode driving means for applying a display voltage corresponding to the data electrodes to the data electrodes, and the data electrode driving means for applying the display data to the data electrodes within one screen scanning period according to the contents of the display data. Calculating means for calculating the magnitude or the application time width of the correction voltage to be applied to the data electrode, and voltage control means for outputting the correction voltage instead of the display voltage to each data electrode during the correction period, A drive device for a liquid crystal display device, comprising: