JPS61242473A - Automatic pedestal level clamping circuit - Google Patents

Abstract

PURPOSE:To obtain a circuit which is low in its cost, small in size and has high universality by applying a DC potential from two switches to a DC stopping capacitor by a pedestal level clamp pulse opened and closed by a pedestal level clamp pulse and executing a pedestal level adjustment. CONSTITUTION:In case when there are many low parts of a luminance signal 'it is dark as a whole', a period in which a clock 112 can pass through the first gate circuit 101 increases and when its output 115 is inputted into a specified period exceeding a counting value set in advance in order to execute the decision of 'it is dark as a whole' to a counting circuit 102, the counting circuit 102 judges 'dark' as a whole and its result 118 is read in the end of the specified period by a latching circuit. On the other hand, in case when the luminance signal is 'it is dark as a whole', a period in which the clock 112 can pass through a gate 105 decreases, a counting circuit 106 decides to be 'it is dark as a whole', and its result 119 is read in the end of the specified period by a latching circuit 107.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement of an autopedestal level clamp circuit in an automatic brightness adjustment circuit for a television.

[Conventional technology]

An example of a conventional autopedestal level clamp circuit is shown in Fig. 2. In Fig. 2, 201 outputs a divided voltage of the + side of the power supply voltage (hereinafter referred to as VDD) and one side of the power supply voltage (hereinafter referred to as VSS). Volume, 202 is a diode, 204.205.209.210 is a capacitor, 206.206.208 is a resistor, 207 is a transistor, 211 is a pedestal level clamp switch that opens and closes with a pedestal level clamp pulse, 212 is a quantization of the composite video signal It is an A/L) converter.

In FIG. 2, a diode connected to an intermediate terminal of a volume 201 clamps the composite video signal passing through a capacitor 205, and the clamped composite video signal is smoothed by a resistor 203 and a capacitor 204. The collector current of the transistor 207 changes according to the change in this smoothed potential, and the capacitor 209 is charged and discharged. As a result, when a bright screen with a large luminance signal in the composite video signal is obtained, the base potential of the transistor 207 rises, so the collector current increases, the capacitor 209 is discharged, and the potential of the capacitor falls. On the other hand, when the screen becomes dark with a small brightness signal, the capacitor is charged,
Potential increases.

FIG. 7 is a timing chart showing the relationship between the pedestal clamp pulse and the opening/closing of the pedestal clamp switch for the composite video signal for approximately 2H of the horizontal period (hereinafter referred to as H) of the composite video signal. ) is the composite video signal, FIG. 7 (Bl is the pedestal level that becomes high level from the rise of the horizontal periodic signal in the composite video signal excluding the DC level until the appearance of the luminance signal (hereinafter referred to as back porch) Clamp pulse is shown.

In Figure 7 (q), the state in which both ends of the pedestal level clamp switch are conducting is shown as closed, and the state in which both ends of the pedestal level clamp switch are non-conducting is shown as open. Therefore, charge flows into and out of the DC blocking capacitor of the composite video signal so that the voltage on the back porch (hereinafter referred to as pedestal level) and the voltage at the other end of the pedestal clamp switch are equal.

The reason for configuring the autopedestal level clamp circuit in this way is that it is difficult to display multiple gradations when the image contrast is low, such as in a time-division drive display on an LCD TV, and the dynamic range of the gradation display can be made brighter. When adjusting to fit the screen, there are problems such as insufficient gradation on dark screens. Therefore, by narrowing the dynamic range determined by the A/D converter, etc., the pedestal level is lowered for bright screens to display more gradations of bright images, while for dark screens the pedestal level is raised to display more gradations of dark images. By displaying multiple values, one autopedestal clamp circuit is required to provide an averaged display.

[Problem that the invention seeks to solve]

However, in order to obtain a high-quality display screen, the circuit shown in FIG. 2 requires fine adjustment of the volume 201 shown in FIG. 2, which increases the number of steps and increases the cost. Also, in Figure 2, capacitors 204 and 205
．． Since 209 has a value of 0.1 to several tens of μF, it cannot be integrated into an IC, and this circuit must be constructed from individual components, which poses problems such as hindering cost reduction and miniaturization of the circuit. Furthermore, in the circuit shown in Figure 2, the output of the A/D converter is not fed back to the pedestal level setting, so it is necessary to precisely select the constants of the components that make up the circuit. Sexuality decreases.

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks and provide an autopedestal level clamp circuit that is low cost, compact, and highly versatile.

Means for Solving the Problems] The present invention has a configuration that includes a luminance signal level detector that detects the level of a luminance signal of a composite video signal that passes through a DC blocking capacitor and is input, and an output of the luminance signal level detector. first and second gate circuits that input the signal, first and second counting circuits that count the signals from the first and second gate circuits, and latches the first and second counting circuits, respectively. It has first and second latch circuits that actuate, and first and second switches that are actuated by outputs from the first and second latch circuits, respectively, and that actuate the DC potential from the first or second switch. The pedestal level is adjusted by applying voltage to the DC blocking capacitor using a pedestal level clamp switch that opens and closes using the pedestal level clamp pulse.

〔Example〕

FIG. 1 is a block diagram of a first embodiment of the present invention. In FIG. 1, the direction indicated by the arrow indicates the direction in which the signal advances, and 101 determines that it is "dark" when the level of the luminance signal is low based on the output of the luminance signal level detector, and the continuous 102 is a clock that can pass through the first gate circuit 101 indicated by 115 during a specific period provided to judge the brightness of the overall luminance signal. A first counting circuit 103 counts the output, and a first counting circuit 103 latches the judgment ``totally bright'' or ``totally dark'' indicated by 118 as the output of the first counting circuit at the end of a specific period. The latch circuit 104 is connected to VDD as a DC potential, and the latch circuit 121
The first switch 105 is closed when the output of the first latch circuit is "totally dark", and the switch 105 is "bright" when the luminance signal level is high based on the output of the luminance signal level detector. 106 is a second counting circuit that counts the clock output that has passed through the second gate circuit 105 indicated by 116 during a specific period, and 107 is a second gate circuit that passes the clock 112. At the end of the period, the second latch circuit 108 latches the judgment of ``totally bright'' or ``totally dark'' shown by 119 as the output of the second counting circuit, and 108 is connected to VSS as a DC potential. , a second switch that is closed when the output of the second latch circuit indicated by 122 is "overall bright";
09 is a pedestal level clamp switch connected to the first and second switches 104 and 108, 110 is a DC blocking capacitor for the input composite video signal, and 111 is a DC blocking capacitor 110 whose input terminal is connected to the pedestal level clamp switch 109 and 108. 4-bit A/
The D converters 116 and 114 are the quantized outputs of the A/D converter 111 used as a luminance signal level detector,
or the comparator output inside the A/D converter,
117, the first and second counting circuits 10 at the beginning of a specific period;
2. Reset signal input to 106, 120 is input to the first and second switch 1 during the period when the screen is not displayed, such as the vertical retrace section.
04. Signal input to the first and second latch circuits 103 and 107 to open 108.

123 is a pedestal level clamp pulse, 124 is a first and second latch circuit 103.107 at the end of a specific period.
are the outputs 118 and 119 of the first and second counting circuits, respectively.
125 is the A/D converter 11
4-bit quantized output of 1 is shown.

In FIG. 1, in the case of "total darkness" where there are many low parts of the luminance signal, the period during which the clock 112 can pass through the first gate circuit 101 increases, and the output 115 is sent to the first counting circuit 102 in advance. If a count value greater than or equal to the predetermined count value is input within a specific period to determine that the whole is dark, the first counting circuit 102 determines that the whole is dark, and the result 118 is The first latch circuit reads at the end of the specified period.

On the other hand, when the luminance signal is "totally dark", the period during which the clock 112 can pass through the second gate 105 is shortened, and its output 116 is sent to the second counting circuit 106 to determine in advance that it is "totally bright". You can only input less than the count value that you have set in order to
Therefore, the second counting circuit 106 determines that the entire image is dark, and the second latch circuit 107 reads the result 119 at the end of the specific period.

As a result, the outputs 121, 122 of the first and second latching circuits cause the first switch 104 to be closed, while the second switch is open, and the pedestal level clamp switch 109 is closed, for a specific period of time. When this happens, charge flows into the DC blocking capacitor 110 due to the charging characteristics determined by the resistances of the switches 104 and 109, the wiring, and the DC blocking capacitor 110, and the A/D converter 11
The pedestal level of the composite video signal input to 1 is increased.

On the other hand, in the case of "generally bright" in which there are many parts where the luminance signal level is high in FIG. Therefore, within a specific period, the clock output 115 of the first gate circuit becomes less than or equal to the count value of the first counting circuit 102 that determines that "the whole is dark", so the first counting circuit 102 The clock output 11 of the second gate circuit
6 is greater than the count value determined by the second counting circuit to be "bright overall," so the second counting circuit 106 determines that it is "bright overall," and calculates the respective results 118 and 119 for a specific period. At the end of , the first and second latch circuits read.

As a result, during a certain period of time the first switch 104 is open;
When the second switch 108 is closed and the pedestal level clamp switch is closed, charge flows out from the DC blocking capacitor 110 due to the discharge characteristics determined by the circuit, and the pedestal level of the composite video signal input to the A/D converter 111 decreases. do.

In addition, in FIG. 1, when the level of the luminance signal is averagely thick (neither large nor small), the clock output 115 passing through the first and second gate circuits 101 and 105
, 116 are not so large, at the end of a specific period, the first counting circuit 102 judges that the whole is bright, while the second counting circuit 106 judges that the whole is dark. The first and second latch circuits 103 and 107 read the output results 118 and 119.

As a result, in the next specific period, the first and twentieth switches 1
04.108 are both open and the pedestal level is not adjusted.

The first and second counting circuits 102,' 1 during the previous specific period
If it is determined that both 06 and 06 are "overall dark," the pedestal level of the composite video signal input to the A/D converter 111 will rise slightly in the next specific period.
The luminance signal level input to the /D converter 111 increases, forming a feedback loop so as to approach an intermediate state.

Conversely, in the case of "overall brightness", a feedback loop is similarly formed to approach the intermediate state.

FIG. 3 is a circuit diagram of the first and second gate circuits 101 and 105 used in the first embodiment of FIG. 1, and FIG.
and Fig. 3 (Bl is the first gate circuit, Fig. 3 (q and the third
(DJ is the second gate circuit.

In Figure 3, the same numbers as in Figure 1 correspond to the same signals,
301 is a comparator output that outputs K/% level when the level of the luminance signal input into the A/D converter is below a specific threshold value, and inputs it to the first gate circuit;
02 is the most significant bit output of the A/D converter, 30
3 is the second most significant bit output of the A/D converter,
304 is the same as the comparator that performs the output 302 or has a high threshold (output of a comparator with the same operation, 305
is an AND circuit, 606 is a NOR circuit, and 307 is an inverter. The first gate circuit is shown in Figure 3 (Al and the third gate circuit).
In the circuit shown in Figure (Bl), when the level of the luminance signal is low, whether the output 301 of the comparator is high level or the A/D
When both the most significant bit output 602 and the second bit output 303 of the converter are at a low level, it is determined that it is "dark" and the clock is passed. On the other hand, when the brightness signal level is high, the output 601 of the converter is at a low level. Or, either the upper two bits output 302 or 303 becomes /1 level, and it is judged as "bright" and the clock is not passed.

As the second gate circuit, the circuit of FIG. 3 (q) and FIG.
．． Both of the signals 606 and 606 become high level, and it is determined that the brightness is "bright" and the clock 112 is passed. On the other hand, when the luminance signal level is low, the output 304 of the comparator becomes high level, or at least of the upper two bit outputs 602 and 303. One side becomes low level, and it is judged as ``dark'' and the clock is not allowed to pass through.

FIG. 4 is a circuit diagram of the first and second counting circuits 101 and 102 used in the first embodiment shown in FIG.

401.402.403.404.40 in Figure 4
5.406 is a frequency divider, φ is the clock input, R is 4
11 is the input terminal of the reset signal that is input at the beginning of a specific period corresponding to the signal 117 in FIG. 1
06 and 408 and 409 are NOR circuits and R-S flip 7.
The reset signal 411 and the AND circuit 40
7 is input, and 410 is the first or second input in FIG.
412 corresponds to the outputs 118 and 119 of the first and second counting circuits in FIG. Output.

FIG. 5 shows the first and second latch circuits 103, 107 and the first and second switches 104, 10 of the first embodiment shown in FIG.
8, a pedestal level clamp switch 109, and a DC blocking capacitor 110.

In Figure 5, the same numbers as in Figure 1 correspond to the same signals,
501 is a data type 7 lip-flop (hereinafter referred to as D-FF) used as the first latch circuit 103 in FIG. is a reset input terminal into which a signal 120 for opening both the first and second switches in the vertical retrace interval etc. is input, θ is a normal rotation output, θB is an inversion output, 502
is the D-FF used as the second latch circuit in FIG.
03 is P- used as the first switch 104 in FIG.
D-FF50 is a MOSFET and is the first latch circuit.
When the content of the holding note 1 is output is "total darkness", the θB ratio output of the D-FF 501 is at a low level, so the first switch 503 is closed, and the switch 504 is the second switch in FIG. The N-MOSFET used as the switch 108 is used to hold and hold the D-FF 502, which is the second latch circuit.
D if the output content is "overall bright"
- The θ output of the FF 502 becomes high level, the second switch 504 is closed, 505 is an inverter, 506 is a transmission gate, the inverter 505 and transmission gate 506 constitute a pedestal level clamp switch, and 507 is a composite video signal. It is a DC blocking capacitor.

FIG. 6 is a timing chart showing an example of the timing of the reset signal of the first counting circuit and the second counting circuit and the reading clock of the first latch circuit and the second latch circuit with respect to the composite video signal.

In Figure 6, a specific period is a horizontal period, Figure 6 (body) is a composite video signal, Figure 6 (B) is a reset pulse output at the beginning of a specific period, and Figure 6 (B) is a specific This is the reading pulse output at the end of the period.

FIG. 8 is a block diagram showing a second embodiment of the present invention, in which the same numbers as in FIG. 1 have the same functions.

In FIG. 8, 801 is a resistor, and 802 is a capacitor. The resistor 801 and the capacitor 802 constitute a smoothing circuit to smooth the Phytopack from the A/D converter.

As a result, the pedestal level changes slowly, making it especially effective for small-amplitude composite video signals.In addition, the timing at which the first and second switches close is set to the same timing as the pedestal clamp switch. By adding a control function to the first latch circuit and the second launch circuit, the pedestal level clamp switch can be omitted.

This is considered an application of the present invention.

Furthermore, it is convenient to use the sampling clock of the A/D converter or its inversion as the clock that passes through the first gate circuit and the second gate circuit.

In addition, in order to finely adjust the pedestal level clamp, the first switch 104 and the second switch 1 in FIG.
08 and the pedestal level clamp switch 109 may be connected to a DC potential such as VDD or SS using a variable resistor or a fixed resistor. Furthermore, when considering the temperature characteristics of a liquid crystal panel, etc., the material of the resistor may be selected so that the change in resistance value of the resistor due to temperature becomes the optimum value for adjustment. This circuit can also be applied to a CRT display type television.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the autopedestal level clamp circuit can be constructed almost entirely from digital circuits, making it easy to incorporate into an IC, thereby reducing component costs and making it possible to downsize. .

Furthermore, since the pedestal level is determined by feeding back the output of a luminance signal level detector such as an A/D converter, a high-quality screen can be obtained without adjustment, reducing adjustment costs. Since there are almost no constraints on the amplitude, versatility is improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the first embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional autopedestal level clamp circuit, and FIG. The first gate circuit diagram, FIG. 3 (C1, (D) is a circuit diagram showing an example of the second gate circuit of the first embodiment, and FIG. 4 is a circuit diagram showing an example of the second gate circuit of the first embodiment. The circuit diagram used in the counting circuit of FIG. 5 shows the first and second latch circuits of the first embodiment and the first
A circuit diagram showing an example of a circuit including a second switch, a transmission gate, and a DC blocking capacitor, FIG. 6 (5) shows a composite video signal, and FIG. 6 (B) shows a circuit diagram of a first counting circuit and a second counting circuit. Set signal, Fig. 6 (q is a waveform diagram of the reading clock of the first latch circuit and second latch circuit, respectively, Fig. 7 CAI is a composite video signal, Fig. 7 (Bl is a pedestal level clamp pulse, Figure 7 (q is a waveform diagram of the timing of opening and closing of the vedestal level clamp inch, Figure 8 is a block diagram of the second embodiment of the present invention. 101... First gate circuit, 102... ...
...First counting circuit, 103...First latch circuit, 104...First switch, 105...
...Second gate circuit, 106...Second counting circuit, 107...Second latch circuit, 10
8...Second switch. Figure 1, 2nd flash, 3rd A (A) (B) (C) (0)
Figure 5 Figure 6 (B) (C) Figure 7

Claims (6)

[Claims] (1) In a circuit that automatically adjusts the pedestal level of a television signal, input the luminance signal level detector that detects the luminance signal level of the composite video signal from the DC blocking capacitor and the output of the luminance signal level detector. first and second gate circuits that count the signals from the first and second gate circuits, respectively, and latches the outputs of the first and second counting circuits, respectively. It has first and second latch circuits and first and second switches that are respectively operated by the outputs from the first and second latch circuits, and the DC potential from the first or second switch is applied to the pedestal. An auto pedestal level clamp circuit characterized in that a pedestal level clamp switch that opens and closes in response to a level clamp pulse applies voltage to the DC blocking capacitor to adjust the pedestal level. (2) The luminance signal level detector quantizes the luminance signal A
The autopedestal level clamp circuit according to claim 1, wherein the autopedestal level clamp circuit is a /D converter. (3) Claim 1, characterized in that the first and second counting circuits count for a predetermined specific period.
Auto pedestal level clamp circuit described in section. (4) The autopedestal level clamp circuit according to claim 3, wherein the specific period is a luminance signal period within one horizontal period. (5) The auto pedestal level clamp circuit according to claim 1, wherein the pedestal level adjustment operates only during a period excluding a vertical retrace period. (6) The auto pedestal level clamp circuit according to claim 1, characterized in that a resistor is connected between the first or second switch and the pedestal level clamp switch.