JPH0646788B2 - Auto pedestal level clamp circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to an improvement of an automatic pedestal level clamp circuit in an automatic brightness adjustment circuit of a television.

[Conventional technology]

A circuit diagram of a conventional auto pedestal level clamp circuit is shown in FIG. In FIG. 2, 201 is a + side of the power supply voltage (hereinafter referred to as VDD) and a − side of the power supply voltage (hereinafter referred to as VSS).
(Referred to as a), a 202 is a diode, 202 is a diode, 204, 205, 209 and 210 are capacitors, 203, 206 and 208 are resistors, 207 is a transistor, and 211 is a pedestal level clamp switch that opens and closes with a pedestal level clamp pulse. , 21
Reference numeral 2 is an A / D converter for quantizing the composite video signal.

In FIG. 2, the diode connected to the intermediate terminal of the volume 201 clamps the composite video signal that has passed through the capacitor 205, and the clamped composite video signal is smoothed by the resistor 203 and the capacitor 204. According to the change in the smoothed potential, the transistor 207
The collector current of the capacitor changes and charging / discharging of the capacitor 209 occurs. As a result, when a bright screen with a large luminance signal in the composite video signal is obtained, the base potential of the transistor 207 rises, the collector current increases, and the capacitor 20 increases.
9 is discharged, and the potential of the capacitor drops. On the other hand, when the screen becomes dark with a small luminance signal, the capacitor is charged and the potential rises.

FIG. 3 is a timing chart showing the relationship between the opening and closing of the pedestal clamp pulse and the pedestal clamp switch with respect to the composite video signal for about 2H of the horizontal cycle (hereinafter referred to as H) of the composite video signal. ) Is a composite video signal, and FIG. 3 (B) is a high level signal from the rise of the horizontal cycle signal in the composite video signal from which the DC level has been removed to the appearance of the luminance signal (hereinafter referred to as the back porch). A destal level clamp pulse is shown.

In Fig. 3 (C), the state in which both ends of the pedestal level clamp switch are conducting is shown as closed, and the state in which the pedestal level clamp switch is not conducting is shown as open. As a result, charges flow in and out of the DC blocking capacitor of the composite video signal so that the back porch voltage (hereinafter referred to as the pedestal level) and the voltage at the other end of the pedestal clamp switch become equal.

The reason why the auto-pedestal level clamp circuit is configured in this manner is that multi-gradation display becomes difficult when the image contrast is low such as time-division drive display of a liquid crystal television, and the dynamic range of gradation display is bright. There is a problem such as lack of gradation on a dark screen when adjusting to the screen. Therefore, by narrowing the dynamic range determined by the A / D converter and the like, the pedestal level is lowered on a bright screen to display many gradations of a bright image, while the pedestal level is increased on a dark screen to display gradations of a dark image. With many displays, an auto-pedestal clamp circuit that displays averaged values is required.

[Problems to be solved by the invention]

However, since the circuit shown in FIG. 2 requires fine adjustment of the volume 201 of FIG. 2 in order to obtain a good display screen, the number of steps is increased, resulting in an increase in cost. Also, in FIG.
Since 5 and 209 cannot be integrated into an IC because they are 0.1 to several tens of microfarads, this circuit must be composed of individual parts, which leads to problems such as low cost and hindering miniaturization of the circuit. there were. Furthermore, in the circuit shown in FIG. 2, the output of the A / D converter is not fed back to the setting of the pedestal level, so it is necessary to precisely select the constants of the components that make up the circuit, and to the amplitude of the composite video signal. Versatility decreases.

An object of the present invention is to improve the above drawbacks and to provide a low cost, compact and highly versatile auto pedestal level clamp circuit.

[Means for solving problems]

The present invention detects the level of a luminance signal in a composite video signal, detects the first detection signal when the level is in the first region, and detects the second detection signal when the level is in the second region. Output,
A luminance signal level detector and a luminance signal period of the composite video signal, which operate based on the first and second detection signals,
First and second switches for electrically connecting a common terminal to a first voltage source and a second voltage source, respectively, and a smoothing circuit for smoothing a voltage signal from the common terminal and guiding it to a pedestal level adjustment voltage applying section. And are provided, depending on the level of the luminance signal,
During the period corresponding to the pedestal level, the first or second
The voltage of the voltage source is applied to the composite video signal.

〔Example〕

FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, the direction indicated by the arrow indicates the direction in which the signal travels.
Reference numeral 01 is a luminance signal period signal indicating a period in which a luminance signal exists in the composite video signal, 102 and 103 are outputs of the lowest and highest comparators of the A / D converter, respectively.
4 is the lowest comparator output 10 of the A / D converter
2 and the luminance signal period signal 101 are input, the first gate for synthesizing the control signal of the first switch is input, 105 is the output 103 of the uppermost comparator of the A / D converter and the luminance signal period signal 101 is input, A second gate for synthesizing the control signal of the second switch, 106 and 107 are first and second gates 10 for controlling the first and second switches, respectively.
4 and 105 outputs, and 108 and 109 each have V at one end
First and second switches connected to DD and VSS, 110
Is a smoothing circuit input by the connecting portion of the first and second switches 108 and 109, 111 is an output of the smoothing circuit 110, and 112
Is a pedestal level clamp pulse, 113 is a pedestal level clamp switch connected to the output 111 of the smoothing circuit, 114 is a DC blocking capacitor that removes the DC component of the composite video signal, and 115 is a composite video to which a DC bias is applied by the pedestal clamp switch 113. The signal is input and the output 102 of the lowest and highest comparators,
4-bit A / D converter for performing 103, 116 for A
This is a 4-bit quantized output of the / D converter 115.

In FIG. 1, when the low luminance signal level corresponding to the dark portion of the display image cannot exceed the threshold value of the lowest comparator of the A / D converter 115 (hereinafter referred to as underflow), the first gate 104 is The first switch is closed and the smoothing circuit is connected to VDD. On the contrary, the high luminance signal level corresponding to the bright part of the displayed image is A / D.
When the threshold value of the highest comparator of the converter 115 can be exceeded (hereinafter referred to as overflow), the second gate 105 closes the second switch 109 and connects VSS to the smoothing circuit. Further, the first and second gates 1 are provided when the luminance signal level does not underflow or overflow, and in the non-display period such as the vertical blanking interval or the horizontal blanking interval.
Nos. 04 and 105 open the first and second switches, respectively, and input nothing to the smoothing circuit.

Thus, in the embodiment of FIG. 1, when the dark screen has a large amount of underflow, VDD is often connected to the smoothing circuit 110, so that the voltage of the output 111 of the smoothing circuit rises and the pedestal level clamp switch. When 113 is closed, the DC bias of the composite video signal input to the A / D converter 115 is increased to form a feedback loop so as to brighten the display image. On the other hand, when there are many bright overflows, the DC bias is lowered to form a feedback loop so as to darken the displayed image. As a result, the DC bias of the composite video signal input to the A / D converter 115 is stabilized so that the areas of the underflow and overflow areas of the display screen are equalized, so that the contrast of the display device can be effectively used.

FIG. 4 is a circuit diagram showing an example of the first and second gates, the switch, the smoothing circuit, and the control circuit for the operation in the non-display period in the embodiment of FIG. In FIG. 4, the same numbers as those in FIG. 1 represent the same signals, and 401 is an AND for the first and second periods in the non-display period.
The switch is controlled to be opened, and 402 is the first gate with NAND, 403 and 404 are the second gate with the inverter and NOR, 405 is the P-MOSFET used as the first switch, 406 is an N-MOSFET used as a second switch, 406 and 407 form a smoothing circuit with a resistor and a capacitor, and 408 and 409 are signals that are at a low level in the vertical blanking interval and the horizontal blanking interval, respectively. At this time, the outputs of the NAND 402 and the NOR 404 become high level and low level, respectively.
This corresponds to the case where the OSFET and the N-MOSFET are non-conductive and both the first and second switches in FIG. 1 are open. In the dark and underflowed display portion, the outputs 102 and 103 of the lowest and highest comparators of the A / D converter of this circuit are both at high level, so that the outputs of NAND 402 and NOR 404 are both at low level and P -MOSFET 405 conducts, smoothing circuit and VD
D connects. On the other hand, when it is bright and overflows, the outputs 102 and 103 of the lowest and highest comparators of the A / D converter are both at low level and N-
The MOSFET becomes conductive. Further, when neither underflow nor overflow occurs, the outputs 102 and 103 of the lowest and highest comparators of the A / D converter are low level and high level, respectively.
Both the FET and the P-MOSFET are non-conductive.

FIG. 5 shows A / A as the first and second luminance signal level detectors.
It is a circuit diagram which shows the example of the other circuit at the time of using the quantized output of a D converter. In FIG. 5, 501 is Noah,
502 is Nando, 503, 504, 505, 506 is 4
Bit A / D converter output, and if underflow, A / D converter quantized outputs 503 to 506
Are all low level, so Nand 502 and Noah 50
Both outputs of 1 are high level. On the other hand, in the case of overflow, the quantized outputs 503 to 5 of the A / D converter
All 06 are high level, Nand 502 and Noah 50
The outputs of 1 are both at the D-level. Further, when neither underflow nor overflow occurs, the outputs of NAND 502 and NOR 501 become high level and low level, respectively. Therefore, the outputs 102 and 103 of the lowest and highest comparators of the A / D converter in FIG. Do the same as.

The first and second switches may be bipolar transistors, and the present invention can be applied to a CRT display type television. Further, the operating periods of the first and second switches may be set at intervals of several H in order to further reduce the power consumption.

〔The invention's effect〕

As will be apparent from the above description, according to the present invention, except for the capacitor of the auto pedestal level clamp circuit, I
Since it is easy to make C, the cost of parts can be reduced and the size can be reduced.

Further, since the pedestal level is determined by feeding back the output of the luminance signal level detector such as the A / D converter, a high quality screen can be obtained without adjustment, and the adjustment cost can be reduced. The versatility is improved because there are almost no constraints on the amplitude.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional auto pedestal level clamp circuit, FIG. 3 shows a conventional technique, and FIG. 3 (A) is a composite video signal. Figure 3 (B)
Is a pedestal level clamp pulse, FIG. 3 (C) is a waveform diagram of the opening and closing timing of the pedestal level clamp switch, and FIG. 4 is the first and second gates, the switch and the smoothing circuit of the embodiment of FIG. FIG. 5 is a circuit diagram showing an example of a control circuit for the operation of the non-display period, and FIG. circuit diagram. 101 ... Luminance signal period signal, 102 ... Lowest comparator output of A / D converter, 103 ... Highest comparator output of A / D converter, 104 ... First
, 105 ... second gate, 108 ... first switch, 109 ... second switch, 110 ... smoothing circuit.

Claims (2)

[Claims] 1. An automatic pedestal level clamp circuit for applying a pedestal level adjustment voltage to a composite video signal according to the level of a luminance signal in the composite video signal during a period corresponding to the pedestal level of the composite video signal. , A brightness signal level detector that detects the level of the brightness signal, and outputs a first detection signal when the level is in the first region and a second detection signal when the level is in the second region When,
First and second switches that operate based on the first and second detection signals during the luminance signal period of the composite video signal to electrically connect the common terminal to the first voltage source and the second voltage source, respectively. And a smoothing circuit that smoothes the voltage signal from the common terminal and guides it to the pedestal level adjustment voltage applying section, and according to the level of the luminance signal, the first or second smoothing circuit is provided in a period corresponding to the pedestal level. An auto pedestal level clamp circuit characterized by applying the voltage of a voltage source to a composite video signal. 2. A luminance signal level detector uses a first detection signal when data from an A / D converter that quantizes a luminance signal is in a first bit area, and when the data is in a second bit area. Outputs a second detection signal. The automatic pedestal level clamp circuit according to claim 1, wherein