JPH0635794A - Method and device for controlling timing in computer system - Google Patents

Abstract

PURPOSE: To shorten the access time of a peripheral equipment, to sufficiently fulfill the performance, to selectively use high/low frequencies with a clock pulse as a control fundamental frequency in a bus and to make frequencies completely compatible with the bus. CONSTITUTION: When it is decided whether the reading/writing logging operation of respective peripheral eqiupments are executed by high speed or low speed clock pulse based on the setting of the inner numeric values of some accumulation devices 5, 11 and 13 which can execute programming, and a reading/writing operation is started, a device for executing reading/writing is discriminated to be high speed or not, a timing control circuit at high speed or low speed is selected/started, the accumulation devices 5, 11 and 13 are especially set in accordance with a difference on different processing speeds of the respective high speed processing means, the starting/terminating timing of a control signal is decided and whole timing control can be restricted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing control method and apparatus therefor, and more particularly to a computer system which is used in a bus system of a computer and which can selectively use a bus clock signal having a different frequency according to the processing speed of a peripheral device. The present invention relates to a timing control method and its apparatus.

[0002]

2. Description of the Related Art Most of the system buses in a conventional computer of this kind are provided with a single clock pulse having a fixed frequency, and a necessary control signal is output based on the clock pulse. The frequency of the clock pulses used on this system bus is usually not very high, in order to allow peripherals of different processing speeds to share this system bus. In this way, the conventional system bus outputs the control system at only one fixed frequency, and the frequency is not high, so
The cycle time that can be executed by this system cannot be shortened significantly, and science and technology are improving day by day,
It is a great regret that this system bus is not able to exhibit its full performance due to the limitation of operating frequency in an era when the processing speed of peripheral devices is also making a leap forward. In recent years, some manufacturers have applied the local bus system to enable peripheral devices and central processing units (C
PU) is connected and the control signal is output according to the operating frequency of the CPU, and it is found that the processing speed of the partial peripheral device is increased.

[0003]

However, it also has serious drawbacks. In other words, the local bus and the current system bus have conflicting control signals and processing speeds, and peripheral devices must be specially designed. Fall to. In view of such a problem of the timing control in the conventional system bus, the present invention shortens the access time of the peripheral device and sufficiently exerts its performance, and controls high / low frequency clock pulses in the bus. It is an object of the present invention to provide a timing control method and apparatus in a computer system which can be selectively used as a fundamental frequency and which is completely compatible with a bus.

[0004]

In order to achieve the above object, according to the present invention, when a read / write operation is started, it is first determined whether the reading or writing device is a high speed processing means or a low speed processing means, If it is a low-speed processing means, the conventional timing control method is used to perform the timing control of the low-speed means at a low job fundamental frequency, and if it is a high-speed processing means, a high frequency clock pulse is used as the job fundamental frequency.
Performs timing control on the high-speed processing means, selectively activates high-speed processing or low-speed processing timing control by different trigger methods, and further responds to the difference in processing speed of each high-speed processing means. A timing control method in a computer in which the activation and termination of a control signal is determined by performing some special settings and the overall timing control operation is performed. Furthermore, the reading or writing device is a high-speed processing means. The timing control method in the computer according to the preceding paragraph, which is configured to determine whether there is a high-speed processing means or a low-speed processing means by utilizing the different addresses of the decoded peripheral devices. In order to control different processing speeds of the processing means, delay control or waiting control method is used. The timing control method in the computer according to the first item, which enables the timing control command signal to start and end normally and completes the entire timing control operation, and further outputs the stator signal and the address signal. CPU to
And a decoder for decoding the status signal and the address signal to determine whether the processing means used for the read / write operation is high speed or low speed, and the result processing means determined by the decoder is low speed. , A low-speed processing means control signal device which outputs an impulse signal output from this decoder to enable its activation, and whose job fundamental frequency is a low-frequency clock pulse, and which outputs a timing control signal of the low-speed processing means. Is a peripheral device which is a timing control device in a computer and which determines the internal numerical value according to the address decoded by each of the high-speed processing means and the area occupied by this address and executes the read / write operation, respectively. A program that determines whether it is a low-speed processing means Is a timing control device in a computer according to the fourth item, further comprising a high speed means processing area accumulating device capable of converting into high speed processing means, and each high speed processing means corresponding to the re-processing speed of each high speed processing means. Each has a sufficient decoding time, and a programmable delay control for accurately regulating the activation time of the control signal by setting a large number of different delay times for the processing speed of each high-speed processing means. The timing control device in the computer according to the fourth or fifth aspect further comprising an accumulating device, wherein the waiting control for extending the control signal is performed according to the difference in the processing speed of the high-speed processing means. The computer according to the sixth paragraph, further comprising a programmable standby control storage device for accurately regulating the end time of the control signal. In order to determine whether the peripheral device to be read and written is a high-speed processing means or a low-speed processing, and to set the start and end timings of the control signal. Of the switching means when the switches are activated, and the switching values are programmable when the switches are activated, the programmable area storage device, the programmable delay control storage device, and the programmable waiting time. The timing control device in the computer according to the seventh item configured to be written in each register of the control storage device, and the peripheral device to be read / written is a high speed processing means or a low speed processing. To determine whether or not, and to set the timing of starting and ending the control signal,
The numerical value determined by using software is logged into a static constant-speed call storage device that can be backed up, and when started, the numerical value logged in the static constant-speed call storage device is passed through software, and the programmable high-speed means processing area The timing control device in a computer according to the seventh item in the data storage device, the programmable delay control storage device, and the programmable standby control storage device.

[0005]

According to the present invention configured as described above, from the concept of coexisting high-speed processing and low-speed processing, a CPU that outputs a status signal and an address signal when a read / write operation starts is provided, and the status signal and the address signal are decoded. Then, a decoder for determining whether the reading or writing device is a high-speed processing means or a low-speed processing means is provided. Is a low-frequency clock pulse and is provided with a low-speed processing means signal generator for outputting timing control of the low-speed processing means, and if it is determined that the high-speed processing means,
For the timing control, since the job fundamental frequency has a high-speed processing means control timing signal generator that outputs the timing control signal of the high-speed processing means with a high-frequency clock pulse, the high-low speed clock pulse is controlled. It is possible to select and use as the above, to achieve the entire timing control operation, to shorten the access time of the peripheral device, and to exhibit the respective performances. A programmable high-speed processing area storage device, a delay control storage device, and a standby control storage device are appropriately provided to determine whether the reading or writing device is a high-speed processing device or a low-speed processing device. It is possible to make a determination by utilizing the fact that the decoded respective addresses of the peripheral devices are different, or it is possible to accurately regulate the start / end time of the control signal. In addition, in order to determine the timing of starting and ending the control signal, attach switches at appropriate places in the peripheral hardware, and determine the switching value when these switches are activated, or the value determined using software. To a static constant velocity call storage device that can be backed up, and the numerical value logged to this static constant velocity call storage device via software when activated is the programmable high-speed processing area storage device and programmable This can be done by writing to the respective registers of the possible delay control storage device and the programmable standby control storage device.

[0006]

Embodiments of the present invention will be described in detail below with reference to the drawings. First, a description will be given of the timing control method in the computer system of the present invention. By the way, the conventional computer timing control system has a basic frequency controlled by only one low-frequency clock pulse, and the peripheral device performs low-speed timing control at low speed and high-speed processing at low frequency. Therefore, due to a part of the peripheral device for low-speed processing, the peripheral device for high-speed processing cannot take advantage of the excellent speed characteristic, and the read / write operation of the entire system is slow. On the other hand, in the computer timing control method according to the present invention, from the idea of coexistence of high speed and low speed, the timing control circuit device of the conventional example controls the timing of the low speed processing means to newly add a high frequency clock pulse input timing control circuit. When the read / write operation is started by controlling the timing of the high-speed processing means by providing the device, first, the attribute of whether the read or write device is the high-speed processing or the low-speed processing is determined, and the high-speed processing is selectively performed. The timing control circuit device for high-speed processing or low-speed processing is started, and at the same time, due to the difference in processing speed of each high-speed processing means, the start and end of the control signal are determined by a special setting with a slight difference, and the overall timing control is performed. It completes the action.

FIG. 1 is a block diagram showing the circuit configuration of an embodiment of the present invention. That is, FIG. 1 is a block diagram showing the configuration of an electric circuit relating to the timing control method and apparatus in the computer system of the present invention. Figure 1
As shown in FIG. 3, when the CPU 1 starts the read / write operation, three kinds of signals, that is, a status signal (Status Signa
l), and an address signal (Address Signal) and a data signal (Data Signal) are output to notify the peripheral control circuit, of which the status signal is the type of this read / write operation, for example, read or write, or its target. Is a memory unit or I / O Port
Etc. is displayed and the peripheral control circuit is executed to execute the reading operation. Then, this address signal notifies the peripheral control circuit of the address location of the portion currently read and written, and this peripheral control circuit performs decoding based on the status signal and address signal to determine the target of this read and write. The control signal is output. Also, in the case of a read operation, the CPU 1 reads the required result from this online data signal, and conversely, in the case of a write operation, the CPU 1 inputs this online data signal of the content to be written, The peripheral device reads its contents from this data signal. CPU
The status signal and the address signal output from 1 are sent to the decoder 3, and there is a storage device 5 capable of programming a high-speed processing area. The operation of the storage device 5 provides one set or one or more sets of registers. This high-speed processing area is defined, and the signals contained in each register include a status signal, a start address, an end address and an available signal, and the contents of this status signal are the same as the definition of the status signal of CPU1. , The number of bits that it occupies depends on the difference of the CPU 1, and the action is notified to the decoder 3,
It makes it possible to determine which kind of read / write belongs to the high-speed processing means. The operation of the start address and the end address both determine the area of the high-speed means, and the number of bits thereof also differs depending on the type of the CPU 1, and when the user wants to determine the area, there is not only one set of high-speed processing means. Can define the processing area of different fast processing means of each set.

FIG. 2 shows a high speed processing area confirmation display diagram of the timing control method and apparatus in the computer system of the present invention. The shaded area in FIG. 2 is the address area in which the high speed processing means is confirmed. As can be seen from the figure, three high-speed processing areas are defined by three sets of registers, and it can be seen that different numbers of registers are arranged depending on the number of high-speed processing means. The decoder 3 processes the status signal and the address signal sent from the CPU 1 and the signal sent from the high-speed processing storage device 5, respectively, to obtain the current CPU.
It is determined whether one signal corresponds to the multiple sets of high-speed processing areas sent from the storage device 5, and if any one of the plural area sets defined in the storage device 5 is matched. For example, an impulse is sent from the decoder 3 to the high speed processing means control signal generator 7, and an area signal is output to determine which high speed processing means is used for reading and writing, and which set of high speed processing means. If it does not coincide with the definite area, the impulse is further output to the low-speed processing means control signal generator 9 (that is, the control signal generator of the conventional example) to generate the read / write operation control signal of the low-speed processing means. There are two signals input to the low speed processing means control signal generator 9, one of which is output from the decoder 3 to the low speed processing means. In down pulse signals, another ready signal resulting from other peripheral devices (READY Signal)
This impulse signal can activate the low-speed processing means control signal generator 9, and the control signal output by the low-speed processing means control signal generator 9 by the ready signal according to the processing speed of the low-speed processing means. On the other hand, the operation and control process of the entire circuit in the reading and writing of the low-speed processing means are both performed with the low-frequency clock pulse CK _L as the time reference.

There are four kinds of input signals to the high speed processing means control signal generator 7, one of which is an impulse signal and a zone signal sent from the decoder 3 and the other of which is a ready signal transmitted from a peripheral device. The third is a delay signal (DELAY Signal) output from the programmable delay control storage device 11, and the fourth is a wait signal (WAIT Signal) output from the standby control storage device 13. When the high-speed processing means control signal generator 7 is activated by the impulse signal output from the decoder 3, first, another area signal output from the decoder 3 determines the attribute of the high-speed processing means, and the determination is made. According to the result, the delay control storage device 11 outputs a delay signal corresponding to the high speed processing means to control the delay time, and the purpose thereof is that the high speed processing means control signal generating device 7 operates the CPU 1. Since the clock pulse [high-frequency clock CK _H ] is used as a reference, the frequency is considerably high, and the delay signal is used to provide sufficient decoding time to the peripheral high-speed processing means. Then, the peripheral high-speed processing means finishes decoding, and it is understood that the next read / write operation is executed by it, and after the preparation operation is completed, the control signal is output to it. However,
In order to adapt to the different processing speeds of each high-speed processing means, the duration of the control signal must always be able to be extended in a timely manner, and there are two factors that determine the length of the control signal. One is a ready signal output from the peripheral device, the other is a standby signal output from the standby control storage device 13, and the control signal output from the high-speed processing means control signal generator 7 is The process is completed only after both the ready signal and the standby signal satisfy the conditions.

This stand-by signal is then the setting made for the fastest operation of the peripheral device and therefore must be supplemented by and controlled by the ready signal, which is signaled by the peripheral device. Output after the read / write operation is completed, and at the same time, see the setting of the wait (WAIT) state for each high-speed processing means in the standby control storage device 13, and then perform an accurate world write operation in this bus cycle. You can The above three storage devices 5, 11 and 13 are provided with N sets of registers according to the number N of the high speed processing means in the system to be used so as to fulfill the above operation method. The decision conditions are as follows. (1) The length of one work cycle time, which is the time reference for all control circuits of the high-speed processing means, is determined by the recycling length of the clock pulse of the CPU 1. (2) The register contents in the high-speed processing storage device 5 are set based on the decode area and address of the peripheral high-speed processing means. (3) The register contents in the delay control storage device 11 are set based on the time required for decoding by the peripheral high-speed processing means. (4) The register contents in the standby control storage device 13 are set based on the read / write operation time required by the peripheral high-speed processing means. There are two types of methods to set the values determined in the above register in the register.By attaching switches at appropriate places in the hardware and using these switches to set the switching value. Read by register and set. Logging the numerical value determined using software to the static constant-speed call storage device (SRAM) that can be backed up (Loggi
ng), the determined value is not lost even if the hunting is performed, and when the hunting is started, the numerical value logged in the static constant-speed call storage device is written and set in each register via software.

[0011]

The present invention constructed as described above has the following features.
As described below 1. 1. The read / write operations of the high-speed processing means and the low-speed processing means can be processed separately to significantly reduce the access time. The special effect that each high-speed processing means has a special setting that is slightly different from each other in terms of the difference in processing speed, so it is possible to fully exhibit the excellent characteristics in the processing speed of the high-speed processing means. Can bring.

[Brief description of drawings]

FIG. 1 is a block diagram of an electrical configuration relating to a timing control method and its apparatus in a computer system as an embodiment of the present invention.

FIG. 2 is a diagram for confirming a high speed processing means area of the timing control method and apparatus in the computer system of the embodiment of FIG.

[Explanation of symbols]

 1 CPU (Central Processing Unit) 3 Decoder 5 High Speed Processing Means Processing Area Storage 7 High Speed Processing Means Control Signal Generator 9 Low Speed Processing Means Control Signal Generator 11 Delay Control Storage 13 Wait Control Storage

Claims (9)

[Claims] 1. When a read / write operation is started, it is first determined whether the read or write device is a high speed processing means or a low speed processing means. Performs timing control of the low speed means at the job fundamental frequency, and if it is the high speed processing means, performs the timing control to the high speed processing means by using the high frequency clock pulse as the job fundamental frequency, and performs high speed processing or low speed processing by different trigger methods. The timing control is selectively activated, and in response to the difference in the processing speed of each high-speed processing means, a slight special setting is applied to each to determine the start and end of the control signal. A timing control method in a computer, characterized by performing a timing control operation. 2. A device for determining whether the device for reading or writing is a high-speed processing device or a low-speed processing device by utilizing the different addresses of the decoded peripheral devices. Item 2. A timing control method for a computer according to Item 1. 3. A timing control command signal can be normally started and ended by a delay control or a waiting control as a method for controlling different processing speeds of the respective high-speed processing means, and the overall timing is controlled. The timing control method for a computer according to claim 1, wherein the control operation is completed. 4. A CPU (1) for outputting a stator signal and an address signal, and decoding the stator signal and the address signal to determine whether the processing means used for the read / write operation is high speed or low speed. If the decoder (3) for performing the operation and the result processing means determined by the decoder (3) have a low speed, the impulse signal output from the decoder (3) is used as the enable signal for the activation, and the basic frequency of the job. Is a low frequency clock pulse, and when the processing means discriminated by the low speed processing means control signal device (9) for outputting the timing control signal of the low speed processing means and the decoder (3) is high speed, this decoder (3) It receives the impulse signal output from it as an enable signal for its start, and its job fundamental frequency is high frequency. Rock is a pulse, high-speed processing means control signal device (7) and the timing control device in a computer, characterized in that it consists of outputting the timing control signal of the high-speed processing means. 5. A peripheral device which determines an internal numerical value according to an address decoded by each of the high-speed processing means and an area occupied by the address and is a high-speed processing means or a low-speed processing means for executing a read / write operation. Programmable high-speed means for discriminating between processing area storage device (5)
The timing control device in a computer according to claim 4, further comprising: 6. Corresponding to the difference in the processing speed of each high-speed processing means, each high-speed processing means has a sufficient decoding time, and a plurality of sets are set for the processing speed of each high-speed processing means. Set different delay times,
6. A timing control device for a computer according to claim 4 or 5, further comprising a programmable delay control storage device (11) for precisely controlling the activation time of the control signal. 7. A programmable waiting control storage device for controlling waiting time for extension of a control signal in accordance with a difference in processing speed of the respective high-speed processing means, and accurately regulating the end time of the control signal. The timing control device in a computer according to claim 6, further comprising: 13). 8. The hardware is used at appropriate places to determine whether the peripheral device which is to perform the read / write operation is a high-speed processing means or a low-speed processing, and sets the timing of starting and ending the control signal. A high-speed processing area storage device in which switches are individually mounted and the switching values can be programmed when the switches are activated.
(5) and programmable delay control storage device (11)
8. A timing control device in a computer according to claim 7, wherein each of the programmable standby control storage devices (13) is written in a register. 9. A determination is made as to whether the peripheral device to be read or written is a high speed processing means or a low speed processing,
In addition, in order to set the start and end timings of control signals, the values determined by software are logged in the static constant-speed call storage device (SRAM) that can be backed up, and when started, the static constant-speed call storage device ( The numerical value logged in (SRAM) is passed through software, and the programmable high-speed processing area storage device (5), programmable delay control storage device (11) and programmable wait control storage device (13) 8. The timing control device for a computer according to claim 7, wherein each of the registers is written in a register.