JPH02176959A - Bus selecting circuit - Google Patents

Abstract

PURPOSE:To cope with various kinds of environment by a common microprocessor by providing a means which share a signal terminal and inputs and outputs an address signal an data on a time-division basis and a means which shorten word length and inputs and outputs the address signal and data at the same time. CONSTITUTION:The circuit is equipped with a flip-flop 7 which is set by EXU2 to level 1 for a separate bus control system and reset to level 0 for a multiplex bus control system, a two-input AND gate 10 which inputs an SB/MB signal 8 and an HB/LB signal 9 and controls a selector 13, and a two-input NOR gate 11 which inputs the SB/MB signal 8 and an address control signal 12 and controls a selector 14 and the bus size of the data signal is varied without increasing the number of terminals to realize the multiplex bus control system and separate bus control system by one microprocessor. Consequently, it is advantageous to compose this circuit of an integrated circuit and the constitution of peripheral equipment is freely selected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus selection circuit, and more particularly to a bus selection circuit that controls a bus of a microprocessor.

[Conventional technology]

Conventionally, in a microprocessor that is program-controlled by instruction codes and data stored in an external storage device, some or all signal terminals of a multi-bit address signal specifying a program storage area of the external storage device are used. In conventional bus selection circuits that share signal terminals for inputting and outputting instruction codes and data, and inputting and outputting address signals and instruction codes and data in a time-sharing manner, the bus for signal terminals that input and output instruction codes and data The bit width (bus size) of the bus is selected by a given instruction or at the time of integrated circuit fabrication.

For example, in conventional microprocessors, it was possible to switch the data signal bus size from 8 bits to 16 bits, but the bus control method was a multiplex bus that shared the data signal terminal and address signal terminal and was used for time division. The control method is fixed.

[Problem to be solved by the invention]

In the microprocessor that is program-controlled by instruction codes and data stored in the external storage device mentioned above,
- The basic bit length of this program code is fixed for boat fishing, and the code that specifies commands and data is a multiple of this basic unit. Therefore, bits corresponding to data and execution instruction codes are input/output in a time-division manner using input/output terminals having the number of bits in this basic unit (bus size).

The microprocessor also outputs address information specifying the program storage area of the external storage device, and the output terminal of this address information is also used as the input/output terminal for the instructions and data, and a bus is used to output the information in a time-sharing manner. A control method (multiplex bus control method) and a bus control method with a dedicated address output terminal (separate bus control method)
There is.

The basic bit length of data, the so-called bus size, and the multiplex bus control method or separate bus control method are selected depending on the speed of instruction processing and the scale of the system that uses a microprocessor. There is also a limit to the number of external terminals in the microprocessor that is configured, and the bus size and bus control method are handled individually based on these requirements.

However, the peripheral devices that form the external environment surrounding the microprocessor also closely correspond to the bus size and bus control method, which has the drawback that it is difficult to apply a common microprocessor to various environments.

An object of the present invention is to provide a bus selection circuit that can handle both the multiplex bus control method and the separate bus control method using a single microprocessor.

[Means to solve the problem]

The bus selection circuit of the present invention includes a bus control unit and an execute unit, and is a bus selection circuit for a microprocessor that is program-controlled by instruction codes and data stored in an external storage device. sharing some or all signal terminals of a multi-bit address signal specifying an area and a signal terminal for inputting and outputting the instruction code and data;
means for time-divisionally inputting and outputting the address signal and the instruction code and data, reducing the word length of the number of signal terminals for inputting and outputting the instruction code and data, and separating the signal terminals for the address signal; The bus control unit includes means for simultaneously inputting and outputting an address signal and the instruction code or data, and both means are configured to be driven by a control signal from the execute unit.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a bus selection circuit diagram of a microprocessor showing an embodiment of the present invention.

As shown in Figure 1, the microprocessor is a bus control unit (hereinafter referred to as BCU) that controls data transmission and reception.
It consists of an Execute Unit (hereinafter referred to as EXU) 2 that controls the execution of instructions and calculations, etc., and writes data to an external storage device (not shown).
Read stored data. The bus size of the data signal inside the BCUI of this microprocessor is 16 bits wide, and the bus size of the internal address signal is 20 bits wide.

In the BCUI of such a microprocessor, bus 3
is a data bus for the lower 8 bits (Do to D7), bus 4 is a data bus for the upper 8 bits (D8 to D, 15), bus is an address bus for the lower 8 bits (AO to A7), and bus 6
is an address bus for upper 12 bits (A8 to A19), and these buses 3 to 6 are both connected to EXU2. Further, FF7 is a flip-flop which is set by EXU2 to become a level in the case of the separate bus control method, and reset to become O level in the case of the multiplex bus control method. The output signal (SB/MB) 8 of this flip-flop 7 is used for separate bus control in Lebel.
The 0 level indicates multiplex bus control, and is a signal for switching between the separate bus control method and the multiplex control method. Also, the HB/LB signal 9 is EX
This signal is output from U2 and is necessary for separate bus control. In the case of Lebel, it indicates the case where data is input/output from the external terminal of the microprocessor to bus 4. If it is at 0 level, the microprocessor is connected to bus 3. The case where data is input/output from an external terminal is shown. The two-man-powered AND gate 10 inputs the SB/MB signal 8 and the HB/LB signal 9 and controls the selector 13. This selector 13 connects the bus (D8-D15) 4 to the data signal terminal 16 when the control input is level 0, and when the control input is at level 0,
Bus (Do-D7) 3 is connected to data signal terminal DA16. On the other hand, the two-man power NOR gate 11 inputs the SB/MB signal 8 and the address strobe signal (ASTB) 12, and controls the selector 14 by its output. This selector 14 selects the bus (D8 to D1) when the control input is level.
5) 4 is connected to the AD terminal 17, and when the control input is at O level, the bus (AO to A7) 5 is connected to the AD terminal 17. In particular, the AD dual-purpose terminal 17 has an 8-bit width, and outputs a lower address signal when using the separate bus control method, and outputs a lower address signal and an upper data signal in a time-sharing manner when using the multiplex bus control method. .

The above-mentioned ASTB signal 12 is supplied from the EXU 2 and is a necessary signal in the case of the multiplex bus control method in which it is sent from the ASTB terminal 15, which is an external terminal of the microprocessor, to an external storage device. When this ASTB signal 12 is a level, it indicates the timing at which an address signal is output to the AD terminal 17, and when it is at 0 level, it indicates the timing at which a data signal is output to the AD terminal 17. Furthermore, the aforementioned address signal terminal 18 is also an external terminal of the microprocessor and is connected to the bus (A8-A19) 6.

The operation when switching to each of the above-mentioned control methods will be explained below.

First, the operation when switching to the separate bus control method will be described.

In this case, it is assumed that an external device such as a memory device connected to the microprocessor has an 8-bit width data signal for one address indicated by the address signal.

When switching to the separate bus control method, the EXU 2 outputs a signal for setting the flip-flop 7 in response to a command or the like. The set flip-flop 7 causes the SB/MB signal 8 to become a level, indicating separate bus control.

FIG. 2 is a timing diagram when the bus selection circuit shown in FIG. 1 is switched to such a separate bus control method.

As shown in FIG. 2, T1 to T4 indicate the timing of clock A for synchronizing the microprocessor, and these four timings constitute one bus cycle. At this time, when the HB/LB signal 9 is level, the above-mentioned EXU 2 also outputs the HB/L signal via the bus (D8-D15) 4.
When the B signal 9 is at the 0 level, the data signal B is inputted via the bus (Do-D7) 3 during the timing T3,
- The data signal C is output from timing T1 to T4, and the address signal is output from the bus (AO
-A7)5 and bus (A8-A19)6 between timings T1 and T4.

First, since the output of the gate 11 is at 0 level due to the SB/MB signal 8, the AD terminal 17 is connected to the bus (AO-A7) 5.
The address signals for the lower 8 bits, ■, are output.

Further, the address signal indicates the output timing of the address signal from the AD dual-purpose terminal 17 and the address signal terminal 18, and from timing T1 to timing T4, the bus (AO-A7) 5 and the bus (A8-A19) 6 to 2
A 0-bit width address signal is output, and the address signal is directly output to the AD terminal 17 and the address signal terminal 18.

On the other hand, when inputting/outputting the lower 8 bits of the data signal, the EXU 2 sets the HB/LB signal 9 to the o level. As a result, AND gate 1o outputs 0 level, so
The selector 13 connects the bus (Do-D7) 3 to the data signal terminal 16. Therefore, data at the address specified by the address signal from the external device connected to the data signal terminal 16 is input/output to/from the bus (DO-D7) 3.

That is, data B indicates the timing of data input from the data signal terminal 16, and the data signal is input at timing T3. Furthermore, data C indicates the data output timing from the data signal terminal 16, and the data signal is output between timings T1 and T4.

In this manner, when one bus cycle in the separate bus control method is completed, the upper eight bits of the data signal are input/output in the next bus cycle. E on next bus cycle
XU2 is HB/L If B signal 9 is set to SB/L,
Since MB signal 8 is in rubel, this causes AN
The D gate 10 outputs a level, and the selector 13 connects the bus (D8-D15) 4 to the data signal terminal 16. That is, a data signal at an address specified by an address signal from an external device connected to the data signal terminal 16 is input/output to/from the bus (D8-D15) 4. At this time, EXU 2 must output an address signal so that the upper 8 bits of data specify the address.

As described above, by repeating the bus cycle twice, a 16-bit wide data signal can be input to the microprocessor.

Next, the operation when the microprocessor control method is switched to the multiplex bus control method will be described.

In this case, it is assumed that the external device connected to the microprocessor has a 16-bit width data signal for one address indicated by the address signal.

When switching to this multiplex bus control method, the EXU 2 outputs a signal for resetting the flip-flop 7 in response to a command or the like.

By the reset flip-flop 7, SB/MB
Since signal 8 is at the 0 level, multiplex bus control is indicated.

FIG. 3 is a timing diagram when the bus selection circuit shown in FIG. 1 is switched to such a multiplex bus control system.

As shown in FIG. 3, periods Tl, T2 . T3 and T4 indicate the timing of clock A that synchronizes the microprocessor, and these four timings form one bus cycle. EXU2 connects bus (Do-D7)3 and bus (D
8-D15) 4, the data signal is input during timing T3, and the data signal is output at timing T3.
On the other hand, the output of the address signal is performed between timing T1 and T4 via bus (AO-A7) 5 and bus (A8-A19) 6.

Further, E indicates the timing of the signal of the AD terminal 17 at the time of data input, F indicates the timing of the signal of the AD terminal 17 at the time of data output, and the signal G indicates the ASTB signal 1.
2 and becomes a rubel at timing T1. Also, H
inputs the lower 8 bits of the data signal at timing T3 at the timing of the signal at the data signal terminal 16 during data input. (3) is the timing of the signal at the data signal terminal 16 during data output, and the lower 8 bits of the data signal are output from timing T1 to timing T4. J outputs the upper 12 bits of the address signal from timing T1 to T4 at the timing of the signal at the address signal terminal 18.

When the ASTB signal 12 is set to level at timing TI, the NOR gate 11 outputs the O level, so
The AD/AD terminal 17 is connected to the bus (AO-A7) 5. Therefore, the lower 8 of the address signal is connected to the AD terminal 17.
A bit signal is output.

Next, from timing T2 to T4, ASTB signal 1
2 is at the 0 level, and the SB/MB signal 8 is also at the 0 level, so the NOR gate 11 becomes a level, and the AD dual-purpose terminal 17 is connected to the bus (D8-D15) 4. The input of the upper 8 bits of the data signal is performed during timing T3, and the output of the upper 8 bits of the data signal is performed at timing T3.
2 to T4.

An external device connected to the microprocessor can determine whether the signal output to the AD terminal 17 is an address signal or a data signal from the signal at the ASTB terminal 15.

Also, since the SB/MB signal 8 is at 0 level, the AND
The output of gate 10 becomes 0 level, and the bus (Do-D7
) 3 is connected to the data signal terminal 16.

As described above, by switching the AD terminal 17 between the address signal and the data signal using the ASTB signal 12,
Data signal input/output and address signal output can be performed using multiplex control method.

Although one embodiment of the present invention has been described above, it is also possible to remove the flip roller 113 and select whether to set the signal SB/MB14 to a level or a 0 level at the time of manufacturing an integrated circuit.

〔Effect of the invention〕

As explained above, the bus selection circuit of the present invention has the advantage that it is possible to change the data signal bus size without increasing the number of terminals, and to realize a multiplex bus control method and a separate bus control method with a single microprocessor. There is.

That is, since the present invention does not increase the number of terminals, it is advantageous to configure it with an integrated circuit, and since the bus control method can be easily selected, the configuration of peripheral devices can be freely selected.

[Brief explanation of the drawing]

FIG. 1 is a bus selection circuit diagram of a microprocessor showing an embodiment of the present invention, FIG. 2 is a timing diagram when the bus selection circuit shown in FIG. This is a timing diagram when the bus selection circuit shown in Figure 1 is configured as a multiplex bus control system.
・Execute unit (EXU), 3...lower bit data (Do-D7) bus, 4...upper bit data (D8-D15) bus, 5...lower bit address (AO-A7) bus, 6... Upper bit address (
A8-A19) Bus, 7...Flip-flop, 8.
・Separate bus/multiplex bus switching (
SB/MB) signal, 9... Upper bit lower and lower data switching (HB/LB) signal, 10... 2 manual AN
D gate, 11...2-man power NOR gate, 12...
Address strobe (ASTB) signal, 13.14...
・Selector, 15...Address strobe (ASTB
) terminal, 16... data signal terminal, 17... address/data signal (AD) combined terminal, 18... address signal (A8-A19) terminal.

Claims (1)

[Claims] In a bus selection circuit of a microprocessor that has a bus control unit and an execute unit and is program-controlled by instruction codes and data stored in an external storage device, a multi-bit address that specifies a program storage area of the external storage device Means for inputting and outputting the address signal and the instruction code and data in a time-sharing manner by sharing a signal terminal for inputting and outputting the instruction code and data with some or all of the signal terminals of the signal; The bus controller includes a means for simultaneously inputting and outputting the address signal and the instruction code and data by reducing the word length of the number of signal terminals for inputting and outputting the instruction code and data, and separating the signal terminals for the address signal. 1. A bus selection circuit comprising a bus selection circuit in a unit and driving both of these means by a control signal from the execution unit.