JPH0131218B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field The present invention relates to a microprogram-controlled central processing unit having a memory paging function, and particularly to control of an address register that specifies addresses for a memory system.

(b) Prior Art Figure 1 is a block diagram showing a conventional microprogram-controlled central processing unit having a memory paging function, and 1 and 2 are for a memory system 3 in which programs, data, etc. are stored. These are an upper address register and a lower address register that specify addresses. Upper address register 1 specifies a page for memory system 3, and lower address register 2 specifies a page specified by upper address register 1 of memory system 3. Specify the address within the page. Also, 4
is an instruction register from which instructions are fetched from the memory system 3 via the bus driver 5, 6 is a group of general-purpose registers such as an accumulator and a program counter, 7 is an arithmetic unit (ALU), and 8 generates fixed data of "all 0s". A fixed data generation circuit 9 includes a microprogram memory 10 such as a ROM that stores microprograms, and analyzes the instructions fetched into the instruction register 4, and provides various controls to each part in synchronization with the system clock CLK. A computer control unit (CCU) is a control unit that generates signals.

Next, the operation will be explained with reference to the timing chart shown in FIG.

First, when the central processing unit finishes executing one instruction and starts executing the next instruction, the memory system 3
outputs commands to the bus driver 5 according to address information from the upper and lower address registers 1 and 2. As shown in Figure 2, this instruction includes an instruction code, a page designation bit Z/C indicating whether the instruction accesses the zero page or the current page, and a lower address for the memory system 3. It consists of. When the command is output, the computer control unit 9 sets both the enable signal DBEN and the signal DBDIR that determines the direction of the bus driver 5 to "L" (FIG. 4b), so that the command is transmitted from the memory system 3 to the bus driver 5. The signal is sent to the bus line BL via the bus line BL (Figure 4c). Then, the instruction is fetched into the instruction register 4 when the fetch signal IL rises, and the instruction is written into the work register of the general-purpose register group 6 when the write signal RW rises (FIG. 4, D and H). When an instruction is fetched into the instruction register 4, the computer control unit 9 takes this instruction and begins parsing it. On the other hand, the instruction written to the work register is taken into the arithmetic unit 7, passes through here, and is again output to the bus line BL by the output enable signal OEY (see Fig. 4,
to).

Here, if there is an instruction to access the current page of the memory system 3, the computer control unit 9 sends an analysis result signal.
OE is kept at "H", so fixed data is not output from the fixed data generation circuit 8, and the gate 11 is opened. However, since the computer control unit 9 does not generate the clock pulse CPM, the contents of the upper address register 1 do not change, and only the lower address of the instruction is taken into the lower address register 2 by the clock pulse CPL. Therefore, upper and lower address register 1
As the output of and 2, only the lower address will be updated.

On the other hand, if the instruction is an instruction to access the zero page of the memory system 3, as a result of analysis, the computer control unit 9 sets the signal OE to "L" and generates a clock pulse CPU, so that the gate 11 is closed. Fixed data "all 0" is output, this data is taken into the upper address register 1, and the upper address register 1 is cleared. Also, the lower address of the instruction is taken into the lower address register 2 in the same way as the current page, and therefore the outputs of the upper and lower address registers 1 and 2 are both updated.

As described above, in conventional central processing units, the instruction register fetches the instruction, and the computer control unit determines whether the instruction accesses the zero page or the current page. In this case, the address is not determined, and therefore, the output of the address information to the memory system is slow, resulting in a long processing time. In particular, since the zero page of the memory system is used as a common data area by other pages, there is a problem in that a delay in processing speed in this area has a large impact on the entire system.

(c) Purpose The present invention provides a microprogram-controlled central processing unit with a memory paging function that, when an instruction is received from the memory system, reads the upper address register before the computer control unit completes the analysis of the instruction. The purpose is to achieve high-speed processing by forcibly clearing or retaining the contents, outputting address information to the memory system early and making the memory system operate efficiently. .

(d) Embodiment FIG. 3 is a block diagram showing an embodiment of a central processing unit using a microprogram control system according to the present invention, and the same components as those of the conventional example shown in FIG. 1 are given the same numbers.

As shown in FIG. 3, in the present invention, the upper address register 12 is composed of a register with a clear terminal that forcibly clears the contents when a signal is input, for example, a plurality of D flip-flops with a clear terminal CR. 13 is a computer control unit as a control section which includes a microprogram memory 14 as in FIG. In other words, at the same time as the control signals DBEN and DBDIR are output to the bus driver 5, the clear enable signal CLREN is output as shown in the timing chart of FIG. 5C.

Furthermore, in the present invention, the clear enable signal from the computer control unit 13
Input CLREN and memory system 3
The page designation signal Z/C from the page designation bit of the instruction fetched from the instruction register 4 is input from the bus line BL, and the clear enable signal is input.
When CLREN is in the specified state, the page designation signal Z/
A clear signal generating circuit 15 is provided which generates a clear signal CLR in accordance with C. In the embodiment shown in FIG. input the output signal G to the data input terminal D,
It consists of a D flip-flop 17 which inputs the system clock CLK to the clock terminal CL.

Next, the operation of this embodiment will be explained with reference to the timing chart shown in FIG.

When an instruction is output from memory system 3,
Just like the conventional example shown in FIG. 1, first, the signals DBEN and DBDIR are applied to the bus driver 5, and the command is sent to the bus line BL via the bus driver 5. However, the computer control unit 13 simultaneously receives the signals DBEN and DBDIR.
The clear enable signal CLREN is set to "L" as shown in FIG. 5C. For this reason, bus line BL
If the command sent to is a command to access the current page, the page designation signal Z/C is "H", so the output signal G of the OR gate 16 is
remains at "H" as shown by the broken line in FIG.
CLK remains at "H" as indicated by the broken line in FIG. 5E, and the upper address register 12 is not cleared but retains its contents. By the way, since the clock pulse CPL as a fetch signal to the lower address register 2 rises almost at the same time as the fetch signal IL rises, the lower address of the instruction is fetched into the lower address register 4 at the same time. Incorporated into 2.

On the other hand, when the instruction is an instruction to access the zero page, the page designation signal Z/C is "L", so the output signal G of the OR gate 16 is "L" as shown by the solid line in FIG. '', and when the system clock CLK is input to the D flip-flop 17, its output signal CLR becomes ``L'' as shown by the solid line in FIG. Therefore, the "L" clear signal CLR is input to the clear terminal CR of the upper address register 12, and the contents of the upper address register 12 are forcibly cleared. On the other hand, the lower address register 2 takes in the lower address of the instruction, just as in the case of the current page.

As described above, in this embodiment, the address information from the upper and lower address registers 12 and 2 for the memory system 3 is fetched almost simultaneously when the instruction is fetched into the instruction register 4, that is, at the computer control unit 13. It is determined and output before the analysis of the instruction is completed. As is clear from a comparison of FIGS. 4 and 5, address information is output approximately one system clock earlier than in the conventional example.

Note that there are direct commands and indirect commands, and only an address is sent from the memory system 3 after the indirect command.
The clock pulse CPM as a signal taken in from the computer control unit 13 to the upper address register 12 is output when only an address is sent following an indirect command.

By the way, when the execution of the instruction is completed, the program counter in the general-purpose register group 6 is incremented by 1 by the arithmetic unit 7, this content is taken into the upper and lower address registers 12 and 2, and the program proceeds to the next instruction.

(e) Effects The microprogram control type central processing unit according to the present invention inputs a page designation signal from the page designation bit of an instruction fetched from the memory system to the instruction register, and generates a clear signal in response to the signal. A clear signal generation circuit is provided to generate a clear signal, and this clear signal forcibly clears the upper address register or holds its contents. Therefore, it is necessary to analyze the instruction fetched into the instruction register before the memory is cleared. Compared to conventional central processing units that cannot output address information to the system, it is possible to output address information to the memory system earlier. Therefore, it is possible to operate the memory system efficiently, and high-speed processing of the entire system can be realized. In particular, it is a great advantage to be able to quickly output address information to the memory system when an instruction to access the zero page is received.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional central processing unit using a microprogram control method, FIG. 2 is a diagram showing an instruction format, and FIG. 3 is a block diagram showing an embodiment of a central processing unit using a microprogram control method according to the present invention. 4 is a timing chart for explaining the operation of the conventional example shown in FIG. 1, and FIG. 5 is a timing chart for explaining the embodiment shown in FIG. 3. Explanation of main figure numbers 1, 12... Upper address register, 2... Lower address register, 3... Memory system, 4... Instruction register, 5... Bus driver, 6... General purpose register group, 7... Arithmetic unit, 8... Fixed data generation circuit, 9, 13... Computer control unit, 10, 14...
...Micro program memory, 15...Clear signal generation circuit.

Claims (1)

[Claims] 1 Consists of an address register for specifying addresses for the memory system, an instruction register from which instructions are fetched from the memory system, and a microprogram memory, which analyzes the instructions fetched into the instruction register and processes various control signals. In a microprogram control central processing unit, the address register is an upper address register that specifies a page for the memory system;
a lower address register that specifies an address within a designated page of the memory system; and a page designation signal from a page designation bit of an instruction fetched from the memory system to the instruction register; 1. A central processing unit using a microprogram control system, characterized in that a clear signal generating circuit is provided to generate a clear signal in response to the above, and the upper address register is forcibly cleared by the clear signal.