JPH04369064A - Method and device for controlling interruption processing - Google Patents

Abstract

PURPOSE:To speed up interruption receiving processing by changing the interruption priority order of respective interruption request factors when there are many interruption requests. CONSTITUTION:This interruption processing control device processing system is constituted of a register circuit 1 for respectively recording the prescribed number of interruption request signals, a priority order judging circuit 2 consisting of a programmable logic element for determining the highest priority interruption request signal from the interruption request signals of respective registers and an interruption priority order changing signal and inputting the determined signal to a CPU, a vector forming circuit 4 for forming vector information corresponding to the interruption factor of the highest priority interruption request signal based upon an output signal from the judging circuit and inputting the formed information to the CPU, and an interruption request checking signal forming circuit 5 for converting the output signal of the vector forming circuit and clearing the contents of the register recording the highest priority interruption request signal.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to an interrupt processing control method and apparatus for requesting interrupt processing from a peripheral device to a central processing unit (CPU) of a computer, and more particularly, to The present invention relates to an interrupt processing control method and a device therefor, which speeds up interrupt acceptance processing when there are many interrupt request factors, and enables changing interrupt priorities among interrupt request factors.

0002

[Prior Art] A dedicated IC for accepting interrupt processing (for example, Signetics' SCB 68154, SCB
68155 Reference Microprocessor Data Manual When using a microprocessor data manual (Philips Electronic Components Division, Philips Japan Co., Ltd.), the number of interrupt request lines is limited to 7 or 14, and in order to handle more requests, a daisy chain is required. method was used.

Furthermore, in order to satisfy a large number of interrupt processing requests, as disclosed in Japanese Patent Publication No. 60-46748, the number of interrupt request lines is reduced to one and the interrupt cause is recorded in a register. There is an interrupt processing method in which the CPU recognizes the interrupt and then searches the register for the cause of the interrupt.

0004

[Problems to be Solved by the Invention] When requesting interrupt processing from a peripheral device to the CPU of a computer, there is a problem in that if a dedicated IC is used, the number of interrupt requests that can be accepted is limited. b. When a daisy chain method is adopted to increase the number of interrupt requests, there is a problem in that the priority order of the parts configured by the daisy chain cannot be changed.

[0005] In order to cope with the increasing number of interrupt processing requests, as in Japanese Patent Publication No. 60-46748, when using a single interrupt request line and searching for the interrupt request source using a register, the interrupt It is possible to change the priority, but since the interrupt priority must be determined by software, the problem is that it takes processing time to respond due to the number of steps, in other words, the time required to move to interrupt processing. Another problem is that it takes time to accept and process the next interrupt.

The present invention solves the above-mentioned problems, speeds up interrupt acceptance processing when there are many interrupt requests, and makes it possible to change the interrupt priority order among each interrupt request factor. An object of the present invention is to provide an interrupt processing control method and a device thereof.

[0007]

[Means for Solving the Problems] The present invention solves the above-mentioned problems, and employs the following methods and technical means. That is, (1) the method invention records each interrupt request signal in each register, and generates a programmable logic from the interrupt request signal and interrupt priority change signal recorded in each register. The device determines the current highest priority interrupt request signal and inputs it to the central processing unit,
Interrupt vector information indicating an interrupt factor of the highest priority interrupt request signal is generated and inputted to the central processing unit to request the central processing unit to process an interrupt, and then the highest priority interrupt request signal is recorded. This interrupt processing control method is characterized by erasing the contents of a register that has been previously stored.

(2) The device invention provides: (a) a register for recording each of a predetermined number of interrupt request signals; and (b) determining the highest priority interrupt request signal from the interrupt request signal and interrupt priority change signal of each register. A priority determination circuit consisting of programmable logic elements input to the central processing unit, and a
A vector generation circuit generates vector information corresponding to the interrupt factor of the highest priority interrupt request signal from the output signal of the determination circuit and inputs it to the central processing unit, and a vector generation circuit converts the output signal of the vector generation circuit to generate the highest priority interrupt. This is an interrupt processing control device characterized by comprising an interrupt request confirmation signal generation circuit that erases the contents of a register in which a request signal has been recorded.

Instead of inputting the output signal of the determination circuit to the request confirmation signal generation circuit via the vector generation circuit, it is possible to configure the output signal to be input directly to the interrupt request confirmation signal generation circuit. can. Furthermore, a pulse conversion circuit that converts the interrupt request high/low signal into a pulse is provided on the input side of each register, and the output signal of the priority determination circuit is connected to the system clock between the priority determination circuit, the central processing unit, and the vector generation circuit. A synchronization circuit may be provided to synchronize with.

0010

[Operation] Since the present invention is constructed as described above, (
1) This can be handled by configuring each register according to the number of interrupts that can be processed. That is, the number of interrupts accepted is not limited. (2) The priority order of interrupt processing can be changed.

(3) Use of a programmable logic element (not software but hardware) for priority determination
Programmable Logic Device
) (hereinafter referred to as PLD), it is possible to determine the priority order at high speed, and by incorporating logic that can change the priority order into the PLD, it becomes easy to change the interrupt priority order.

0012

[Embodiment] An embodiment of the present invention will be explained with reference to the drawings. Figure 1
FIG. 1 is a system explanatory diagram of the first embodiment of the present invention. The interrupt request pulse signal is stored in each register of the register circuit. Note that the number of registers is arbitrarily determined according to design. The register circuit transmits interrupt requests that have not yet been processed by the CPU to a priority determination circuit consisting of a PLD.

[0013] In the determination circuit, the interrupt request signal of the register,
Based on the interrupt priority change signal, it is determined whether the interrupt priority is the highest and is output, and the output signal is input to the CPU as an interrupt signal. Further, other output signals of the priority determination circuit are input to a vector generation circuit, where interrupt vector information indicating the interrupt factor of the highest interrupt signal is generated, and this vector information is input to the CPU. . The CPU performs interrupt processing based on this interrupt signal and vector information.

Further, the other output signals of the vector generation circuit are input to the interrupt request confirmation signal generation circuit, which finds the signal to be interrupted from the vector information and determines the highest priority interrupt request signal corresponding to this signal. Erase the recorded contents of the register. That is, the vector generation circuit is an encoder configured by a PLD, and sends vector information corresponding to the interrupt factor to the CPU and to the interrupt request confirmation signal generation circuit, is decoded by the interrupt request confirmation signal generation circuit, and is processed by the interrupt request confirmation signal generation circuit. The contents of the register corresponding to the interrupt factor are cleared by the signal, and the system enters a standby state for the next interrupt request.

In this way, the present invention can process a large number of generated interrupts at high speed while changing the priority order. FIG. 2 is a system explanatory diagram of a second embodiment of the present invention. In this embodiment, unlike FIG. 1, the output signal of the priority determination circuit is directly input to the interrupt request confirmation signal generation circuit without passing through the vector generation circuit. Therefore, this embodiment has the advantage that the encoder (not shown) in the configuration of FIG. 1 is unnecessary and the response speed is faster.

FIG. 3 is a system explanatory diagram of a third embodiment of the present invention, in which a pulse conversion circuit and a synchronization circuit are added to FIG. 1. In this configuration, when the interrupt request signal is not a pulse signal but a High or Low signal, this H
A pulse conversion circuit for converting high and low signals into normal pulse signals is provided, and a synchronization circuit is further provided for synchronizing the output signal of the priority determination circuit with the system clock.

This synchronization circuit is capable of converting the output signal of the priority determination circuit to an interrupt timing that can be accepted by the CPU when the output signal has a timing different from the interrupt acceptance timing of the CPU. FIG. 4 is a detailed explanatory diagram of the pulse conversion circuit, register circuit, and priority determination circuit shown in FIG. 3.

The pulse conversion circuit 14 includes the inverter circuit 1
, two D flip-flop circuits 2, an AND circuit 3, etc., and converts the interrupt request signal 11 into a normal pulse signal when it is a High or Low signal. The register circuit 15 includes a NAND circuit 4 and a JK flip-flop circuit 6, and the JK flip-flop circuit 6 serves as a register. A clear signal 5 for erasing the contents of the JK flip-flop circuit (register) 6 is input to one input side of the NAND circuit 4 .

Pulse conversion circuit 14 and register circuit 15
is provided with a predetermined expected number of interrupts determined by design. The priority order determination circuit includes a PLD 7 and an encoder 8. The PLD 7 selects the interrupt request with the highest priority from among the interrupt requests registered in the JK flip-flop circuit 6. Further, a priority change signal 10 is input to the PLD 7. The logic of the PLD 7 is prepared as many as the number of patterns whose priority order can be changed. The encoder 8 is provided to output a priority interrupt signal to the CPU. Further, the encoder 8 may be incorporated into the functions of the PLD 7.

FIG. 5 is an explanatory diagram of the synchronous circuit, and
7. This is for synchronizing the output of the encoder 8 with the system clock 16, and is composed of a multiplexer 9 and a D flip-flop circuit 2. Further, the priority change signal 10 is transmitted to the address decoder 1 as shown in FIG.
7, when a specific address is decoded, the priority order is changed via the latch 18.

[0021]

Effects of the Invention The present invention makes it possible to change the interrupt priority order among each interrupt request factor even when there are many interrupt requests, and also to speed up the interrupt acceptance processing. This has an excellent effect on improving processing efficiency.

[Brief explanation of drawings]

FIG. 1 is a system explanatory diagram of a first embodiment of the present invention.

FIG. 2 is a system explanatory diagram of a second embodiment of the present invention.

FIG. 3 is a system explanatory diagram of a third embodiment of the present invention.

FIG. 4 is a detailed explanatory diagram of a pulse conversion circuit, a register circuit, and a priority determination circuit according to the present invention.

FIG. 5 is an explanatory diagram of a synchronous circuit of the present invention.

FIG. 6 is an explanatory diagram of a priority change circuit according to the present invention.

[Explanation of symbols]

1 Inverter circuit 2 D flip-flop circuit 3 AND circuit 4 NAND circuit 5 Clear signal 6 JK flip-flop circuit 7 PLD 8 Encoder 9 Multiplexer 10 Priority change signal 11 Interrupt request signal 14 Pulse conversion circuit 15 Register circuit 16 System clock 17 Address decoder 18 Latch

Claims (4)

[Claims] [Claim 1] Each of the interrupt request signals is recorded in each register, and the interrupt request signal and the interrupt priority change signal recorded in each register are processed using a programmable logic element. The current highest priority interrupt request signal is determined and inputted to the central processing unit, and interrupt vector information indicating the interrupt factor of the highest priority interrupt request signal is generated, inputted to the central processing unit, and inputted to the central processing unit. 1. An interrupt processing control method, comprising requesting a processing device to perform interrupt processing, and then erasing the contents of a register in which the highest priority interrupt request signal has been recorded. 2. A register for recording each of a predetermined number of interrupt request signals, and determining the highest priority interrupt request signal from the interrupt request signal and interrupt priority change signal of each register and inputting it to the central processing unit. a priority determination circuit comprising a programmable logic element, and vector generation for generating vector information corresponding to the interrupt factor of the highest priority interrupt request signal from the output signal of the determination circuit and inputting the vector information to the central processing unit. and an interrupt request confirmation signal generation circuit that converts the output signal of the vector generation circuit and erases the contents of a register in which the highest priority interrupt request signal has been recorded. Device. 3. The output signal of the determination circuit is directly input to the interrupt request confirmation signal generation circuit instead of being input to the request confirmation signal generation circuit via the vector generation circuit. The interrupt processing control device according to claim 2. 4. A pulse conversion circuit for converting an interrupt request high/low signal into a pulse is provided on the input side of each register, and
3. The interrupt processing control device according to claim 2, further comprising a synchronization circuit for synchronizing the output signal of the priority determination circuit with a system clock between the priority determination circuit, the central processing unit, and the vector generation circuit.