CN117873756A - Kernel interrupt processing method, device, equipment, medium and heterogeneous acceleration device - Google Patents

Abstract

The invention discloses a method, a device, equipment, a medium and heterogeneous acceleration equipment for processing kernel interrupt, and relates to the technical field of computers. Firstly, obtaining the number of the kernel which initiates the interrupt request at the same time, and then sequentially outputting the interrupt request corresponding to the kernel which initiates the interrupt request according to the priority order of the kernel, thereby realizing the output after sequencing the interrupt requests which are sent out at the same time; secondly, the output of the interrupt request is simultaneously initiated according to the priority of the kernel, so that the delay of interrupt initiation is reduced, the fairness of users is improved, a large amount of comparison logic is not needed, and the logic resource expenditure is saved; in addition, the current request vector and each row of the independent hot vector or each column of the independent hot vector of the current priority matrix are polled for phases, the kernel numbers for initiating the interrupt requests are obtained according to the results of the phases, and the interrupt requests of the kernels for initiating the interrupt requests can be accurately output according to the kernel numbers.

Description

Kernel interrupt processing method, device, equipment, medium and heterogeneous acceleration device

Technical Field

The present invention relates to the field of computer technology, and in particular to a kernel interrupt processing method, device, equipment, medium and heterogeneous acceleration equipment.

Background technique

With the development of computer technology, more and more data needs to be processed. In order to meet the needs of processing huge amounts of data, heterogeneous acceleration devices have emerged. After the core in a heterogeneous acceleration device completes a certain operation, the core needs to initiate an interrupt request to the static shell, which then processes the request and notifies the host.

In high-density core scenarios, when multiple cores initiate interrupt requests at the same time, the static shell must complete the parallel-serial conversion of multiple core interrupt requests to the Peripheral Component Interconnect Express (PCIE) interrupt requests, that is, the static shell can only initiate one interrupt to the host computer at a time. In some scenarios where user fairness requirements are high, the order of interrupt initiation directly affects the latency of user functions.

It can be seen that how to process the output of interrupt requests initiated simultaneously to reduce the delay of interrupt initiation and improve user experience is a technical problem that people in this field need to solve urgently.

Summary of the invention

The purpose of the present invention is to provide a kernel interrupt processing method, device, equipment, medium and heterogeneous acceleration device to solve the technical problem that in parallel interrupt application scenarios, if a reasonable interrupt initiation order is not set, it will cause user function delays and reduce user experience.

In order to solve the above technical problems, the present invention provides a method for processing a kernel interrupt, comprising:

Obtaining an interrupt request initiated by a kernel in a multi-core device at a preset time and obtaining a current request vector according to the interrupt request initiated by the kernel in the multi-core device at the preset time;

Get the current priority matrix; wherein, the vectors composed of each row or column of elements in the current priority matrix are all one-hot vectors, and each row of one-hot vectors or each column of one-hot vectors respectively represents the priority order of each kernel;

Performing AND operations on the current request vector and each row one-hot vector or each column one-hot vector of the current priority matrix respectively, and obtaining the kernel number that initiates the interrupt request according to each AND operation result;

The interrupt request corresponding to the core that initiated the interrupt request is output in sequence according to the core number and the priority order of the cores.

On the one hand, before polling and performing AND operation on the current request vector with each row one-hot vector or each column one-hot vector of the current priority matrix respectively, the method further includes:

When it is detected that the number of cores initiating interrupt requests is greater than 1, the step of polling and performing AND operation on the current request vector and each row one-hot vector or each column one-hot vector of the current priority matrix is entered;

When it is detected that the number of cores initiating interrupt requests is equal to 1, determining the core number initiating the interrupt request according to the current request vector; and outputting the interrupt request corresponding to the core according to the core number;

When it is detected that the number of cores initiating interrupt requests is equal to 0, the process ends.

On the other hand, determining that the number of cores that initiate interrupt requests is equal to 1 includes:

When it is detected that the position of the least significant non-zero value and the position of the most significant non-zero value of the current request vector are the same, it is determined that the number of cores initiating interrupt requests is equal to 1.

On the other hand, each row of one-hot vectors represents the priority order of each core, and the smaller the row number, the higher the priority; the current request vector is polled and ANDed with each row of one-hot vectors or each column of one-hot vectors of the current priority matrix, and the core number that initiates the interrupt request is obtained according to each AND result, including:

Sequentially poll and AND the current request vector with each row of the one-hot vector of the current priority matrix;

When it is detected that the result of the current AND operation is not a zero vector, the current kernel number for initiating the interrupt request is determined according to a pre-established correspondence between the vector after the AND operation and the kernel number.

On the other hand, after outputting the interrupt request corresponding to the core that initiated the interrupt request in sequence according to the core number and in combination with the priority order of the cores, or after outputting the interrupt request corresponding to the core according to the core number, the method further includes:

The current request vector is polled and ANDed with each row of one-hot vectors or each column of one-hot vectors in the current priority matrix in order of the kernel priorities from low to high, and the current priority matrix is updated according to the results of each ANDing.

On the other hand, each row of one-hot vectors represents the priority order of each kernel, and the smaller the row number, the higher the priority;

The step of polling and performing AND operations on the current request vector and each row one-hot vector or each column one-hot vector of the current priority matrix in order of the kernel priorities from low to high, and updating the current priority matrix according to the AND operations results comprises:

Performing AND operations on the current request vector and each row of the one-hot vector of the current priority matrix in reverse order;

When it is detected that the result of the current phase and is not a zero vector, the current priority matrix is updated according to a preset method;

When it is detected that the result of the current AND operation is a 0 vector, the priority matrix to be updated corresponding to the last AND operation of the current operation is kept unchanged.

On the other hand, the current priority matrix is an N-order matrix, N is the total number of cores of the multi-core device, and the row of the current priority matrix is labeled k, 0≤k≤N-1; the current request vector is sequentially and polled in reverse order with each row of the one-hot vector of the current priority matrix, and if it is detected that the result of the AND is not a 0 vector, then updating the current priority matrix in a preset manner includes:

When k is equal to N-1, the current request vector is ANDed with the one-hot vector corresponding to the row labeled k of the current priority matrix. If it is detected that the ANDed result is not a zero vector, the one-hot vector corresponding to the row labeled k of the current priority matrix is assigned to the last row of the priority matrix to be updated; the one-hot vector corresponding to the row labeled 0 to the row labeled k-1 of the priority matrix to be updated is the same as the one-hot vector corresponding to the row labeled 0 to the row labeled k-1 of the current priority matrix;

When k is less than N-1, the current request vector is ANDed with the one-hot vector corresponding to the row labeled k of the current priority matrix. If it is detected that the AND result is not a zero vector, the one-hot vector corresponding to the row labeled k of the current priority matrix is assigned to the last row of the priority matrix to be updated; the one-hot vector corresponding to the rows labeled k+1 to N-1 of the priority matrix to be updated corresponding to the last AND operation is assigned to the rows labeled k to N-2 of the priority matrix to be updated; the one-hot vector corresponding to the rows labeled 0 to k-1 of the priority matrix to be updated is the same as the one-hot vector corresponding to the rows labeled 0 to k-1 of the priority matrix to be updated corresponding to the last AND operation.

On the other hand, after obtaining the kernel number that initiates the interrupt request according to the results of each phase and each phase, the method further includes:

Store each kernel number in a first-in-first-out buffer in turn;

The interrupt requests corresponding to the core that initiates the interrupt request are output in sequence through the first-in first-out buffer.

On the other hand, obtaining the current priority matrix includes:

When it is detected that the host computer sets a kernel priority order for the multi-core device, the current priority matrix is established according to the kernel priority order set by the host computer.

On the other hand, the interrupt requests corresponding to the cores initiating the interrupt requests are outputted in sequence according to the core numbers and in combination with the priority order of the cores, including:

Obtain the interrupt control protocol for reporting interrupts that is pre-negotiated with the host computer;

According to the core number, the priority order of the cores and the interrupt control protocol, the interrupt request corresponding to the core that initiates the interrupt request is reported to the host computer in sequence.

On the other hand, after updating the current priority matrix according to the results of each phase, the method further includes:

Starting from obtaining the updated current priority matrix, returning within a preset time period to the steps of obtaining an interrupt request initiated by a core in the multi-core device at a preset time and obtaining a current request vector according to the interrupt request initiated by the core in the multi-core device at the preset time.

In order to solve the above technical problems, the present invention also provides a heterogeneous acceleration device, including: a controller, an interrupt enable register and an interrupt status register corresponding to each core, the controller is respectively connected to each interrupt enable register and each interrupt status register, the interrupt enable register is used to store the interrupt request information corresponding to the core, and the interrupt status register is used to store the situation of initiating the interrupt request corresponding to the core; the controller is used to implement the steps of the above-mentioned core interrupt processing method.

On the other hand, the heterogeneous acceleration device further includes: a first first-in first-out buffer for storing a current request vector, a second first-in first-out buffer for storing a core number that initiates an interrupt request;

The controller is connected to the first FIFO buffer and is used to obtain the current request vector from the first FIFO buffer;

The controller is connected to the second FIFO buffer and is used for sequentially outputting interrupt requests corresponding to the core that initiates the interrupt request through the second FIFO buffer.

In order to solve the above technical problems, the present invention further provides a kernel interrupt processing device, comprising:

A first acquisition module is used to acquire an interrupt request initiated by a kernel in a multi-core device at a preset time and acquire a current request vector according to the interrupt request initiated by the kernel in the multi-core device at the preset time;

The second acquisition module is used to acquire the current priority matrix; wherein each row or column of the current priority matrix is composed of a one-hot vector, and each row of the one-hot vector or each column of the one-hot vector represents the priority order of each kernel;

A polling and acquisition module, used for polling and performing AND operations on the current request vector and each row one-hot vector or each column one-hot vector of the current priority matrix, and obtaining the kernel number that initiates the interrupt request according to each AND operation result;

The output module is used to output the interrupt request corresponding to the core that initiates the interrupt request in sequence according to the core number and the priority order of the cores.

In order to solve the above technical problems, the present invention further provides a kernel interrupt processing device, comprising:

Memory for storing computer programs;

The processor is used to implement the steps of the above-mentioned kernel interrupt processing method when executing the computer program.

In order to solve the above technical problem, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned kernel interrupt processing method are implemented.

The kernel interrupt processing method provided by the present invention includes: obtaining an interrupt request initiated by a kernel in a multi-core device at a preset time and obtaining a current request vector according to the situation that the kernel in the multi-core device initiates the interrupt request at the preset time; obtaining a current priority matrix; wherein the vectors composed of each row or column of elements in the current priority matrix are all one-hot vectors, and each row of one-hot vectors or each column of one-hot vectors respectively represent the priority order of each kernel; performing AND operation on the current request vector and each row of one-hot vectors or each column of one-hot vectors in the current priority matrix respectively, and obtaining the kernel number that initiates the interrupt request according to each AND operation result; and outputting the interrupt request corresponding to the kernel that initiates the interrupt request in sequence according to the kernel number and in combination with the kernel priority order.

The beneficial effects of the present invention are as follows: firstly, by obtaining the core number of the multi-core device that initiates the interrupt request at a preset time, and then outputting the interrupt request corresponding to the core that initiates the interrupt request in sequence according to the priority order of the cores, the sorting and serial output of the interrupt requests issued simultaneously are realized; secondly, since the interrupt request is output according to the priority of the core, the delay of interrupt initiation is reduced, the fairness of users is improved, and the user experience is improved; thirdly, since the interrupt request is output directly according to the priority of the core, a large amount of comparison logic is not required, saving logic resource overhead; in addition, by polling and ANDing the current request vector with each row of the unique hot vector or each column of the unique hot vector of the current priority matrix, and obtaining the core number of the interrupt request according to each AND result, the output of the interrupt request of each core that initiates the interrupt request can be accurately realized according to the core number.

Before polling and ANDing the current request vector with each row one-hot vector or each column one-hot vector of the current priority matrix respectively, when the number of cores initiating interrupt requests is equal to 1, it is not necessary to poll and AND the current priority matrix with the current request vector to obtain the core number. Instead, the core number initiating the interrupt request is directly determined according to the current request vector, and then the interrupt request corresponding to the core is output according to the core number, thereby improving the processing efficiency of a single interrupt request.

When it is determined that the number of cores initiating an interrupt request is 1, the efficiency of determining whether it is a single interrupt request is improved by comparing whether the least significant bit and the most significant bit non-zero values are in the same position.

In the case where each row of one-hot vectors represents the priority order of each core, and the smaller the row number, the higher the priority, the current request vector is sequentially polled and ANDed with each row of one-hot vectors in the current priority matrix to complete the sorting; after outputting the interrupt request corresponding to the core, the current request vector is sequentially polled and ANDed with each row of one-hot vectors in the current priority matrix in reverse order, and the current priority matrix is updated according to the results of each phase, thereby ensuring the fairness of the core interrupt order in the parallel interrupt application scenario.

After obtaining the core number that initiates the interrupt request according to each phase and result, each core number is stored in a first-in first-out buffer in sequence; the first-in first-out buffer is used to realize the sequential output of the interrupt request corresponding to the core that initiates the interrupt request.

In addition, the present invention also provides a heterogeneous acceleration device, a kernel interrupt processing device, a kernel interrupt processing device and a computer-readable storage medium, which have the same or corresponding technical features as the above-mentioned kernel interrupt processing method and have the same effect as above.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

FIG1 is a schematic diagram of a field programmable gate array chip reporting an interruption according to an embodiment of the present invention;

FIG2 is a flow chart of a method for processing a kernel interrupt provided by an embodiment of the present invention;

FIG3 is a schematic diagram of a priority matrix provided by an embodiment of the present invention;

FIG4 is a schematic diagram of an output interrupt request provided by an embodiment of the present invention;

FIG5 is a schematic diagram of a field programmable gate array chip provided by an embodiment of the present invention;

FIG6 is a flow chart of a priority processing method provided by an embodiment of the present invention;

FIG7 is a structural diagram of a kernel interrupt processing device provided by an embodiment of the present invention;

FIG8 is a structural diagram of a kernel interrupt processing device provided by another embodiment of the present invention.

Detailed ways

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of the present invention.

The core of the present invention is to provide a kernel interrupt processing method, device, equipment, medium and heterogeneous acceleration device to solve the technical problem that in parallel interrupt application scenarios, if a reasonable interrupt initiation order is not set, it will cause user function delays and reduce user experience.

There is no limitation on the multi-core device in the embodiment of the present invention, which is determined according to the actual situation. For the convenience of description, the embodiment of the present invention takes the multi-core device as a heterogeneous acceleration device implemented by a Field Programmable Gate Array (FPGA) chip as an example to illustrate the solution in the embodiment of the present invention.

In heterogeneous acceleration devices implemented using FPGA, the design of the FPGA chip part is generally divided into a static shell part and a dynamic kernel part. The shell part implements the basic management functions and interface circuits of the FPGA accelerator; the dynamic kernel part implements various computing acceleration functions required by the host computer. FIG1 is a schematic diagram of a field programmable gate array chip reporting an interrupt provided by an embodiment of the present invention. As shown in FIG1 , a field programmable gate array chip 100 reports a kernel interrupt to a host computer 200. Among them, the dynamic area of the field programmable gate array chip 100 includes multiple kernels, such as kernel 1, kernel 2 to kernel N. After the kernel is controlled to execute a certain operation, the static area needs to collect the kernel's interrupt request and report the interrupt to the host computer 200.

In high-density core scenarios, one or more cores may initiate interrupts at the same time. If only a single core initiates an interrupt request, the static area directly processes the request. Otherwise, the static area must complete the parallel-serial conversion of multiple core interrupt requests to fast peripheral component interconnect interrupt requests. In this process, the order of initiating interrupts needs to be considered. In some scenarios, the processing logic between different cores is relatively independent, and the host computer central processing unit (CPU) has no fixed requirements for the order in which interrupts are received. However, in some scenarios where user fairness requirements are high, the order in which interrupts are initiated directly affects the latency of user functions.

Therefore, the embodiment of the present invention provides a method for processing kernel interrupts, in which the order is based on priority, and the priority is maintained in a static area, which can be tracked and updated in real time through FPGA logic design. Therefore, it is not necessary to design complex comparison logic for the priority value, and only tracking and updating based on the initial priority can quickly obtain the priority relationship between kernels of any interrupt input combination. The output of interrupt requests initiated simultaneously is processed based on the kernel priority, thereby reducing the delay of interrupt initiation and improving the user experience.

In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. FIG2 is a flow chart of a method for processing a kernel interrupt provided by an embodiment of the present invention. As shown in FIG2, the method includes:

S10: Obtaining an interrupt request initiated by a kernel in the multi-core device at a preset time and obtaining a current request vector according to the interrupt request initiated by the kernel in the multi-core device at the preset time;

S11: Obtain the current priority matrix; wherein each row or column of the current priority matrix is composed of a one-hot vector, and each row of the one-hot vector or each column of the one-hot vector represents the priority order of each kernel;

S12: performing AND operations on the current request vector and each row one-hot vector or each column one-hot vector of the current priority matrix respectively, and obtaining the core number of the initiator of the interrupt request according to each AND operation result;

S13: Outputting the interrupt request corresponding to the core that initiated the interrupt request in sequence according to the core number and the priority order of the cores.

In the embodiment of the present invention, whether the kernel initiates an interrupt request or does not initiate an interrupt request is determined by high and low levels, such as a high level indicates that an interrupt request is initiated, and a low level indicates that an interrupt request is not initiated. Since the collected signal is a level signal, it is impossible to distinguish the kernel corresponding to the interrupt request directly based on the level signal. Therefore, in the embodiment of the present invention, when processing a kernel interrupt, it is necessary to determine the kernel that initiates the interrupt request. In order to distinguish each kernel, each kernel in a multi-core device will be numbered in advance. There is no limitation on the numbering of each kernel, which is determined according to the actual situation. If there are 4 kernels, the kernels can be numbered as kernel 0, kernel 1, kernel 2, and kernel 3. That is, when processing a kernel interrupt, it is necessary to determine the number of the kernel that initiates the interrupt request.

In order to determine the core number that initiates the interrupt request, the request vector is polled and ANDed with the priority matrix in an embodiment of the present invention. Specifically, the current request vector is obtained according to the situation that the core in the multi-core device initiates the interrupt request at the preset time. There is no limitation on the preset time. The situation of initiating an interrupt request includes initiating an interrupt request or not initiating an interrupt request. As described above, if an interrupt request is initiated, the level signal collected in the static area is 1; if an interrupt request is not initiated, the level signal collected in the static area is 0, that is, an array composed of 0 and 1 is used as the current request vector. It should be noted that when there is an interrupt request, the request vector is a one-hot vector.

When processing the interrupt requests initiated simultaneously, what is collected is the level signal, that is, the collected data is 0 or 1. If there are multiple 0s and/or multiple 1s in the collected level signal, the sorting result cannot be obtained by comparing the size. For example, if there are 4 cores, if the level signals collected in the static area are 1, 1, 1, 0. Obviously, by comparison, it can only be obtained that there is a core that has not initiated an interrupt request, and the core whose level signal is 1 cannot be sorted by comparison. Therefore, in the embodiment of the present invention, the cores that simultaneously initiate interrupt requests are directly sorted according to the priority of the core, and then the interrupt requests of the cores that initiate interrupt requests are output in order.

There is no limit on the priority of the set kernel. If there is no special requirement, an initial value can be set according to the kernel number. For example, the unit matrix is the kernel with a large number and the highest priority; the matrix with a secondary diagonal of 1 is the kernel with a small number and the highest priority. When the host computer has special requirements, if it is detected that the host computer has set a kernel priority order for the multi-core device, the current priority matrix is established according to the kernel priority order set by the host computer. The vector composed of each row or column element in the current priority matrix is a one-hot vector, and each row of one-hot vectors or each column of one-hot vectors represents the priority order of each kernel. There is no limit on the number of rows and columns of the priority matrix.

The priority matrix set in the embodiment of the present invention is a square matrix, and the order of the priority matrix is the same as the number of cores in the multi-core device. If the total number of cores is N, the priority matrix selected is an N-order matrix. There are 4 cores, namely core 0, core 1, core 2 and core 3. If the priorities of the cores set from high to low are core 1, core 2, core 3 and core 0, when the row label of the priority matrix is set to represent the priority, the smaller the row label, the higher the priority; the column label represents the core number, and the priority matrix established at this time is shown in Figure 3, which is a schematic diagram of a priority matrix provided by an embodiment of the present invention. The first row of one-hot vectors represents that the priority order of core 1 is the highest, the second row of one-hot vectors represents that the priority order of core 2 is lower than the priority order of core 1, the third row of one-hot vectors represents that the priority order of core 3 is lower than the priority order of core 2, and the third row of one-hot vectors represents that the priority order of core 0 is lower than the priority order of core 3. In practice, the column label of the priority matrix can also be set to represent the priority, the smaller the column label, the higher the priority; the row label represents the core number.

After obtaining the current request vector and the current priority matrix, the current request vector is polled and ANDed with each row of one-hot vectors or each column of one-hot vectors of the current priority matrix. It is worth noting that when determining whether to poll and AND the current request vector with each row of one-hot vectors or each column of one-hot vectors of the current priority matrix, it depends on the meaning of the row label or the meaning of the column label in the established priority matrix. If the row label indicates the priority, the current request vector is polled and ANDed with each row of one-hot vectors of the current priority matrix; if the column label indicates the priority, the current request vector is polled and ANDed with each column of one-hot vectors of the current priority matrix. When polling and ANDing, polling can be performed in the order of high to low priority in the priority matrix.

After each AND operation, an AND result is obtained. The current kernel number that initiates the interrupt request is determined based on the pre-established correspondence between the vector after the AND operation and the kernel number. The AND result may be a 0 vector or may not be a 0 vector. When the AND result is a 0 vector, no processing is performed; when the AND result is a 0 vector, the AND result (the AND result is a one-hot vector) is converted into binary, and then the kernel number that initiates the interrupt request corresponding to the current AND result is determined based on the correspondence between the binary and the kernel number. After obtaining the kernel number, the interrupt request corresponding to the kernel that initiates the interrupt request is output in sequence in combination with the kernel priority order. In order to ensure that the interrupt request corresponding to the kernel that initiates the interrupt request can be output in sequence according to the priority order, after obtaining the kernel number that initiates the interrupt request according to each AND result, it also includes: storing each kernel number in a first-in-first-out buffer in sequence; and outputting the interrupt request corresponding to the kernel that initiates the interrupt request in sequence through the first-in-first-out buffer.

The form of initiating an interrupt depends on the interrupt protocol used in the static area. For example, under the extended message signal interrupt (MSIX) protocol, the interrupt initiation module needs to query the specific interrupt vector assigned to the kernel by the host computer and write the interrupt vector to the specified location. Therefore, the interrupt requests corresponding to the kernel that initiates the interrupt request are output in sequence according to the kernel number and the kernel priority order, including:

Obtain the interrupt control protocol for reporting interrupts that is pre-negotiated with the host computer;

According to the core number, the priority order of the cores and the interrupt control protocol, the interrupt request corresponding to the core that initiates the interrupt request is reported to the host computer in sequence.

The method for processing kernel interrupts provided in an embodiment of the present invention first obtains the kernel number of the kernel that initiates the interrupt request in a multi-core device at a preset time, and then outputs the interrupt request corresponding to the kernel that initiates the interrupt request in sequence according to the kernel priority order, thereby realizing the sorting and serial output of interrupt requests issued simultaneously; secondly, since the interrupt request is output according to the kernel priority, the delay of interrupt initiation is reduced, the fairness of users is improved, and the user experience is improved; thirdly, since the interrupt request is output directly according to the kernel priority, a large amount of comparison logic is not required, thus saving logic resource overhead; in addition, by polling and ANDing the current request vector with each row unique hot vector or each column unique hot vector of the current priority matrix respectively, and obtaining the kernel number that initiates the interrupt request according to each AND result, the output of the interrupt request of each kernel that initiates the interrupt request can be accurately realized according to the kernel number.

When only one core initiates an interrupt request at a preset time (i.e., a single interrupt), if the current request vector is polled and ANDed with each row of the one-hot vector or each column of the current priority matrix in the manner described above, since multiple ANDs need to be performed, the efficiency of determining the core number will be reduced. Therefore, in order to reduce the latency of single interrupt request processing, in some implementations, before the current request vector is polled and ANDed with each row of the one-hot vector or each column of the one-hot vector of the current priority matrix, the following is also included:

When it is detected that the number of cores initiating interrupt requests is greater than 1, the step of polling and performing AND operation on the current request vector and each row one-hot vector or each column one-hot vector of the current priority matrix is entered;

When it is detected that the number of cores initiating interrupt requests is equal to 1, the core number initiating the interrupt request is determined according to the current request vector; and the interrupt request corresponding to the core is output according to the core number;

When it is detected that the number of cores initiating interrupt requests is equal to 0, the process ends.

In implementation, the number of interrupt cores requested at one time is determined by combinatorial logic. Determining that the number of cores initiating interrupt requests is equal to 1 includes:

When it is detected that the position of the lowest non-zero value and the position of the highest non-zero value of the current request vector are the same, it is determined that the number of cores that initiate the interrupt request is equal to 1. The number of cores that initiate the interrupt request is equal to 1, and the corresponding current request vector is a one-hot vector. The one-hot vector is converted into binary, and then the core number that initiates the interrupt request is determined according to the corresponding relationship between the binary information and the core number. After the core number is obtained, the interrupt request corresponding to the core is output.

In this embodiment, when it is determined that the number of cores initiating an interrupt request is 1, the core number is directly determined based on the current request vector. There is no need to poll the current request vector with the one-hot vector of each row or each column of the current priority matrix respectively, which improves the efficiency of determining the core number and the efficiency of processing a single interrupt request.

In order to enable those skilled in the art to better understand the method for determining the kernel number and the method for outputting the interrupt request provided by the embodiment of the present invention. Here, taking each row of one-hot vectors as an example to represent the priority order of each kernel, and the smaller the row number, the higher the priority, the process of polling and ANDing the current request vector with each row of one-hot vectors or each column of one-hot vectors of the current priority matrix, and obtaining the kernel number that initiated the interrupt request according to each AND result, is explained. Specifically, the current request vector is polled and ANDed with each row of one-hot vectors of the current priority matrix in sequence;

When it is detected that the result of the current AND operation is not a zero vector, the current kernel number for initiating the interrupt request is determined according to a pre-established correspondence between the vector after the AND operation and the kernel number.

FIG4 is a schematic diagram of an output interrupt request provided by an embodiment of the present invention. Assuming that the total number of cores is 4, the established priority matrix is a 4-order matrix. The row label of the priority matrix represents the priority, and the smaller the row label, the higher the priority. When the pre-set kernel priority is in the order from high to low: core 1, core 2, core 3, core 0, the established priority matrix is shown in matrix A in FIG4. The row labels of the matrix are 0, 1, 2, and 3 from top to bottom. The request vector is 1011, and the request vector 1011 is sequentially ANDed with each row of the priority matrix, and the core that issues the interrupt request is determined according to each AND result. Specifically, 1011&0010 obtains 0010, and core 1 is determined based on 0010, and the interrupt request of core 1 is output; 1011&0100 obtains 0000, and no processing is performed; 1011&1000 obtains 1000, and core 3 is determined based on 1000, and the interrupt request of core 3 is output; 1011&0001 obtains 0001, and core 0 is determined based on 0001, and the interrupt request of core 0 is output.

In the method provided by this embodiment, each row of one-hot vectors represents the priority order of each kernel, and the smaller the row number, the higher the priority. The current request vector is sequentially polled and ANDed with each row of one-hot vectors in the current priority matrix, and the kernel is determined according to the AND result, and the request corresponding to the kernel is output, so as to sort the kernels that initiate interrupt requests at the same time and process the interrupt requests of each kernel that initiates the interrupt request in the order of priority, thereby ensuring the fairness of the kernel interrupt order in the parallel interrupt application scenario as much as possible.

After outputting the request, in order to further ensure the fairness of the kernel interrupt order in the parallel interrupt application scenario, in some embodiments, after outputting the interrupt request corresponding to the kernel that initiated the interrupt request in sequence according to the kernel number and in combination with the kernel priority order, or after outputting the interrupt request corresponding to the kernel according to the kernel number, it also includes:

According to the order of kernel priority from low to high, the current request vector is polled and ANDed with each row one-hot vector or each column one-hot vector of the current priority matrix respectively, and the current priority matrix is updated according to the results of each ANDing.

Similarly, when determining whether to perform polling AND with each row of one-hot vectors or each column of one-hot vectors in the current priority matrix, it depends on the meaning of the row label or the column label in the established priority matrix. If the row label indicates the priority, the current request vector is polled and ANDed with each row of one-hot vectors in the current priority matrix; if the column label indicates the priority, the current request vector is polled and ANDed with each column of one-hot vectors in the current priority matrix. In order to improve the fairness of kernel interrupt processing, the kernel that is interrupted first among the kernels that initiate interrupt requests at the same time has the lowest priority in the next processing, that is, the priority needs to be updated in the same processing cycle.

In order to enable those skilled in the art to better understand the method of updating the priority matrix provided by the embodiment of the present invention. Here, each row of one-hot vectors represents the priority order of each kernel, and the smaller the row number, the higher the priority. As an example, the current request vector is polled and ANDed with each row of one-hot vectors or each column of one-hot vectors in the current priority matrix in order from low to high priority of the kernel, and the current priority matrix is updated according to the results of each AND. It includes polling and ANDing the current request vector with each row of one-hot vectors in the current priority matrix in reverse order; when it is detected that the result of the current AND is not a 0 vector, the current priority matrix is updated according to a preset method; when it is detected that the result of the current AND is a 0 vector, the priority matrix to be updated corresponding to the previous AND of the current AND is kept unchanged.

Specifically, the current priority matrix is an N-order matrix, N is the total number of cores of the multi-core device, and the row of the current priority matrix is labeled k, 0≤k≤N-1; the current request vector is polled and ANDed with each row of the unique hot vector of the current priority matrix in reverse order, and if it is detected that the result of the ANDing is not a zero vector, the current priority matrix is updated according to a preset method, including:

When k is equal to N-1, the current request vector is ANDed with the one-hot vector corresponding to the row labeled k of the current priority matrix. If it is detected that the AND result is not a zero vector, the one-hot vector corresponding to the row labeled k of the current priority matrix is assigned to the last row of the priority matrix to be updated; the one-hot vector corresponding to the row labeled 0 to the row labeled k-1 of the priority matrix to be updated is the same as the one-hot vector corresponding to the row labeled 0 to the row labeled k-1 of the current priority matrix.

When k is less than N-1, the current request vector is ANDed with the one-hot vector corresponding to the row labeled k of the current priority matrix. If it is detected that the result of the ANDing is not a zero vector, the one-hot vector corresponding to the row labeled k of the current priority matrix is assigned to the last row of the priority matrix to be updated; the one-hot vector corresponding to the rows labeled k+1 to N-1 of the priority matrix to be updated corresponding to the last ANDing is assigned to the rows labeled k to N-2 of the priority matrix to be updated; the one-hot vector corresponding to the rows labeled 0 to k-1 of the priority matrix to be updated is the same as the one-hot vector corresponding to the rows labeled 0 to k-1 of the priority matrix to be updated corresponding to the last ANDing.

4 , the method of updating the priority matrix is described. In Figure 4, the first matrix in the update priority matrix is the current priority matrix, i.e., the A matrix. When k=3, the request vector 1011 is ANDed with 0001 of the A matrix, and the result is 0001, which is not a zero vector. Then, the one-hot vector (0001) corresponding to the row labeled 3 of the A matrix is used as the last row (i.e., the row labeled 3) of the A1 matrix (the matrix currently to be updated). The one-hot vectors corresponding to the rows labeled 0 to 2 of the A1 matrix are the same as the one-hot vectors corresponding to the rows labeled 0 to 2 of the A matrix, i.e., the first 3 rows of the A1 matrix are the same as the first 3 rows of the A matrix. When k=2, the request vector 1011 is ANDed with 1000 of the A1 matrix, and the result is 1000, which is not a zero vector. Then, the A1 matrix is continued to be updated, and the one-hot vector (1000) corresponding to the row labeled 2 of the A1 matrix is used as the last row (i.e., the row labeled 3) of the A2 matrix (the matrix currently to be updated). The one-hot vector (0001) corresponding to the row labeled 3 is assigned to the row labeled 2 of the A2 matrix. The one-hot vectors corresponding to the rows labeled 0 to 1 of the A2 matrix are the same as the one-hot vectors corresponding to the rows labeled 0 to 1 of the A1 matrix, that is, the first 2 rows of the A2 matrix are the same as the first 2 rows of the A1 matrix. When k=1, the request vector 1011 is ANDed with the 0100 of the A2 matrix, and the result is 0000, that is, the 0 vector, so there is no need to update at this time. A2 vector; when k=0, the request vector 1011 is ANDed with 0010 of the A2 matrix, and the result is 0010, which is not a 0 vector. Then the A2 matrix is updated, and the one-hot vector (0010) corresponding to the row labeled 0 of the A2 matrix is used as the last row (i.e., the row labeled 3) of the A3 matrix (the matrix to be updated currently), and the one-hot vectors corresponding to the rows labeled 1 to 3 of the A2 matrix are assigned to the rows labeled 0 to 2 of A3. The update of the priority matrix A is realized through the above process.

In the method provided in this embodiment, each row of one-hot vectors represents the priority order of each core, and the smaller the row number, the higher the priority. The current request vector is polled and ANDed with each row of one-hot vectors in the current priority matrix in reverse order, and the current priority matrix is updated according to the results of each AND, thereby ensuring the fairness of the core interrupt order in the parallel interrupt application scenario.

After the current request vector is processed, in practice, there may be multiple current request vectors. In order to continue processing the request vector, after updating the current priority matrix according to the results of each phase, the following is also included:

Starting from obtaining the updated current priority matrix, returning within a preset time period to the steps of obtaining an interrupt request initiated by a core in the multi-core device at a preset time and obtaining a current request vector according to the interrupt request initiated by the core in the multi-core device at the preset time.

There is no limit on the preset duration, which is determined according to the actual situation. It should be noted that when processing a new current request, the current priority matrix here can use the updated priority matrix obtained after the last processing of the request vector, or can use the priority matrix created according to the new priority order set on the host computer. When there is a new request vector, the method described above can be used to output the new request vector.

A method for processing a kernel interrupt is described above, and this embodiment further provides a heterogeneous acceleration device. The heterogeneous acceleration device includes: a controller, an interrupt enable register and an interrupt status register corresponding to each kernel, the controller is connected to each interrupt enable register and each interrupt status register respectively, the interrupt enable register is used to store the interrupt request information corresponding to the kernel, and the interrupt status register is used to store the situation of initiating an interrupt request corresponding to the kernel; the controller is used to implement the steps of the method for processing a kernel interrupt described above.

The heterogeneous acceleration device further includes: a first first-in first-out buffer for storing a current request vector, a second first-in first-out buffer for storing a kernel number that initiates an interrupt request;

The controller is connected to the first FIFO buffer and is used to obtain the current request vector from the first FIFO buffer;

The controller is connected to the second FIFO buffer and is used for sequentially outputting the interrupt requests corresponding to the core that initiates the interrupt request through the second FIFO buffer.

FIG5 is a schematic diagram of a field programmable gate array chip provided by an embodiment of the present invention. As shown in FIG5 , the field programmable gate array chip 100 acceleration platform is divided into two parts: a dynamic area and a static area. A large number of cores in the dynamic area realize the calculation acceleration function required by the host computer. The method for processing kernel interrupts provided by an embodiment of the present invention is mainly implemented in the static area. In the dynamic area, each kernel is provided with an interrupt enable register, which outputs an interrupt signal to an interrupt information extraction module. The static area is divided into three parts: an interrupt information extraction module, an interrupt initiation module, and a priority management module.

The interrupt information extraction module extracts valid interrupt request information from the interrupt enable register of the kernel and submits the valid kernel interrupt request to the priority search module. Due to the delay characteristics of the interrupt enable register, the request signal from the kernel to the interrupt information extraction module remains at a valid level even after the interrupt is issued, until the driver reads the interrupt status register and clears the valid value of the interrupt enable register. Therefore, the valid interrupt request must be identified through the effective edge detection of the interrupt information extraction module for direct use by the priority management module.

In the embodiment of the present invention, it is required that a request must spend a fixed clock cycle to complete the polling of the priority matrix. Therefore, it is necessary to screen out the cycle of a single core request for separate processing to maximize the time efficiency of initiating interrupts. Priority management is subdivided into two parts: the search for interrupt initiation priority and the update of the interrupt priority matrix. The two parts are functionally independent and can be executed in parallel logically. FIG6 is a flow chart of a priority processing method provided by an embodiment of the present invention. As shown in FIG6, the method includes:

S14: Waiting for a valid interruption request;

S15: Determine whether the number of interrupt cores is equal to 1; if so, proceed to step S16; if not, proceed to step S19;

S16: Calculate the interrupt kernel number (convert one-hot code to binary);

S17: Output single interrupt request;

S18: Outputting a first priority matrix to be updated;

S19: The interrupt request vector is ANDed with the interrupt priority matrix in sequence;

S20: output multiple interrupt requests;

S21: The interrupt request vector is polled in reverse order with the interrupt priority matrix;

S22: Outputting a second priority matrix to be updated;

S23: Update the first priority matrix to be updated or the second priority matrix to be updated, and return to step S14.

The priority management module waits for the valid interrupt request from the interrupt information extraction module, and determines the number of interrupt cores requested at one time through combinational logic. The determination method is to determine whether the least significant bit and the most significant bit are in the same position. If they are the same, the number of interrupt cores is 1.

After the number of interrupt cores is determined, the process branch is selected. Since both branches have the requirements of updating the priority matrix and outputting interrupt requests, and the processing delay of multiple interrupt branches is much higher than that of single interrupt branches when the number of cores is large, in order to ensure that the output interrupts are not out of order and avoid complex arbitration logic, a finite state machine is used here to completely divide the processing of the two branches in time, and merge the states when updating the priority matrix.

The manner of outputting a single interrupt request when there is a single interrupt request and outputting multiple interrupt requests when there are multiple interrupt requests, as well as the manner of updating the priority matrix have been described in detail above, and will not be repeated here.

The interrupt initiation module receives the core number to be interrupted through the first-in first-out buffer device and issues interrupt vectors in sequence.

In the method provided by the embodiment of the present invention, single interrupt and multiple interrupt requests are classified and processed, the priorities of each core that initiates interrupts at the same time are determined by ANDing the interrupt request vector with the order of each row of the priority matrix, and the priority matrix is updated by ANDing the interrupt request vector with the reverse order of each row of the priority matrix to ensure fairness among cores; whether it is a single interrupt request is quickly determined based on comparing whether the lowest and highest non-zero values are in the same position; the sorting is based on the priority of the core, rather than completely unknown input data, and the sorting process is implemented by polling the priority matrix through searching and updating the interrupt priority matrix, which can realize the priority sorting of core interrupts without comparison and save logic resource overhead.

In the above embodiments, the method for processing kernel interrupts is described in detail, and the present invention also provides embodiments corresponding to the kernel interrupt processing device and kernel interrupt processing equipment. It should be noted that the present invention describes the embodiments of the device part from two perspectives, one is based on the functional module perspective, and the other is based on the hardware perspective.

FIG7 is a structural diagram of a kernel interrupt processing device provided by an embodiment of the present invention. This embodiment is based on the perspective of functional modules and includes:

A first acquisition module 10 is used to acquire an interrupt request initiated by a core in a multi-core device at a preset time and acquire a current request vector according to the interrupt request initiated by the core in the multi-core device at the preset time;

The second acquisition module 11 is used to acquire the current priority matrix; wherein each row or column of the current priority matrix is composed of a one-hot vector, and each row of the one-hot vector or each column of the one-hot vector represents the priority order of each kernel;

The polling and acquisition module 12 is used to perform AND operation on the current request vector and each row one-hot vector or each column one-hot vector of the current priority matrix, and obtain the kernel number that initiates the interrupt request according to each AND operation result;

The output module 13 is used to sequentially output the interrupt request corresponding to the core that initiated the interrupt request according to the core number and the priority order of the cores.

In some embodiments, it also includes:

The detection module is used to trigger the polling and acquisition module 12 when it is detected that the number of cores initiating interrupt requests is greater than 1; determine the core number initiating the interrupt request according to the current request vector when it is detected that the number of cores initiating interrupt requests is equal to 1; output the interrupt request corresponding to the core according to the core number; and end when it is detected that the number of cores initiating interrupt requests is equal to 0.

Each row of unique hot vectors represents the priority order of each kernel, and the smaller the row number, the higher the priority; the polling and acquisition module 12 includes:

The sequential polling and determination module is used to sequentially poll and AND the current request vector with each row of the one-hot vector of the current priority matrix in turn; when it is detected that the result of the current AND is not a 0 vector, the current kernel number that initiates the interrupt request is determined based on the pre-established correspondence between the vector after the AND and the kernel number.

In some embodiments, it also includes: an AND and update module, which is used to poll the current request vector with each row of one-hot vectors or each column of one-hot vectors in the current priority matrix in order from low to high priority of the kernel, and update the current priority matrix according to each AND result.

Each row of unique hot vectors represents the priority order of each kernel, and the smaller the row number, the higher the priority; the AND and update modules include:

A reverse polling AND module is used to perform reverse polling AND operations on the current request vector and each row of the one-hot vector of the current priority matrix in sequence;

An updating module, used for updating the current priority matrix according to a preset method when detecting that the current phase and result is not a zero vector;

The maintaining module is used to keep the priority matrix to be updated corresponding to the last phase and the current phase unchanged when it is detected that the result of the current phase and the current phase is a 0 vector.

The current priority matrix is an N-order matrix, where N is the total number of cores of the multi-core device, and the row of the current priority matrix is labeled k, 0≤k≤N-1; the update module is specifically used for:

When k is equal to N-1, the current request vector is ANDed with the one-hot vector corresponding to the row labeled k of the current priority matrix. If it is detected that the result of the ANDing is not a zero vector, the one-hot vector corresponding to the row labeled k of the current priority matrix is assigned to the last row of the priority matrix to be updated; the one-hot vector corresponding to the row labeled 0 to the row labeled k-1 of the priority matrix to be updated is the same as the one-hot vector corresponding to the row labeled 0 to the row labeled k-1 of the current priority matrix;

When k is less than N-1, the current request vector is ANDed with the one-hot vector corresponding to the row labeled k of the current priority matrix. If it is detected that the result of the ANDing is not a zero vector, the one-hot vector corresponding to the row labeled k of the current priority matrix is assigned to the last row of the priority matrix to be updated; the one-hot vector corresponding to the rows labeled k+1 to N-1 of the priority matrix to be updated corresponding to the last ANDing is assigned to the rows labeled k to N-2 of the priority matrix to be updated; the one-hot vector corresponding to the rows labeled 0 to k-1 of the priority matrix to be updated is the same as the one-hot vector corresponding to the rows labeled 0 to k-1 of the priority matrix to be updated corresponding to the last ANDing.

In some embodiments, it also includes:

A storage module, used for sequentially storing the kernel numbers in a first-in first-out buffer;

The output submodule is used to sequentially output the interrupt requests corresponding to the core that initiates the interrupt request through the first-in first-out buffer.

The second acquisition module 11 is specifically configured to establish a current priority matrix according to the priority order of the cores set by the host computer when it is detected that the host computer sets a priority order of the cores for the multi-core device.

The output module 13 includes:

A third acquisition module is used to acquire an interrupt control protocol for reporting interrupts that is pre-negotiated with the host computer;

The reporting module is used to report the interrupt request corresponding to the core that initiates the interrupt request to the host computer in sequence according to the core number, the priority order of the cores and the interrupt control protocol.

Since the embodiments of the apparatus part correspond to the embodiments of the method part, the embodiments of the apparatus part refer to the description of the embodiments of the method part, which will not be described here. And it has the same beneficial effects as the above-mentioned kernel interrupt processing method.

FIG8 is a structural diagram of a kernel interrupt processing device provided by another embodiment of the present invention. This embodiment is based on the hardware perspective, as shown in FIG8, the kernel interrupt processing device includes:

A memory 20, for storing computer programs;

The processor 21 is used to implement the steps of the method for processing kernel interrupts mentioned in the above embodiment when executing a computer program.

Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one hardware form of a digital signal processor (DSP), a field programmable gate array, and a programmable logic array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU; the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 21 may be integrated with a graphics processing unit (GPU), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 20 is at least used to store the following computer program 201, wherein, after the computer program is loaded and executed by the processor 21, the relevant steps of the kernel interrupt processing method disclosed in any of the aforementioned embodiments can be implemented. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, the data involved in the kernel interrupt processing method mentioned above.

In some embodiments, the kernel interrupt processing device may further include a display screen 22 , an input/output interface 23 , a communication interface 24 , a power supply 25 , and a communication bus 26 .

Those skilled in the art will appreciate that the structure shown in FIG. 8 does not constitute a limitation on the device for processing kernel interrupts, and may include more or fewer components than those shown in the figure.

The kernel interrupt processing device provided by the embodiment of the present invention includes a memory and a processor. When the processor executes the program stored in the memory, it can implement the following method: the kernel interrupt processing method has the same effect as above.

Finally, the present invention also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps recorded in the above method embodiment are implemented.

It is understandable that if the method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc. Various media that can store program codes.

The computer-readable storage medium provided by the present invention includes the above-mentioned method for processing kernel interrupts, and the effect is the same as above.

The above is a detailed introduction to the kernel interrupt processing method, device, equipment, medium and heterogeneous acceleration device provided by the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified in several ways, and these improvements and modifications also fall within the scope of protection of the present invention.

It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims (16)

1. A method for processing a kernel interrupt, comprising:

obtaining an interrupt request initiated by a core in the multi-core device at a preset moment, and obtaining a current request vector according to the condition that the interrupt request is initiated by the core in the multi-core device at the preset moment;

acquiring a current priority matrix; the vector formed by each row or each column of elements in the current priority matrix is a single-hot vector, and each row of single-hot vector or each column of single-hot vector respectively represents the priority sequence of each kernel;

the current request vector and each row of independent heat vector or each column of independent heat vector of the current priority matrix are polled and phase-separated respectively, and the kernel number for initiating the interrupt request is obtained respectively according to the phase-separated results;

and sequentially outputting interrupt requests corresponding to the cores for initiating the interrupt requests according to the core numbers and the priority order of the cores.

2. The method of claim 1, wherein prior to the step of separately sorting the current request vector from each row of the current priority matrix and each column of the single hot vector, the method further comprises:

when the number of cores for initiating the interrupt request is detected to be greater than 1, entering a step of carrying out phase-separating on the current request vector and each row of independent hot vectors or each column of independent hot vector polling of the current priority matrix respectively;

Under the condition that the number of cores for initiating the interrupt request is detected to be equal to 1, determining the number of the cores for initiating the interrupt request according to the current request vector; outputting an interrupt request corresponding to the kernel according to the kernel number;

in the case that the number of cores that initiate the interrupt request is detected to be equal to 0, then the process ends.

3. The method of processing a core interrupt according to claim 2, wherein determining that the number of cores that initiate the interrupt request is equal to 1 comprises:

and determining that the number of cores for initiating the interrupt request is equal to 1 under the condition that the position of the lowest non-zero value and the position of the highest non-zero value of the current request vector are detected to be the same.

4. The method for processing the kernel interrupt according to claim 1, wherein each row of the independent hot vectors respectively represents a priority order of each kernel, and a smaller row mark represents a higher priority; the polling the current request vector with each row of the independent hot vector or each column of the independent hot vector of the current priority matrix respectively, and obtaining the kernel number for initiating the interrupt request according to the phase results respectively comprises the following steps:

sequentially polling the current request vector and each row of independent heat vector of the current priority matrix;

And under the condition that the current phase and the result are not 0 vector, determining the current kernel number for initiating the interrupt request according to the corresponding relation between the vector and the kernel number after the phase is established in advance.

5. The method for processing a kernel interrupt according to claim 2, wherein after sequentially outputting the interrupt request corresponding to the kernel that initiates the interrupt request according to the kernel number in combination with the priority order of the kernel, or after outputting the interrupt request corresponding to the kernel according to the kernel number, further comprises:

and respectively carrying out polling phase and phase counting on the current request vector and each row of the independent hot vector or each column of the independent hot vector of the current priority matrix according to the order of the priority of the kernel from low to high, and updating the current priority matrix according to the phase and results.

6. The method for processing the kernel interrupt according to claim 5, wherein each row of the independent hot vectors respectively represents a priority order of each kernel, and a smaller row mark represents a higher priority;

the step of carrying out polling phase-to-phase connection on the current request vector and each row of the independent hot vector or each column of the independent hot vector of the current priority matrix according to the order of the priority of the kernel from low to high, and the step of updating the current priority matrix according to the phase-to-phase results comprises the following steps:

The current request vector and each row of the current priority matrix are subjected to reverse order polling phase;

under the condition that the current secondary phase and the result are not 0 vector, updating the current priority matrix according to a preset mode;

and under the condition that the current phase and the result are 0 vector, keeping the priority matrix to be updated corresponding to the last phase and the last phase of the current time unchanged.

7. The method for processing a kernel interrupt according to claim 6, wherein the current priority matrix is an N-order matrix, N is the total number of kernels of the multi-kernel device, and the row of the current priority matrix is denoted by k, and k is equal to or greater than 0 and equal to or less than N-1; the current request vector and each row of the single-heat vector of the current priority matrix are polled and the phase is reversed in sequence, and if the phase is detected to be not the 0 vector, the updating of the current priority matrix according to the preset mode comprises the following steps:

when k is equal to N-1, the independent hot vector phase corresponding to the current request vector and the row marked with k of the current priority matrix is added, and if the phase-phase result is detected to be not 0 vector, the independent hot vector corresponding to the row marked with k of the current priority matrix is assigned to the last row of the current priority matrix to be updated; the independent heat vector corresponding to the row marked with 0 to the row marked with k-1 of the current priority matrix to be updated is the same as the independent heat vector corresponding to the row marked with 0 to the row marked with k-1 of the current priority matrix;

When k is smaller than N-1, the independent hot vector phase corresponding to the current request vector and the row marked with k of the current priority matrix is combined, and if the phase-to-phase result is detected to be not a 0 vector, the independent hot vector corresponding to the row marked with k of the current priority matrix is assigned to the last row of the current priority matrix to be updated; assigning independent heat vectors corresponding to the rows from k+1 to N-1 of the priority matrix to be updated corresponding to the last and last phases of the current time to the rows from k to N-2 of the priority matrix to be updated; the unique heat vector corresponding to the row marked with 0 to the row marked with k-1 of the current priority matrix to be updated is the same as the unique heat vector corresponding to the row marked with 0 to the row marked with k-1 of the current priority matrix corresponding to the last and last phases.

8. The method for processing a core interrupt according to claim 1, further comprising, after the core numbers for initiating the interrupt request are obtained from the respective phases and the results, respectively:

sequentially storing each kernel number in a first-in first-out buffer;

and sequentially outputting interrupt requests corresponding to the cores initiating the interrupt requests through the first-in first-out buffer.

9. The method for processing a kernel interrupt according to claim 1, wherein said obtaining a current priority matrix comprises:

and under the condition that the upper computer is detected to set the kernel priority order for the multi-kernel device, establishing the current priority matrix according to the kernel priority order set by the upper computer.

10. The method for processing a kernel interrupt according to claim 1, wherein sequentially outputting interrupt requests corresponding to a kernel from which the interrupt request is initiated according to the kernel number in combination with the priority order of the kernel comprises:

acquiring an interrupt control protocol which is negotiated with an upper computer in advance and used for reporting the interrupt;

and sequentially reporting the interrupt request corresponding to the kernel initiating the interrupt request to the upper computer according to the kernel number, the priority order of the combined kernel and the interrupt control protocol.

11. The method according to any one of claims 5 to 7, further comprising, after updating the current priority matrix according to the respective phases and the result:

and returning an interrupt request initiated by the kernel in the multi-kernel device at the preset time within the preset time from the updated current priority matrix, and acquiring a current request vector according to the condition that the kernel in the multi-kernel device at the preset time initiates the interrupt request.

12. A heterogeneous acceleration device, comprising: the interrupt control device comprises a controller, interrupt enabling registers and interrupt state registers corresponding to the cores, wherein the controller is respectively connected with the interrupt enabling registers and the interrupt state registers, the interrupt enabling registers are used for storing interrupt request information corresponding to the cores, and the interrupt state registers are used for storing interrupt request initiating conditions corresponding to the cores; the controller is configured to implement the steps of a method for processing a kernel interrupt according to any one of claims 1 to 11.

13. The heterogeneous acceleration apparatus of claim 12, further comprising: a first-in first-out buffer for storing the current request vector, a second first-in first-out buffer for storing the kernel number of the interrupt request;

the controller is connected with the first-in first-out buffer and is used for acquiring the current request vector from the first-in first-out buffer;

the controller is connected with the second first-in first-out buffer and is used for sequentially outputting interrupt requests corresponding to the cores initiating the interrupt requests through the second first-in first-out buffer.

14. A device for processing a core interrupt, comprising:

the first acquisition module is used for acquiring an interrupt request initiated by the inner core in the multi-core device at the preset moment and acquiring a current request vector according to the condition that the inner core in the multi-core device at the preset moment initiates the interrupt request;

the second acquisition module is used for acquiring the current priority matrix; the vector formed by each row or each column of elements in the current priority matrix is a single-hot vector, and each row of single-hot vector or each column of single-hot vector respectively represents the priority sequence of each kernel;

the polling and obtaining module is used for polling the current request vector with each row of independent hot vector or each column of independent hot vector of the current priority matrix respectively and obtaining the kernel number for initiating the interrupt request according to the phase results;

and the output module is used for sequentially outputting interrupt requests corresponding to the cores for initiating the interrupt requests according to the core numbers and in combination with the priority order of the cores.

15. A processing device for a kernel interrupt, comprising:

a memory for storing a computer program;

a processor for implementing the steps of the method for processing a core interrupt according to any one of claims 1 to 11 when executing said computer program.

16. A computer-readable storage medium, on which a computer program is stored, which computer program, when being executed by a processor, implements the steps of the method of handling a core interrupt according to any of claims 1 to 11.