JPH05325564A - Input buffer for system clock of semiconductor storage device - Google Patents

Abstract

PURPOSE:To speed up the generation of an internal clock at the time of an MOS-level input by changing paths that the input passes according to the kind of the level of the system clock. CONSTITUTION:Whether the system clock which is inputted is at the MOS level or TTL level is previously set with a mode select signal SEL. When the SEL is at 'H', i.e., the MOS level of input, output of a two-input NAND 107 is held at 'H' and the system clock K is passed through a two-input NAND 108 and an R-SFF 104 to generate the internal clock 103 instead. Consequently, unnecessary delay of a two-input NOR 105 and a NOT 106 for level conversion is cut and the internal clock can be generated at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input buffer of a system clock synchronization type CMOS semiconductor memory device.

[0002]

2. Description of the Related Art In a system using a semiconductor memory device, a system clock for controlling the system is classified into a TTL level and a MOS level according to the application.
Therefore, in the semiconductor memory device, the input buffer is TT
A logic gate that can handle both L level and MOS level is built.

FIG. 8 shows a conventional system clock-synchronized system clock K input buffer. In FIG. 8, 801 is an input pin of the system clock K, 802 is an RS flip-flop, 803 is an internal clock which is the Q output of the RS flip-flop, 804 is a NOR type gate, 805 is an inverter, and 806 is a Pch type. Reference numeral 807 denotes a transistor, which is surrounded by a dotted line, is a conversion circuit unit for converting from the TTL level to the MOS level.

Next, the operation will be described. FIG. 9 shows the operation waveforms of FIG. Input pin 801 for system clock K
If the system clock input from is at the TTL level, the NOR gate 804, the inverter 805, the Pch
Type transistor 806 allows the TTL level to be changed to the MO level.
It is converted to the S level, passes through the inverter 808 and the RS flip-flop 802, and becomes the internal clock 803. When the system clock to the input pin 801 is at the MOS level, the internal clock 803 is generated as it is through each gate and the RS flip-flop 802.

However, in the case of a system in which the system clock is input to this K input buffer at the MOS level, the TT at the first input stage of the system clock K input buffer is used.
The conversion unit 807 for converting from the L level to the MOS level is unnecessary from the viewpoint of access time. That is,
The access is delayed by a delay corresponding to two logic gates 804 and 8052 of the conversion unit 807.

[0006]

Since the conventional input buffer for the system clock K is constructed as described above,
If the input to the K buffer is at MOS level, TT
Conversion unit 80 for conversion from L level to MOS level
The internal clock is unnecessarily delayed by a delay of 7. Particularly, in the system clock synchronous type semiconductor memory device, since the operation is controlled by the internal clock, there is a problem that the delay of the internal clock causes a delay of the entire access time.

Further, in a high-speed semiconductor memory device that completes its operation (reading and writing of data) in one cycle of the system cycle, there is a problem in that the generation of the internal clock is delayed when the frequency of the system clock is increased. was there.

The present invention has been made to solve the above problems, and by changing the path through which the input passes according to the type of the level of the system clock,
System clock synchronous CMOS capable of speeding up internal clock generation in the case of MOS level input
An object is to obtain an input buffer of a semiconductor memory device.

[0009]

In the input buffer according to the present invention, whether the system clock is at the TTL level or M
Depending on the mode select signal at OS level, TT
The logic gate for converting from the L level to the MOS level is used or not used.

[0010]

According to the input buffer of the present invention, the input buffer corresponding to the input level of the system clock K can be easily selected by the mode select signal. Particularly, when the input level of the system clock K is the MOS level, the TTL level to the MOS level can be selected. The generation of the internal clock is speeded up by the delay of the logic gate for the conversion to.

[0011]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an input buffer of a system clock synchronous CMOS semiconductor memory device according to an embodiment of the present invention. In the figure, 101 is an external system clock input pin, 100 is a 2-input NOR gate 105 and an inverter 1.
06 and P-channel transistor 109, TT
A level conversion circuit for converting the L level to the MOS level, 102 is a mode select signal SEL indicating whether the system clock K is the TTL level or the MOS level,
Reference numeral 108 denotes a second two-input N for outputting an external system clock when the mode select signal SEL102 is "H".
AND, 107 is a first two-input NAND for outputting a signal that has passed through the level conversion circuit 100 when the mode select signal SEL102 is "L", and 104 is an output of the first two-input NAND 107 for S1 input, , A three-input RS flip-flop, which uses the output of the two-input NAND 108 as the S2 input, 103 is the RS flip-flop 10
4 is an internal clock signal which is the Q output of 4. Three-input R-
The S flip-flop 104 is shown in FIG. In the figure,
200 is a 2-input NAND, 201 is a negative logic 3-input OR,
S1 and S2 are first and second S (set) inputs, and R is a reset input.

Next, the operation will be described. Whether the input system clock is the MOS level or the TTL level is set in advance by the mode select signal SEL. In the figure, when SEL is "L", a TTL level input is received, and when SEL is "H", a MOS level input is received. When SEL is “L”, that is, when the input is at the TTL level, the logic gates 105 and 106 and the P-channel transistor 109 change the TTL level to the MOS level.
After being converted to a level, the two-input NAND 107, RS
The internal clock 103 is generated via the flip-flop 104. The operation waveform at this time is shown in FIG. From this figure, it can be seen that the rise of the internal clock 103 is delayed by the time t1 as compared with the rise of the system clock input 101.

On the other hand, when SEL is "H", that is, when the input is at the MOS level, the two-input NAND10 is used.
The output of 7 is fixed at "H", and the system clock K is replaced by the two-input NAND 108 and the RS flip-flop 1.
The internal clock 103 is generated via 04. By doing so, the two-input NOR 105, N for level conversion
By cutting unnecessary delay of OT106,
It is possible to speed up the generation of the internal clock. The operation waveform at this time is shown in FIG. From this figure, internal clock 1
It can be seen that the rising edge of 03 is delayed by a time t2 shorter than the time t1 with respect to the rising edge of the system clock input 101.

As described above, in this embodiment, the logic gate for processing the input signal is 108, 100, or 107 depending on whether the input level of the system clock is the MOS level or the TTL level, that is, the mode select signal SEL. Switching is performed, and when the input system clock is at the MOS level by the switching, the output of the input buffer can be speeded up.

Example 2. FIG. 5 shows another embodiment of the present invention, which is a circuit constructed by using the two-input type RS flip-flop 501 shown in FIG. In FIG. 6, 300 is a two-input NAND, 301 is a negative logic two-input OR, S is an S (set) input, and R is a reset input.

In the figure, 110 is composed of an inverter 111 and two transmission gates 112 and 113, and inputs the system clock input 101 to the level conversion circuit 100 side from the TTL level to the MOS level or processes the input of the MOS level. Mode select signal SE
A switching circuit for switching by L. Also, 1
Reference numeral 20 is an inverter connected to the output of the level conversion circuit 100, 121 is a transmission gate for switching whether or not to pass the output by the mode select signal SEL, and 122 is SEL for whether or not to pass the output of the two-input NAND 108. It is a transmission gate that is switched by.

Also in the K input buffer of the present embodiment shown in FIG. 5 using the two-input RS flip-flop 501 shown in FIG. 6, the circuit means 110 causes the mode select signal SEL to set the input level of the system clock to the MOS level. The logic gate that processes the input signal is switched between 108 and either 100 or 120 depending on whether it is the TTL level or the TTL level, and when the input system clock is the MOS level by the switching, the output of the input buffer It is possible to speed up the process, and it has the same operation and effect as the first embodiment.

Example 3. FIG. 7 shows still another embodiment of the present invention. In the above embodiment, the mode select signal SE
By switching the input first stage of the input buffer by L,
In the case of the MOS level input, the generation of the internal clock is speeded up, but in this embodiment, the input first stage is switched by the switches 701a and 701b by the wiring on the pattern layout. That is, the case where the input is at the MOS level and the case where the input is at the TTL level are distinguished by the wiring method.

For example, when the input 101 receives the TTL level, the wiring on the pattern layout is switched to the switch 70.
1a and 701b, input 101 is two-input NOR
Connected to the input of 702, the output of the inverter 705 in the latter stage of the level conversion circuit including the two-input NOR 702, the inverter 704 and the P-channel transistor 709 is connected to the S input of the RS flip-flop 501. At this time, the input of the inverter 703 is the power supply and the output is floating. On the other hand, when the input 101 receives the MOS level, the wiring on the pattern layout is connected to the switch 70 in the figure.
Instead of the state of 1a and 701b, the upper and lower two contact pieces intersect each other, the input 101 is connected to the input of the inverter 703, and the output of the inverter 703 is connected to the S input of the RS flip-flop 501. At this time, two-input NOR
The input of 702 is connected to the power supply, and the output of the inverter 705 is left floating.

In the configuration of this embodiment, in the circuit in which the input level of the system clock K is the TTL level, the input can be converted by the conversion circuit from the TTL level to the MOS level and output. The input is M
In the OS level circuit, the TTL level to M
It is possible to prevent the generation of the internal clock from being delayed by the delay of the logic gate for conversion to the OS level, and as a result, it is possible to obtain substantially the same operation and effect as in the first embodiment.

Further, according to such a configuration, by adding only one inverter 703 to the conventional input buffer,
It is very easy to increase the speed of the internal clock with respect to the system clock of MOS level input.

[0022]

As described above, according to the present invention, the first stage of the input buffer of the system clock K is provided by the circuit means or in the pattern layout depending on whether the system clock K is at the MOS level or the TTL level. Since it is configured to be switched by switching the wiring of, if the input of the system clock K is at the MOS level, the internal clock which is the output of the input buffer can be easily speeded up.

[Brief description of drawings]

FIG. 1 is a diagram showing a system clock K input buffer of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a three-input RS flip-flop.

FIG. 3 shows a TT of a K input buffer according to an embodiment of the present invention.
FIG. 7 is an operation waveform diagram at the time of L level input.

FIG. 4 is an M diagram of a K input buffer according to an embodiment of the present invention.
FIG. 6 is an operation waveform diagram when an OS level is input.

FIG. 5 is a diagram showing a K input buffer according to another embodiment of the present invention.

FIG. 6 is a diagram showing a two-input RS flip-flop.

FIG. 7 is a diagram showing a K input buffer according to still another embodiment of the present invention.

FIG. 8 is a diagram showing a conventional K input buffer.

FIG. 9 is an operation waveform diagram of a conventional K input buffer.

[Explanation of symbols]

101 external system clock input pin 102 mode select signal 103 internal clock 104 RS flip-flop 100 level conversion circuit from TTL level to MOS level 107 two-input NAND 108 two-input NAND 105 two-input NOR gate 106 inverter 109 P-channel MOS transistor 110 Switching Circuit 111 Inverter 112 Transfer Gate 113 Transfer Gate 105 Two-input NOR 501 Two-input RS Flip-flop 120 Inverter 121 Transfer Gate 122 Transfer Gate 701a, 701b Switch by wiring on pattern layout

Claims (5)

[Claims] 1. A semiconductor memory comprising a memory array for storing data, and means for reading and writing data in response to an external request from the memory array, the operation of which is performed in synchronization with a system clock. In an input buffer for taking in a system clock in a device, the input level of the system clock is a MOS level or T
A means for switching a logic gate for processing an input signal depending on whether it is a TL level is provided, and when the input system clock is a MOS level, the output of the input buffer can be speeded up by the switching. Input buffer for system clock of semiconductor memory device. 2. The input buffer according to claim 1, wherein the means for switching the logic gate comprises a circuit means. 3. The input buffer according to claim 2, wherein a level conversion circuit for converting a signal from a system clock input pin from a TTL level to a MOS level, and a signal from the level conversion circuit and a mode select signal are provided. A first two-input NAND gate that receives the input, a second two-input NAND gate that receives the signal from the system clock input pin and an inversion mode select signal as two inputs, and an output of the first two-input NAND gate To a first S input, and a three-input RS flip-flop having the second S-input as an output of the second two-input NAND gate, and inputting a system clock of the semiconductor memory device. buffer. 4. The input buffer according to claim 2, wherein two transmission gate circuits for passing or blocking a signal from a system clock input pin according to a mode select signal, and a signal from the one transmission gate. To TT
A level conversion circuit for converting the L level to the MOS level, an inverter for inverting the output thereof, a two-input NAND gate for allowing the MOS level signal from the other transmission gate to pass by an inversion mode select signal, and the level conversion circuit And an output of the two-input NAND gate in a required mode, and an SR flip-flop for inputting a signal passing through the transmission gate in each of the required modes as an S input. An input buffer for a system clock of a characteristic semiconductor memory device. 5. The input buffer according to claim 1, wherein the switching of the input first stage is performed by switching the wiring on the pattern layout, and the TTL level and the MOS level are determined when the product is completed. An input buffer for a system clock of a semiconductor memory device characterized by: