JPH06149942A - Automatic wiring path designing device - Google Patents

Abstract

PURPOSE:To considerably improve a wiring rate by dividing an expanded area and deciding a final wiring path from a rough wiring path on the divided area. CONSTITUTION:This device is provided with a wiring area compressing means 10 for compressing the area of a wiring object, rough path deciding means 12 for deciding the rough wiring path on the compressed area, wiring area expanding means 14 for expanding the area, where the rough wiring path is decided, into the size before compression, wiring area dividing means 16 for dividing the expanded area, and final path deciding means 18 for deciding the final wiring path from the rough wiring path on the respective partial divided areas. In this case, first of all, the wiring object area is laterally or longitudinally or bidirectionally compressed, and the rough wiring path is decided on this area. Then, this area is divided after the compressed size is returned to the original size, and the wiring path is finally decided concerning each divided area by using the rough wiring path.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic wiring route designing device for automatically designing a wiring route.
Designing a wiring path in a printed circuit board or an integrated circuit having complicated wiring is automatically performed by using this kind of device.

[0002]

2. Description of the Related Art With the increase in the scale of substrates and integrated circuits, enormous amounts of memory and processing time are required for the automatic design of wiring paths.

Therefore, a method of dividing a wiring target area into a plurality of rectangular areas and determining a wiring route for each of the divided areas is disclosed in Japanese Patent Laid-Open No. 1-137373 (invention title: automatic wiring method), Japanese Patent Application No. -320598 (Title of invention: Area division wiring method) and the like.

In these methods, when the net terminals to be connected are in different divided areas, a plurality of virtual relay terminals are set at the boundaries of the divided areas, and one of the relay terminals is selected from the net terminals in each divided area. The route to is independently determined (see FIGS. 11 and 12).

Normally, the relay terminal closest to the net terminal is selected (see FIG. 12). However, if the terminal has already been used for another route, the next closest relay terminal is selected.

[0006]

When the wiring target area is divided into a large number and the net terminals at the route start point and the end point are separated from each other, the wiring process fails due to another area crossing the route. This failure also occurs depending on how to select the relay terminal.

Therefore, in the prior art, the wiring rate (the number of wirings for which route determination has been successful divided by the total number of wirings) is 80-
Only 90%. Therefore, it is necessary to manually perform the rest, and as a result, it takes one to two weeks to determine all the wiring routes in a large-scale circuit.

The present invention has been made in view of the above conventional circumstances. And the objective is to provide the apparatus which can raise a wiring rate significantly.

[0009]

In order to achieve the above object, the device according to the first invention is configured as shown in FIG. 1, and the device shown in FIG. Means 10, general route determining means 12 for determining a rough wiring route on the compressed area, wiring area expansion means 14 for expanding the area where the rough wiring path is determined to the size before compression, and expansion Wiring area dividing means 16 for dividing the divided area, and final route determining means 18 for determining a final wiring path from the rough wiring paths on each of the divided partial areas.
And.

The device according to the second invention is configured as shown in FIG. 2, and the device shown in FIG. 2 is designated as a partial region designating means 20 for designating a part of a wiring target region according to a predetermined condition. A partial area compression unit 22 for compressing a partial area, a rough route determination unit 24 for determining a rough wiring route on the compressed region, and a partial region for which a rough wiring route is determined to a size before compression. A partial area expanding means 26 for expanding and a partial path determining means 28 for determining a final wiring path from an approximate wiring path for the expanded partial area.
And the remaining area route determining means 30 for determining the final wiring route for the wiring target region excluding the designated partial region.
And.

[0011]

In the first aspect of the present invention, the wiring target area is first compressed in either the horizontal direction or the vertical direction or bidirectionally, and the rough wiring route is determined on the area. Then, after the compressed area is restored to its original size, this area is divided, and the wiring route is finally determined for each divided region using a rough wiring route.

The wiring path on the compression area is disclosed in Japanese Patent Laid-Open No. 1-
It can be determined as shown in Japanese Patent No. 137373, and the wiring path on the area restored by extension can also be determined as shown in the same publication. In the second aspect, only a part of the wiring target area is compressed.

[0013]

EXAMPLE Referring to FIG. 3, a keyboard 32 and a mouse 34
Are connected to a display 36, and this display 36 is connected to a processing unit 38 of the computer main body.

The disk unit 40 and the memory 42 are accessed by the processing unit 38, and the data of the circuit for which the wiring path is to be determined is read from the disk unit 40 and expanded on the memory 42.

In FIG. 4, the operation of this embodiment is described with reference to a flow chart. First, the disk device 40 is accessed (step 400) and the circuit data is stored in the memory 4.
It is judged whether or not it can be expanded to 2 (step 40).
2).

At this time, when the judgment result that the expansion is possible is obtained (YES in step 402), the memory 42
It is determined whether the processing can be performed faster by dividing the wiring area and sequentially determining the wiring path for each divided area, rather than expanding all the circuit data and collectively determining the wiring path. (Step 404).

At this time, when it is determined that the former process is faster (NO in step 404),
All the circuit data are expanded in the memory 42 to collectively determine the wiring path (step 406), and the result is output to the disk device 40 (step 408).

If the circuit is large-scale and the data cannot be expanded in the memory 42 (NO in step 402), or if the area division is faster (step 404).
If YES, the wiring area is divided (step 42).
0), a wiring route is determined for each divided area (step 422).

However, when the circuit data cannot be expanded in the memory 42 (NO in step 402), the memory shortage is calculated (step 410). When this deficiency is larger than the prescribed amount, the entire wiring region is compressed (step 412), and when it is small, only a part (portion with low terminal density) is compressed (step 414). Further, when high speed processing is to be performed, the entire wiring area is immediately compressed.

Then, a wiring route is roughly determined for the compressed area (step 416), and thereafter, the area is expanded to its original size and restored (step 418), and then the above-described area division is performed. (Step 420) is started.

In FIG. 5, the operation of compression and expansion of the entire area is described. When area compression is performed as shown in FIG. 6 (compression to a size that can be expanded in the memory 42), terminals and a schematic wiring pattern ( The overlap occurs in the path) as shown in FIG. 5 (in FIG. 5, the image is vertically compressed in half and the 2n-th trace is merged with the 2n-1th trace).

In FIG. 7, the wiring path immediately after the extension is described, and then the area division (step 42) is performed.
0) and route determination processing for each divided area (step 422)
Then, the overlapped wiring patterns are distributed to the terminals in the vicinity thereof (see FIGS. 8 and 9).

In FIG. 10, the compression operation of the partial area is described (the size of the area to be compressed is determined in consideration of allowing the remaining areas to be collectively processed), and the compressed partial area and the uncompressed remaining area. The wiring paths of the above are separately determined (step 422).

As described above, when the circuit data cannot be expanded in the memory 42, the area of the circuit wiring is once compressed, and the wiring route is roughly determined on the area. Further, after the wiring area is expanded and restored to the original size, the area division is performed, and the final wiring path is determined based on the roughly determined path.

That is, after the wiring route is globally determined, its contents are examined locally for each divided area. Therefore, according to the present embodiment, the wiring rate can be significantly increased (almost 100%), and the circuit wiring design can be completed in a short period of time (which conventionally required 1 to 2 weeks is shortened to half a day). .

Further, when the size of the circuit data slightly exceeds the memory capacity, only the excess portion is compressed, so that the processing amount becomes small, so that the processing can be completed in a shorter time.

[0027]

As described above, according to the present invention, the wiring rate is significantly increased, so that the circuit wiring design can be efficiently completed in an extremely short time.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the first invention.

FIG. 2 is a diagram illustrating the principle of the second invention.

FIG. 3 is a diagram illustrating a configuration of an example.

FIG. 4 is a flowchart illustrating the operation of the embodiment.

FIG. 5 is an explanatory diagram of an operation of area compression and expansion.

FIG. 6 is an explanatory diagram of an operation of a region compression result.

FIG. 7 is an explanatory diagram of a wiring path immediately after expansion.

FIG. 8 is an explanatory diagram of a final wiring route determination operation.

FIG. 9 is an explanatory diagram of a final wiring route determining operation.

FIG. 10 is an explanatory diagram of the operation of partial region compression.

FIG. 11 is a flowchart illustrating a conventional technique.

FIG. 12 is an explanatory diagram of an operation of determining a wiring route.

[Explanation of symbols]

 32 keyboard 34 mouse 36 display 38 processor 40 circuit data storage display 42 circuit data expansion memory

Claims (2)

[Claims] 1. A wiring area compression means (10) for compressing an area to be wired, a rough route determination means (12) for determining a rough wiring path on the compressed area, and a rough wiring path is determined. Wiring area expansion means (14) for expanding the expanded area to the size before compression, and wiring area dividing means (16) for dividing the expanded area.
And a final route determining means (18) for determining a final wiring route from a rough wiring route on each of the divided partial areas. 2. A partial area designating means (20) for designating a part of a wiring target area according to a predetermined condition, and a partial area compressing means (2) for compressing the designated partial area.
2), a rough route determining means (24) for determining a rough wiring route on the compressed region, and a partial region expanding means (24) for stretching the partial region having the rough wiring route determined to a size before compression. 26), a partial route determining means (28) for determining a final wiring route from an approximated wiring route for the extended partial region, and a final wiring route for a wiring target region excluding the designated partial region. Remaining area route determining means (30) for determining
And a wiring route automatic designing device.