JPH04100260A - Semiconductor integrated circuit layout method and device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a semiconductor integrated circuit layout method and its device, and aims to reduce development man-hours and shorten the development period. After making a layout using basic cells of the same size, wiring each laid out cell and finding the actual wiring capacity of each wiring, find the load capacity of each basic cell, and calculate the load capacity of the basic cell with respect to the load capacity. The size is determined, simulation data is created from the size of each basic cell and each actual wiring capacitance, and the operating speed is checked based on the simulation data and test pattern data [Industrial Application Field] The present invention relates to a semiconductor integrated circuit layout method and its apparatus.

In recent years, while semiconductor integrated circuits have become larger in scale,
There is a need to shorten the development period. Therefore, it is necessary to perform efficient design by eliminating design changes based on the occurrence of errors between simulations performed at the logical design stage and simulations performed after layout.

[Background Art] Conventionally, in the logical design of semiconductor integrated circuits, provisional wiring is performed by predicting the placement position of each circuit (cell) whose size is determined. Then, they estimated the wiring capacity, number of fanouts, etc., added delay time to the circuit, and ran simulations to check whether the operating speed and functionality reached the expected values. If the expected value is not achieved, the logic is changed, the cell size is changed, etc.

Next, a layout is performed based on the logic data obtained from the logic design after the simulation. After laying out the layout, the actual wiring capacitance is determined based on the layout, and simulation data is created based on the actual wiring capacitance, the size of each cell, and the like. Then, a simulation is performed based on the simulation data and test pattern data to check the operating speed and functions, and it is determined whether there are any errors between the operating speed and functions obtained at the logic design stage.

[Problems to be Solved by the Invention] However, in layout, each cell is rarely placed in the position predicted at the logical design stage, and may be laid out in a position that is unexpectedly far away or close to the opposite position. It was happening a lot. Therefore, the wiring capacitance after layout differs significantly from the wiring capacitance estimated in logic design, causing problems in terms of operating speed and functionality. As a result, it becomes necessary to change the logic or modify the layout pattern at the location where the problem occurs, which poses a problem in shortening the development period.

The present invention has been made to solve the above-mentioned problems, and its purpose is to provide a semiconductor integrated circuit layout method and device that can reduce the number of development steps and shorten the development period. It is in.

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention in detail.

The basic cell placement means 1 inputs logic data 2 for which functional simulation has been completed, and uses the same logic data 2 to perform layout. At this time, the basic cell placement means 1 uses basic cells of the same size to be laid out. The wiring means 3 performs wiring processing on the laid out basic cells of the same size. The actual wiring capacitance calculating means 4 inputs the data of each wiring wired by the wiring means 3 and calculates the actual wiring capacitance of each wiring based on the same data.

The load capacitance calculating means 5 calculates the load capacitance of each basic cell laid out by the basic cell arranging means 1 based on the data of the actual wiring capacitance of each wiring calculated by the actual wiring capacitance calculating means 4. The size determining means 6 determines the size of each basic cell based on the load capacity data for each basic cell calculated by the load capacity calculation means 5, and changes the size of each basic cell that has been filled out by the basic cell placement means 1. do.

The simulation data creation means 7 performs a simulation based on the size data of each laid out basic cell determined by the size determination means 6 and the actual wiring capacitance data of each wiring calculated by the actual wiring capacitance calculation means 4. Create data.

The simulation means 8 performs an operation speed simulation based on the simulation data created by the simulation data creation means 7 and the test pattern data 9 prepared in advance.[Operation] Lays out each basic cell based on the logical data 2. At this time, when basic cells of the same size are laid out by the basic cell placement means 1 and each laid out basic cell is wired by the wiring means 3, the actual wiring capacitance calculation means 4 calculates the δ wiring. The actual wiring capacitance is calculated 1,
Subsequently, the load capacity calculation means 5 calculates the load capacity of each basic cell.

When the load capacity of each basic cell is determined, the size determining means 6
Accordingly, a basic cell of the optimum size for the load capacity of the basic cell is determined for each basic cell, and the size of each basic cell laid out by the basic cell placement means 1 is changed.

When the size of each basic cell according to the load capacity is determined, the simulation data creation means 7 generates data on the size of each basic cell and the actual wiring of each wiring determined by the actual wiring capacitance calculation means 4. Simulation data is created based on the data of the human body. Then, the simulation means 8 performs an operation speed simulation based on this simulation data and test pattern data 9 prepared in advance.

Therefore, the simulation data created based on the size of each basic cell and the actual wiring capacitance of each wiring corresponds to reality, and the precision of the layout work is high. As a result, during logic design, only functional simulations are performed; other simulations do not need to be performed, and post-layout simulations only include operational speed simulations, which greatly shortens the development period.

[Example] An example embodying the present invention will be described below with reference to the drawings.

FIG. 2 shows a system configuration diagram of a semiconductor integrated circuit layout device 11 consisting of a CAD device.
Enter. The layout device 11 has a function of performing processing such as layout data creation processing and simulation processing.

The simulation process includes a function simulation process and an operation speed simulation process based on the logical data 12. Functional simulation processing is a process in which simulation data is created using logical data obtained from temporary wiring at the logic design stage, and only functional simulation is performed using that data. Only static mode simulation is performed, and each basic Perform a simulation to see if the cell operates with the expected function 9 In this embodiment, the layout device 11 performs a functional simulation of the logical data 12, or another device performs a functional simulation of the logical data based on the logical data. 12, it is not necessary to perform this functional simulation.

On the other hand, the operation speed simulation (hereinafter referred to as speed simulation) processing is a simulation performed using the size and actual wiring capacity of each basic cell determined after basic cells are laid out based on the logic data 12. Simulate the dynamic operating speed of the cell.

Layout data creation process is thick (separate layout,
There are processing operations for verification, wiring capacity estimation, cell determination, and simulation data creation.

Layout processing is a process of laying out basic cells based on the logic data 12 checked in the functional simulation and wiring between each basic cell, and when laying out basic cells, basic cells of the same size are used for layout. do.

For example, in the logic design, inverters 21 to 23 shown in FIG.
When a logic circuit is designed and laid out based on the logic data, inverter cells 21a to 23a of the same size are used for the layout, as shown in FIG. Inverter cells 21a to 23 laid out
In this embodiment, the size of inverter cell INV1.a is determined by three sizes of inverter cells INV1. INV2. The largest size inverter cell INV3 from INV3 is used. Then, once the basic cells of the same size are laid out, wired and 1 to L4 are performed, this is stored in the storage device 13 as layout data.

The verification process is a so-called router check to check whether the wires are wired at correct intervals.

The wiring capacity estimation process calculates the actual wiring capacity of each wiring based on the layout data stored in the storage device 13, and stores the actual wiring capacity of each wiring in the storage device 13 as layout data. That is, in FIG. 4, the wiring L
The wiring capacitances of 1 to L4 are calculated. At this time, wire 2
The wiring capacitance is large, and the wiring L3. It can be seen that the wiring capacitance of L4 is small.

The cell determination process is a process of changing the size of basic cells of the same size laid out by the layout process to a size corresponding to the load capacity, and is a process of changing the size of basic cells of the same size laid out by the layout process, and changing the size of each basic cell based on the data of the actual wiring capacity of each wiring stored in the storage device 13. Calculate the load capacity for the basic cell. That is, in FIG. 4, the load capacitance of the inverter cell 21a is composed of the wiring capacitance of the wiring 2 and the input load capacitance of the inverters 22a and 23a, and the load capacitance of the inverter cell 22a is the wiring capacitance of the wiring 3 and the wiring capacitance of the wiring 3. Consists of the input load capacitance of connected cells. Further, the load capacitance of the inverter cell 23a consists of the wiring capacitance of the wiring 4 and the input load capacitance of the cell connected to the wiring 4. Then, the size of the basic cell is determined according to the load capacity, and the size of the laid out basic cell is changed. In FIG. 4, since the load capacity of the inverter cell 21a is large, the sixth
As shown in the figure, a cell with a large driving force, ie, the largest inverter cell INV3 shown in FIG. 5, is used to drive the net. On the other hand, inverter cell 22a
, 23a are both small, so a small driving force is required to drive the net, as shown in FIG.
VI is used.

Then, as shown in FIG. 6, final layout data is created based on the data of the basic cell whose size has been changed and the data of the actual wiring capacitance of each wiring, and is stored in the storage device 13.

In the simulation data creation process, the final layout data stored in the storage device 13 is read out, and simulation data is created based on data such as the actual wiring capacity of each wiring and the size of the basic cell. This simulation data is then used in the speed simulation process described above.

In this way, in this example, the simulation data is data based on each basic cell whose actual wiring capacitance and size are determined based on the load capacitance, so the data corresponds to the actual situation, and the layout data has extremely high accuracy and reliability. Become something.

Furthermore, in this embodiment, when laying out basic cells based on logical data, basic cells of the same size are placed and the size is changed after calculating the load capacity.
This eliminates the need to repeat the work of arranging basic cells of a size determined by logic design during layout and then changing the size depending on the load capacity.

Furthermore, since the basic cells are laid out with the same size, only functional simulations are performed for logical data, while post-layout simulations are only speed simulations, which reduces development man-hours and shortens the development period. can be achieved.

Further, in this embodiment, the maximum size basic cells of the same size are used in the layout, so that even if the size of the basic cells is changed, it is easy to change the size in the direction of reduction or change the arrangement.

It should be noted that the present invention is not limited to the above-mentioned embodiment. For example, in the above-mentioned embodiment, only speed simulation was performed in the post-layout simulation, but function simulation may also be performed in order to further improve accuracy and reliability. good.

Further, in the above embodiment, the size of the basic cells to be laid out is the largest, but the point is that it is sufficient that the basic cells of the same size are laid out, and the basic cells are not limited to the largest size.

Furthermore, although the basic cells of the inverter were explained in the above embodiments, the same applies to the basic cells of various gate circuits such as AND circuits and NOR circuits, and the same size is laid out for each gate circuit. , resized based on load capacity.

[Effects of the Invention] As described in detail above, the present invention has the excellent effect of reducing the number of steps for developing a semiconductor device and shortening the development period.

[Brief explanation of drawings]

Fig. 1 is a principle explanatory diagram showing the principle of the present invention, Fig. 2 is a system configuration diagram of a layout device for explaining an embodiment of the present invention, and Fig. 3 is a diagram for explaining logical data at the logical design stage. circuit diagram, Figure 4 is an explanatory diagram to explain the basic cell layout based on logic data, Figure 5 is an explanatory diagram to explain a library of inverter cells of different sizes, and Figure 6 is an explanatory diagram to explain the size determination. FIG. 7 is a circuit diagram based on the layout data after the size has been determined. In the figure, 1 is basic cell placement means, 2 is logical data, 3 is wiring means, 4 is actual wiring capacity calculation means, 5 is load capacity calculation means, 6 is size determination means, 7 is simulation data creation means, and 8 is simulation means; 9 is test pattern data; Figure 5: Circuit diagram for explaining logical data Figure 5: Circuit diagram based on layout data Figure 5: Explanatory diagram showing the layout of basic cells Figure 5: Explanatory diagram showing basic cells of different sizes

Claims (1)

[Claims] 1. After laying out basic cells to be laid out based on logical data using basic cells of the same size, wiring each laid out cell, and determining the actual wiring capacity of each wiring. , find the load capacity of each basic cell, determine the size of the basic cell with respect to the load capacity, create simulation data from the size of each basic cell and each actual wiring capacity, and combine the simulation data and test pattern data. A layout method for a semiconductor integrated circuit, characterized in that the operating speed is checked based on the following. 2. Basic cell placement means (1) that uses basic cells of the same size to lay out the basic cells laid out based on the logical data (2), and wiring that performs wiring processing for the laid out basic cells of the same size. means (3); an actual wiring capacitance calculation means (4) for calculating the actual wiring capacitance of each wiring wired by the wiring means (3); and each wiring calculated by the actual wiring capacitance calculation means (4). load capacity calculation means (5) for calculating the load capacity of each basic cell of the same size based on the actual wiring capacity of the cell; size determining means (6) for determining the size of each basic cell, and the size determining means (6);
simulation data creation means (6) for creating simulation data based on data on the size of each laid out basic cell determined by step 6) and data on the actual wiring capacitance of each wiring calculated by the actual wiring capacity calculation means (4); 7
), and a simulation means (8) for performing an operation speed simulation based on the simulation data created by the simulation data creation means (7) and test pattern data prepared in advance. Device.