JP3037787B2 - Logic simulation method and logic simulation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation method taking into account the dynamic detailed delay value of an LSI (semiconductor integrated circuit device) whose delay value changes depending on the state around a logic gate of interest or an input signal waveform. Logical stain
To a simulation device .

[0002] With the recent advancement of LSI technology, higher speed, and larger scale, improvement of reliability of tester data and improvement of simulation accuracy are required. For this reason, it is necessary to obtain a value along the actual circuit as the delay value.

[0003]

2. Description of the Related Art Conventionally, circuit data in a logic simulation of an LSI, that is, a delay value of a so-called simulation model has been statically calculated. That is, the switching state of the logic gate ahead of the logic gate output of interest,
It is possible to calculate delay values for all combinations in consideration of the tie-up situation of other output nets of the target logic gate output.

Assuming that the number of logic gates ahead of the logic gate output of interest is X and the number of outputs of the logic gate of interest is Y,
The number TO of all combinations attached to one output of a logic gate is

[0005]

## EQU1 ## TO = 2 ^X × 2 ^(Y-1) × 2 The term “2 ^X ” indicates whether or not the X logic gates are switched. The term “2 ^(Y−1) ” indicates the state of the other output of the logic gate of interest. Indicates that there are two levels of one output of the target logic gate.

However, in the above-mentioned conventional method, since the delay values of all combinations considering each situation are stored, there is a problem that the data amount becomes enormous.
Also, a plurality of delay values are added to the output of the logic gate of interest, and the condition is the number and state of the logic gates ahead of the logic gate output of interest, and the other output nets of the logic gate output of interest. Since it changes depending on the shape (whether or not it is doted) and its state, it is necessary to store the delay value use condition together with the delay value, and the data amount further increases.

Therefore, conventionally, when the delay value changes due to the switching of the logic gate preceding the logic gate output of interest, a value that uniformly approximates the switching probability has been used.

However, since the switching probabilities are uniformly approximated, there are a plurality of logic gates ahead of the logic gate output of interest, and even if all the logic gates ahead of the logic gate output of interest are switched, only one is switched. Regardless of whether or not the delay value is the same.

In the case where the delay value changes depending on the state of the other output of the logic gate output of interest, for example, when the other output net of the logic gate output of interest is dot, the probability of tie-up is high. Was used.

However, since the tie-up probability is uniformly approximated, the same delay value is obtained whether or not the other output nets of the target logic gate are tied up or not.

The dullness of the signal waveform input to the target logic gate cannot be approximated by predicting the degree of the dullness, and cannot be considered by the conventional method.

[0012]

Therefore, in the conventional method, if the signal passes through the same signal propagation path, the switching status of the logic gate ahead of the logic gate output of interest and the timing of other output nets of the logic gate output of interest are determined. Because the same delay value cannot be considered regardless of the up situation and the dullness of the signal waveform input to the target logic gate, the simulation accuracy does not improve and the reliability of the tester data does not increase. Had occurred.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and has been developed in accordance with a real LSI in consideration of a state around a logic gate of interest or a signal waveform input to the logic gate of interest. It is an object of the present invention to obtain a detailed delay value, improve the accuracy of logic simulation, and improve the reliability of tester data.

[0014]

To solve the above problems [Means for Solving the Problems] The first invention is to sequentially input LSI of the circuit data, and inputs the signal data for checking the operation input to the LSI sequentially, In a logic simulation method in which each logic gate in circuit data is operated in a pseudo manner to obtain a change in the output signal of the logic gate and a change in the output signal of each output terminal, the logic gate for stopping the logic simulation is stored in advance. Place, continuously performing logic simulation to calculate the change in the output signal of the logic gate based on the circuit data when the logic gate to be calculated the output signal change is not preset logic gates, calculate an output signal change If the logic gate to be executed is a preset logic gate, the logic simulation is interrupted and A dynamic delay value is calculated in consideration of a state around the logic gate or an input signal waveform, and a logic simulation is restarted based on the calculated dynamic delay value to determine a change in an output signal of the logic gate. It was calculated.

[0015] The second invention is to sequentially input LSI of the circuit data, perform logic simulation signal data for checking the operation input to the LSI are sequentially input, each logic in the circuit data A logic simulator in which a gate is operated in a pseudo manner to obtain a change in the output signal of the logic gate and a change in the output signal of each output terminal.
In Shon device determines a stop circuit storage unit for previously storing a logic gate to stop the logic simulation, whether the logic gates are to be calculated the output signal change to match the stored logic gate stop circuit storage unit A determination unit, a delay storage unit that stores a delay value in the circuit data, and a state around the logic gate stored in the stop circuit storage unit based on the match determination by the determination unit or an input signal waveform, and A dynamic delay calculator that calculates a dynamic delay value of the logic gate; and a delay value stored in the delay storage unit based on the mismatch determination by the determination unit, and is calculated by the dynamic delay calculator based on the match determination. And a selector for selecting the selected dynamic delay value, and inputting the data and signal data of each logic gate in the circuit data. A logic simulating unit that receives the output of the selector and calculates a change in the output signal of each logic gate and a change in the output signal of each output terminal; and temporarily suspends the logic simulating unit based on the matching determination by the determining unit. ,
A stop / start controller for restarting the logic simulator based on the delay calculation of the dynamic delay calculator is provided.

[0016]

Therefore, according to the first aspect of the present invention, during execution of the logic simulation, when the logic gate of interest becomes a previously stored logic gate, the logic simulation is interrupted, and the state around the logic gate, that is, the logic gate, Considering the switching status of the logic gate ahead of the output and the tie-up status of other output nets of the logic gate output of interest, or considering the signal waveform input to the logic gate of interest, A delay value is calculated. Then, the logic simulation is restarted based on the calculated dynamic delay value, and the change in the output signal of the logic gate is calculated. Therefore, the accuracy of the logic simulation is improved, and the reliability of the tester data is improved. .

According to the second aspect of the present invention, when the determination section determines that the logic gate whose output signal change is to be calculated does not match the logic gate stored in the stop circuit storage section, the selector stores the logic gate in the delay storage section. The selected delay value is selected, and the logic simulating unit calculates the change of the output signal of each logic gate and the change of the output signal of each output terminal based on each logic gate in the circuit data, the signal data, and the delay value of the delay storage unit. Is done.

When the determination section determines that the logic gate whose output signal change is to be calculated matches the logic gate stored in the stop circuit storage section, the operation of the logic simulation section is temporarily stopped by the stop / start control section. At the same time, the dynamic delay value of the logic gate is calculated by the dynamic delay calculation unit in consideration of the state around the logic gate stored in the stop circuit storage unit or the input signal waveform. Then, the dynamic delay value calculated by the dynamic delay calculation unit is selected by the selector and output to the logic simulation unit. Then, the logic simulation unit is restarted by the stop / start control unit based on the delay calculation of the dynamic delay calculation unit, and each logic gate,
The change of the output signal of each logic gate and the change of the output signal of each output terminal are calculated based on the signal data and the dynamic delay value of the dynamic delay calculator.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a logic simulation of the present embodiment.
Device (hereinafter referred to as a logic simulator) 10
FIG. 2 shows a flowchart of tester data creation using the logic simulator 10.

As shown in FIG. 2, tester data is created by first creating a simulation model (circuit data) in which a static delay value is set for each logic gate in step 1 as in the prior art, and then in step 2. In addition to executing the logic simulation, the logic simulation is temporarily suspended in step 3 where a detailed delay value (hereinafter referred to as a dynamic delay value) is required, and a dynamic delay calculation is performed. To restart the logic simulation.

Then, in step 4, after the logic simulation is completed, tester data is created based on the simulation result. Next, the logic simulator 1
0 will be described with reference to FIG.
0 is a static delay table 1 as input units 11 and 12, a stop circuit storage unit 13, a determination unit 14, and a delay storage unit.
5, a dynamic delay calculating section 16, a selector 17, a logic simulating section 18, a signal change output section 19, a stop / start control section 20, and the like.

The input section 11 outputs L from the signal data file 5
Signal data for inputting to the SI and checking its operation are sequentially input and output to the logic simulator 18.

The input unit 12 outputs L from the circuit data file 6
Circuit data consisting of SI logic gates, gate characteristics, connections, delay values, etc. are sequentially input. Then, the input unit 12
Indicates data of the logic gates in the determination unit 14 and the logic simulation unit 18, data of the static delay value of each logic gate in the static delay table 15, and gate characteristics / connections and the like in the dynamic delay calculation unit 16. Is output.

The stop circuit storage unit 13 is preliminarily input from an external input device with data of a logic gate for temporarily stopping the logic simulation, and the data of the stop logic gate is sent to the determination unit 14. Is output.

The determination section 14 determines whether or not the data of the logic gate to be sequentially calculated via the input section 12 for which the output signal change is to be calculated matches the stop logic gate from the stop circuit storage section 13. Then, the determination result is output to the dynamic delay calculation unit 16, the selector 17, and the stop / start control unit 20.

The dynamic delay calculator 16 includes the input unit 1
2 as well as data such as gate characteristics and connection of the LSI, and a simulation result at that time from the logic simulation unit 18 described later, that is, the state around the logic gate of interest and the input signal waveform and the like. Data has been entered. When a match is determined by the determination unit 14, the dynamic delay calculation unit 16 determines the data such as the gate characteristics and connection of the LSI, the state around the logic gate (stop logic gate) of interest, and the input signal. The dynamic delay value of the logic gate is calculated based on data such as a waveform, and is output to the selector 17.

The calculation of the dynamic delay value by the dynamic delay calculating section 16 is based on the fact that the delay value of one output terminal of the stop logic gate is determined by the number of logic gates connected to the output terminal, the switching number thereof, This is because the delay value of the stop logic gate varies depending on the tie-up state of the other output terminal of the logic gate or the dull state of the input signal of the stop logic gate.

FIG. 4 shows the relationship between the logic gate output of interest and the element in which the delay value changes. The logic gate 41 is the logic gate of interest, and the output terminal 41c
Is the output terminal of interest, the output terminal 41
Logic gates 43 to 46 are connected to the end of c.
The other output terminal 41 of the output terminal 41c of the logic gate 41
d is tied up when the other output terminal 41d
And the output of the logic gate 42, which is an OR dot 48, is already "H" and this net is fixed at "H", and the output of the other output terminal 41d is changed from "L" to "H" or "H".
The change from “L” to “L” indicates a state that is irrelevant.

FIG. 5 shows the relationship of the change in the delay value due to the switching of the logic gate ahead of the logic gate output of interest. Assuming that the logic gate 41 is the logic gate of interest and the output terminal 41e is the output terminal of interest, logic gates 43 to 46 are connected before the output terminal 41e. Therefore, the amount of change in the delay value of the output terminal 41e of the logic gate 41 due to the switching of each of the logic gates 43 to 46 is calculated by the logic gate 4
Assuming that all of 3 to 46 have the same size (equal in resistance, capacitance, etc.), it can be obtained by (change in delay value due to switching of one logic gate) × (number of logic gates switched).

Therefore, in the case of FIG. 5A, only the logic gate 43 switches and the number of switching is "1".
In the case of FIG. 5B, the logic gates 43 to 46 switch and the number of switching becomes “4”. Therefore, the change of the delay value becomes larger in the case of FIG. Propagation slows down.

FIG. 6 shows a change in the delay value of the logic gate output of interest due to the dulling of the input signal. FIG. 6A shows a case where the dullness of the input signal is small, and FIG. 6B shows a case where the dullness of the input signal is large.
At this time, if the conditions other than the input signal are the same, FIG.
6A and 6B, the delay value that is not affected by the dullness of the input signal is Tpd0. Then, FIG.
Then, the delay value due to the dullness of the input signal is Tpd1, and FIG.
In (b), the delay value due to the dullness of the input signal is Tpd2
The change in the delay value increases as the dullness of the input signal increases.

Further, the selector 17 selects the data of the static delay value of each logic gate stored in the static delay table 15 on the basis of the discrimination by the discriminating unit 14 and based on the discrimination by the discriminating unit 14 on the basis of the discrimination. Select the dynamic delay value calculated by the dynamic delay calculation unit 16,
Output to the logic simulator 18.

The logic simulation unit 18 receives the signal data input through the input unit 11, the data of the logic gate input through the input unit 12, and the output of the selector 17, and executes the logic simulation. Then, each logic gate is operated in a simulated manner, and the output signal change of each logic gate and the output signal change of each output terminal are obtained.

The signal change output section 19 and executes the strobe processing for comparing an output expected value in the simulation result and the signal data of the logic simulation unit 18, and outputs a trace list 21 executes the tracing process.

When the judgment is made by the judgment unit 14, the stop / start control unit 20 suspends the operation of the logic simulation unit 18, and the dynamic delay calculation unit 16 calculates the dynamic delay value. Then, the logic simulator 18 is restarted.

FIG. 3 is a flowchart showing processing executed by the logic simulator 10 configured as described above. First, when performing a logic simulation,
A logic gate that focuses on the stop circuit storage unit 13 in advance, ie,
Data of a stop logic gate for stopping the logic simulation is input from an external input device.

When the logic simulation is started, the judgment unit 14 compares the data of the logic gate input via the input unit 12 with the data of the stop logic gate of the stop circuit storage unit 13 in step 31. If the determination unit 14 determines that the two match, the process proceeds to step 32 and the stop / start control unit 20 causes the logic simulation unit 18 to execute.
Operation is suspended.

Then, in the next step 33, the dynamic delay calculating section 16 determines the logic gate based on the data such as the gate characteristics and connection of the LSI, the state around the stop logic gate, and the input signal waveform and the like. Is calculated, and this dynamic delay value is output to the selector 17.

When the dynamic delay value is calculated by the dynamic delay calculating section 16, the stop / start control section proceeds to step 34.
The logic simulation unit 18 is restarted by 20, and the dynamic delay value is selected by the selector 17 and output to the logic simulation unit 18.

In the next step 35, the logic simulation unit 1
8, a signal change operation is executed based on the signal data, the logic gate data, and the dynamic delay value, and the output signal change of the logic gate (stop logic gate) is calculated.

If it is determined in step 31 that the two do not match, the process proceeds to step 39 where the selector 17 selects the delay value stored in the static delay table 15 and performs a logic simulation. Output to the logic unit 18 and in step 35 the logic simulation unit 1
8, a signal change operation is executed based on the signal data, the logic gate data, and the delay value of the static delay table 15 , and the output signal change of the logic gate is calculated.

[0042] After this, the signal change output section 1 in Step 36
9, the strobe processing for comparing the simulation result of the logic simulation unit 18 with the expected output value of the signal data is executed. In the next step 37, the trace processing is executed and the trace list 21 is output.

If it is determined in step 38 that there is an unprocessed logic gate, the process returns to step 31 and the processes after step 31 are repeatedly executed. As described above, in this embodiment, the data of the stop logic gate for stopping the logic simulation, that is, the data of the logic gate requiring a detailed delay value is stored in the stop circuit storage unit 13 in advance, and the output signal change is determined by the determination unit 14. When it is determined that the logic gate for which is calculated matches the stored stop logic gate, the operation of the logic simulation unit 18 is temporarily stopped by the stop / start control unit 20. Then, the dynamic delay calculating section 16 compares the data such as the gate characteristics and connection of the LSI with the logic gate of interest (stop logic gate).
When the dynamic delay value of the stop logic gate is calculated based on the surrounding state and data such as the input signal waveform,
The logic simulation unit 18 is restarted, the selector 17 outputs a dynamic delay value, and the logic simulation unit 18 calculates a change in the output signal of the stop logic gate based on the dynamic delay value. When the determination unit 14 determines that the logic gate whose output signal change is to be calculated does not match the stored stop logic gate, the selector 17 determines the static state of each logic gate stored in the static delay table 15. A delay value is selected, and a change in the output signal of each logic gate is calculated by the logic simulator 18 based on the static delay value.

Therefore, a more detailed delay value along the actual LSI can be obtained, and the accuracy of logic simulation can be improved. Further, by improving the accuracy of the logic simulation, the reliability of tester data created based on the simulation result can be improved.

In this embodiment, the logic simulation is temporarily stopped to calculate a dynamic delay value only for a logic gate requiring a detailed delay value, and the logic simulation is restarted based on the dynamic delay value. As a result, it is possible to prevent an increase in the data amount and to suppress an increase in the processing time of the logic simulation.

In this embodiment, the dynamic delay calculating section 16
Is calculated based on the state around the logic gate of interest and the data of the input signal waveform, but only the state around the logic gate of interest or the input signal The calculation may be performed based only on the waveform data.

In this embodiment, during the execution of the logic simulation, when the logic gate of interest becomes the logic gate, the logic simulation is interrupted, the dynamic delay value of the logic gate of interest is obtained, and the obtained dynamic delay value is obtained. The logic simulation is restarted based on the delay value and the change in the output signal of the logic gate is calculated to generate tester data. However, after the logic simulation is completed, signal propagation that requires a detailed delay value is performed. With respect to the path, tester data may be created by calculating a detailed delay value of each logic gate constituting the signal propagation path by calculation.

[0048]

As described in detail above, according to the present invention,
A more real LSI in consideration of the state around the logic gate of interest or the signal waveform input to the logic gate of interest
In this case, a detailed delay value can be obtained in accordance with the above, and there is an excellent effect that the accuracy of logic simulation can be improved and the reliability of tester data can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a logic simulator according to one embodiment.

FIG. 2 is a flowchart showing LSI tester data creation.

FIG. 3 is a flowchart showing processing of a logic simulator.

FIG. 4 is a diagram illustrating a relationship between a target logic gate output and an element whose delay value changes.

FIGS. 5A and 5B are diagrams showing a signal change of a subsequent logic gate due to a signal change of a target logic gate output.

6A and 6B are diagrams showing a change in an output signal due to a dull input signal of a target logic gate, wherein FIG. 6A shows a case where the dullness of the input signal is small, and FIG. 6B shows a case where the dullness of the input signal is large. Show.

[Explanation of symbols]

 Reference Signs List 5 signal data file 6 circuit data file 10 logic simulator 13 stop circuit storage unit 14 determination unit 15 static delay table as delay storage unit 16 dynamic delay calculation unit 17 selector 18 logic simulation unit 20 stop / start control unit 21 trace list

Continuation of the front page (56) References JP-A-4-256069 (JP, A) JP-A-4-205188 (JP, A) JP-A-4-156676 (JP, A) JP-A-3-1522673 (JP , A) JP-A-3-58279 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 17/50

Claims (2)

(57) [Claims] 1. A while sequentially input LSI of the circuit data, the signal data for checking the operation input to the LSI are sequentially input, by artificially operating each logic gate in the circuit data the logic gate In the logic simulation method in which the output signal change of the output signal and the output signal change of each output terminal are obtained, a logic gate for stopping the logic simulation is stored in advance, and a logic gate to calculate the output signal change is set in advance. said circuit data when not a logic gate
The logic gate interrupt the logic simulation when calculating the change in the output signal of the logic gate to continue performing logic simulation, logic gates should calculate an output signal change is preset logic gates based on A dynamic delay value is calculated in consideration of the surrounding state or the input signal waveform, and a logic simulation is restarted based on the calculated dynamic delay value to calculate a change in the output signal of the logic gate. A logic simulation method characterized by doing so. With wherein inputting the LSI of the circuit data sequentially executes the logic simulation signal data for checking the operation input to the LSI are sequentially input,
A logic for stopping a logic simulation in a logic simulation apparatus in which each logic gate in circuit data is operated in a pseudo manner to obtain a change in an output signal of the logic gate and a change in an output signal of each output terminal. A stop circuit storage unit (13) for storing gates in advance, and a determination unit (14) for determining whether a logic gate for which an output signal change is to be calculated matches a logic gate stored in the stop circuit storage unit (13). ), A delay storage unit (15) for storing a delay value in the circuit data, and a state around the logic gate stored in the stop circuit storage unit (13) based on a match determination by the determination unit (14). A dynamic delay calculator for calculating a dynamic delay value of the logic gate in consideration of an input signal waveform; A selector (17) for selecting the delay value stored in the delay storage unit (15) based on the match determination and selecting the dynamic delay value calculated by the dynamic delay calculation unit (16) based on the match determination.
And a logic for inputting the data and signal data of each logic gate in the circuit data and inputting the output of the selector (17) to calculate the change of the output signal of each logic gate and the change of the output signal of each output terminal. Simulator (18)
And temporarily suspends the logic simulation unit (18) based on the match determination by the determination unit (14), and restarts the logic simulation unit (18) based on the delay calculation of the dynamic delay calculation unit (16). A logic simulation device comprising a stop / start control unit (20) for causing the stop / start control unit (20).