JP2002108966A - Circuit analyzer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce unwanted power consumption in LSI operation by analyzing the spot of great through delay and the spot of the high amplification factor of through delay inside an LSI circuit in the design of the LSI circuit. SOLUTION: A net list is read and while utilizing output data from a through delay calculating means calculating and outputting the calculation value of through delay in the input/output terminal of a cell, a terminal having the greater calculation value of through delay than a designated value is retrieved. Then, data related to this terminal and this calculation value are outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an LSI (Large).
The present invention relates to an apparatus related to circuit and layout verification in e-scale integration (large-scale integrated circuit) design.

[0002]

2. Description of the Related Art In LSI circuit design, an important requirement is to avoid unnecessary power consumption. Here, conventionally, software dedicated to power consumption estimation is often used. For example, simulation is performed by inputting a number of appropriate simulation patterns into a netlist or the like. In the simulation, for example, the number of toggles of each node is counted, and a location where power consumption is abnormally high is specified.

[0003] Therefore, it greatly depends on (the number and contents of) simulation patterns. However,
There is a limit to the number and content of simulation patterns,
At present, defective points (abnormal power consumption points) have not been sufficiently extracted.

[0004]

SUMMARY OF THE INVENTION According to the present invention, in an LSI circuit design, a portion having a large through delay and a portion having a high amplification factor of a through delay in an LSI circuit are statically analyzed, and the LSI circuit is designed to operate at a time of LSI operation. It is intended to reduce unnecessary power consumption.

[0005]

SUMMARY OF THE INVENTION The present invention has been made to achieve the above object. The slew delay analyzing means according to claim 1 of the present invention uses the output data from the slew delay calculating means for reading a netlist, calculating a calculated slew delay value at an input / output terminal of a cell, and outputting the calculated value. , A terminal whose calculated value of the through delay is larger than the first specified value, and outputs data relating to the terminal and the calculated value.

According to a second aspect of the present invention, the through delay analyzing means reads the netlist, calculates a through delay calculation value at the input / output terminal of the cell, and outputs the data from the through delay calculating means. Utilizing (1) the calculated value of the through delay of the output terminal in the cell is larger than the calculated value of the through delay of the input terminal. (2) In the cell, the calculated value of the through delay of the output terminal is the input terminal. And the difference is larger than the second specified value, or (3) in the cell, the calculated value of the through delay of the output terminal is larger than the calculated value of the through delay of the input terminal. A cell that satisfies any of the above conditions (1), (2) or (3) and that has an input terminal and an output terminal that are large and whose magnification is larger than the third specified value is searched for. And it outputs the data according to the calculated value.

According to a third aspect of the present invention, a netlist tracing means reads a netlist based on any one of the terminal data of the output of the first aspect, and further reads the netlist in an upstream direction. The data is traced toward the output terminal, and the data relating to the output terminal and the input terminal corresponding to the output of claim 2 is searched upstream, and the data relating to the terminal is output.

According to a fourth aspect of the present invention, there is provided a loop circuit delay calculating means for reading a netlist, calculating a calculated value of a through delay at an input / output terminal of a cell, and outputting the calculated value. When calculating the through delay calculation value in the above, if it is determined that the terminal is a part of the loop circuit, the calculation value of the through delay at one round of the loop circuit is recalculated, and the through delay at the recalculation is calculated. If the calculated value has increased, the data relating to the loop circuit, the terminal and the calculated value is output.

[0009]

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 8 shows an embodiment of a hardware configuration of a system device for realizing the present invention. The device is equipped with a CAD system in LSI design. For example, UNIX
(Registered trademark) computer 52. In FIG. 8, software (program code) relating to a system for realizing the present invention is stored on a magnetic disk 54, mounted on a memory 56 in response to a request from a system user, and externally input control commands 58. It operates in accordance with the operation instruction of the mouse device 60 and the predetermined information is displayed on the display device 64.
To be displayed. Result output (output 1, output 2,
Output 3 and output 4) file, netlist file,
The through delay library and the like are held on the magnetic disk 54, and are mounted on the memory 56 according to a request of software (program code) related to the system for realizing the present invention or a request of the system user. And is again held on the magnetic disk 54.

FIG. 1 shows an outline of the overall configuration and operation flow of a preferred embodiment according to the present invention. In FIG. 1, the netlist 2, the through delay library 4, the result output file 6, and the result output file (after sorting) 8
Is a computer file recorded on the magnetic disk 54. The input unit 12, the through delay calculating unit 14, the loop circuit delay calculating unit 14 ', the through delay analyzing unit 16, the netlist tracing unit 18 and the sorting unit 20 shown in FIG. This is realized by mounting the program code and controlling and operating by a CPU (central processing unit) 70.

Next, an outline of the overall configuration and operation flow of FIG. 1 will be described.

First, the input means 12 reads the through delay library 4 and the netlist 2. Next, based on the through delay library 14 read by the input means 12, the through delay calculation means 14 calculates one or more of the plurality of cells constituting the netlist 2 similarly read by the input means 12, respectively. Calculate the value of the through delay at the terminal of.

The above-described calculation of the through delay value is a known conventional technique. Further, the netlist 2 may be a netlist with capacitance and resistance (for example, a SPICE netlist). Rather, the netlist with capacitance and resistance can be more accurately verified by the processing according to the present invention.

(First Embodiment) In the through delay analyzing means 16, first, the through delay calculating means 14
The terminal having the through delay value calculated in the step is searched for a terminal whose through delay value (calculated value) is larger than the specified value. The search result is output to the result output file 6 as “output 1”.

(Second Embodiment) The through-delay analyzing means 16 further outputs the output of each cell in the data group relating to the terminal (provided with the through-delay value) calculated by the through-delay calculating means 14. Focus on the through delay value of the terminal and the through delay value of the input terminal. When the slew delay value of the output terminal of each cell is larger than the slew delay value of the input terminal, the slew delay value of the output terminal of each cell is larger than the slew delay value of the input terminal, and the difference is larger than the specified value Search for a cell whose through delay value at the output terminal of each cell is larger than the through delay value at the input terminal and whose magnification is larger than the specified value. The search result is output to the result output file 6 as “output 2”.

(Third Embodiment) The subsequent netlist tracing means 18 traces the netlist 2 from the position detected in the output 1 in the upstream direction,
A portion corresponding to the output 2 is detected at the upstream side. The detection result is output to the result output file 6 as “output 3”.

(Fourth Embodiment) A function of the following means (loop circuit delay calculating means 14 ') is added to a known prior art through delay calculating means 14.
That is, when calculating a through delay value at each terminal, it is first determined whether or not the terminal is part of a loop circuit (including a sequential circuit). In the case of a loop circuit, the through delay value after one round of the loop circuit is recalculated, and if the through delay value has increased, its terminal is detected. The search result is output to the result output file 6 as “output 4”.

The output 1, output 2,
The results of output 3 and output 4 are appropriately sorted (rearranged) as appropriate, and the result is output to a result output file (after sorting).
Output to

{First Embodiment} FIG. 2 is a flowchart showing a main part of the operation of the through delay analysis means 14 according to the first embodiment of the present invention.

Step S02: Through delay calculating means 14
It is determined whether or not the through delay value (calculated value) is larger than the designated value K at the terminal provided with the through delay value calculated in. The designated value K may be given in advance, or may be input before processing by the mouse device 60 of the computer 52 or the like. If it is larger, the process proceeds to step S04.

Step S04: "Output 1" is output.
An example of the contents of the output 1 is shown in FIG. That is, data of terminal ID (identifier), specified value K, and calculated value are provided. Here, “terminal ID” indicates an identifier of a terminal (the same applies hereinafter).

The operation shown in the above flowchart is performed for all the terminals having the through delay value.

{Second Embodiment} FIG. 3 is a flowchart showing the main part of the operation of the through delay analysis means 14 according to a second embodiment of the present invention.

Step S12: The slew delay value (ots) of the output terminal of each cell and the slew delay value (it) of the input terminal of each cell
Focusing on s), it is determined whether or not ots is greater than its. Only when larger, the process proceeds to step S14.

Step S14: Data indicating the content of "with reason" is temporarily stored. "With reason"
This is temporary storage data indicating that there is a reason to output to output 2 (the reason is).

Step S16: It is determined whether or not ots is larger than "its" and whether the difference is larger than the designated difference value (K1). That is, it is determined whether the following equation 1 is true or false.

Ots-its> K1 The difference designation value K1 may be given in advance, and
May be input before processing by the mouse device 60 or the like.
Only when it is larger (true), the process proceeds to step S18.

Step S18: Data indicating the content of "with reason" is temporarily stored. "With reason"
This is temporary storage data indicating that there is a reason to output to output 2 (the reason is).

Step S20: Whether ots is larger than its and whether the magnification is larger than the designated magnification value (K2)
Is determined. That is, it is determined whether the following equation 2 is true or false.

## EQU2 ## (ots) / (its)> K2 The designated magnification value K2 may be given in advance, and
It may be input before the processing by the second mouse device 60 or the like. Only when it is larger (true), the process proceeds to step S22.

Step S22: Data indicating the content of "with reason" is temporarily stored. "With reason"
This is temporary storage data indicating that there is a reason to output to output 2 (the reason is).

Step S24: It is determined whether any of "reason", "reason" and "reason" is recorded (temporarily stored). Only when one of them is temporarily stored, the process proceeds to step S26.

Step S26: "Output 2" is output.
An example of the contents of the output 2 is shown in FIG. Output terminal ID, input terminal ID, output terminal through delay value (ots), input terminal through delay value (its), reason flag, reason flag, reason flag, difference, difference designation. The data of the value K1, the magnification, and the magnification designation value K2 are provided. Here, the "reason flag" is a flag that is set if "reason" is temporarily stored (the same applies to other cases). After the output of "output 2", all the temporary storages of "reason", "reason", and "reason" are cleared.

The operation shown in the flowchart is performed for all the cells included in the netlist 2.

{Third Embodiment} FIG. 4 shows a netlist tracing means 18 according to a third embodiment of the present invention.
5 is a flowchart showing a main part of the operation of FIG.

Step S32: Data relating to the location detected in the output 1 is read, and the netlist 2 is read from the location.
In the upstream direction. While tracing,
A portion corresponding to the above output 2 is detected. Therefore, during the trace, the data of the output 2 of the result output file 6 is appropriately referred to.

Step S34: If there is a portion corresponding to the output 2, the process proceeds to step S36.

Step S36: "Output 3" is output.
An example of the contents of the output 3 is shown in FIG. That is, data of terminal ID, output terminal ID, and input terminal ID are provided. The above “terminal ID” is data from “output 1”, and “output terminal ID” and “input terminal ID” are data from “output 2”.

Step S38: Trace further upstream. Then, it is determined again whether there is a portion corresponding to the output 2 (step S34). The trace and the output of the output 3 are repeated until there is no portion corresponding to the output 2.

The operation shown in the above flowchart is performed on all data relating to the portion detected at the output 1.

According to the third embodiment, a terminal having a large through delay value and an input / output terminal relating to an upstream cell which can be presumed to be the cause can be simultaneously grasped. It can be used as basic data for circuit design review.

{Fourth Embodiment} FIG. 5 shows a fourth embodiment of the present invention.
5 is a flowchart showing a main part of the operation of FIG.

Step S42: Calculate a through delay at a certain point (terminal) in the net list 2. This step
This is a part of the operation of the through delay calculating means 14 according to the related art.

Step S44: It is determined whether or not the terminal is part of a loop circuit (including a sequential circuit). If it is a loop circuit, the process proceeds to step S46.

Step S46: The loop circuit makes one round,
Recalculate the through delay value at the same location (terminal).

Step S48: The through delay value (calculated value (1)) in step S42 is compared with the through delay value (recalculated value, that is, calculated value (2)) in step S46. If the calculated value (2) is larger than the calculated value (1), the process proceeds to step S50.

Step S50: "Output 4" is output.
An example of the contents of the output 4 is shown in FIG. That is, it has data of a loop circuit ID, a terminal ID, a calculated value (1), and a calculated value (2).

The operation shown in the above flowchart is performed for all the terminals included in the netlist 2.

<< Result Output (After Sorting) File 8 >> The Result Output (After Sorting) File 8 can be used in various data displays. FIG. 7 shows an example in which the data of the output 3 is rearranged in the power order and displayed on the display device 64.

{Display of Circuit Diagram} In displaying the circuit diagram relating to the net list 2 on the display device 64, if there is the result output file 6 and the result output (sorted) file 8, the first embodiment will be described. Points detected in the second embodiment, the fourth embodiment, and the like, which are considered to have extremely high power consumption, can be displayed on the circuit diagram. In addition, the terminal and the input / output terminal of the upstream cell, which are detected in the third embodiment, can be displayed on the circuit diagram in a superimposed manner. As a result, it is possible to make a hit for reviewing the circuit design.

[0050]

As described above, according to the present invention, a portion having a large through delay (a portion having a high amplification factor of the through delay) of a circuit can be statically analyzed and found. The power consumption can be reduced without depending on the simulation pattern.

[Brief description of the drawings]

FIG. 1 shows an outline of an overall configuration and an operation flow of a preferred embodiment according to the present invention.

FIG. 2 is a flowchart showing a main part of the operation of the through delay analysis means according to the first embodiment.

FIG. 3 is a flowchart showing a main part of the operation of a through delay analysis unit according to the second embodiment;

FIG. 4 is a flowchart showing a main part of the operation of the netlist tracing means according to the third embodiment.

FIG. 5 is a flowchart showing a main part of an operation of a loop circuit delay calculating means according to a fourth embodiment.

FIG. 6 is an example of the contents of output 1, output 2, output 3 and output 4.

FIG. 7 is a display example of a result output file on a display device.

FIG. 8 is an example of a hardware configuration of a system device for realizing the present invention.

[Explanation of symbols]

2 ... net list, 4 ... through delay library, 6 ... result output file, 12 ... input means,
14 ... through delay calculating means, 16 ... through delay analyzing means, 18 ... net list tracing means, 52
... UNIX computer, 54 ... magnetic disk, 56
... memory, 58 ... control commands, 60 ... mouse device, 64 ... display device, 70 ... central processing unit (CPU).

Claims (4)

[Claims] The present invention uses an output data from a through delay calculating means for reading a netlist and calculating and outputting a calculated value of a through delay at an input / output terminal of a cell. Means for searching for a terminal having a large calculated value of the above, and outputting data relating to the terminal and the calculated value. 2. A method according to claim 1, further comprising the steps of:
In the cell, the calculated value of the through delay of the output terminal is larger than the calculated value of the through delay of the input terminal. (2) In the cell, the calculated value of the through delay of the output terminal is larger than the calculated value of the through delay of the input terminal. And the difference is larger than the second specified value, or (3) in the cell, the calculated value of the through delay of the output terminal is larger than the calculated value of the through delay of the input terminal, and the magnification is the second value. A cell that satisfies any one of the above conditions (1), (2) or (3), which is larger than the specified value of 3, and its input terminal and output terminal are searched, and data relating to the terminal and the calculated value is retrieved. Output, through delay analysis means. 3. A netlist is read based on an arbitrary one of the terminal data of the output of claim 1, and the netlist is traced in an upstream direction. Netlist tracing means for searching for data relating to the corresponding output terminal and input terminal and outputting data relating to the terminal. 4. A through-delay calculating means for reading a netlist and calculating and outputting a calculated value of a through delay at an input / output terminal of a cell. If it is determined that it is a part of the circuit, the calculated value of the through delay at one round of the loop circuit is recalculated, and if the calculated value of the through delay at the time of the recalculation is increased,
Loop circuit delay calculating means for outputting data relating to the loop circuit, the terminal, and the calculated value.