JPH05328228A - Driver for image pickup element - Google Patents

Abstract

PURPOSE:To facilitate the signal processing in the unit of picture elements by reading an image pickup video signal with a clock signal whose frequency is 5fSC from a CCd image pickup element. CONSTITUTION:A vertical synchronizing signal and a horizontal synchronizing signal of the NTSC system from a synchronizing signal generating circuit 21 are fed to a timing generator 22 for CCD drive and a clock signal whose frequency is 4fSC (fSC is a color subcarrier frequency) is fed to a phase comparator circuit 24 via a 1/4 frequency divider 23. An output signal from a VCO 25 whose oscillating frequency is 10fSC is fed to the phase comparator circuit 24 via a 1/10 frequency divider 26 and the oscillating frequency of the VCO 25 is controlled in response to the result of phase comparison. The output signal from the VCO 25 is divided into a clock signal whose frequency is 5fSC at a 1/2 frequency divider 27 and the result is fed to a CCD drive timing generator 22. The clock signal whose frequency is 5fSC is inverted for each line by setting the 1/2 frequency divider 27 by a horizontal synchronizing signal and a CCD 11 is read in response to the clock signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup device for reading an image pickup video signal by driving an image pickup device composed of a plurality of two-dimensionally arranged pixels such as a CCD (charge coupled device) by a predetermined clock signal. A drive device.

[0002]

2. Description of the Related Art It is desired to increase the number of pixels of a solid-state image pickup device such as a CCD (charge coupled device) to improve the resolution. Here, as a specific example, in the case of a CCD image pickup device in which the number of pixels is increased to, for example, about 500,000, the horizontal transfer frequency is about 18 MHz, and the so-called D-1 format, which is the standard of the digital component VTR, or the digital composite. The so-called D- which is a VTR standard
Applications to various camera systems such as 2 format and analog are considered.

As a clock signal for driving a solid-state image pickup device such as a CCD (charge coupled device), it is preferable to use the system clock of the camera as it is in order to perform signal processing in pixel units such as defect correction. In the digital composite D-2 standard, the system clock frequency f _S of the camera is generally selected to be an integer multiple of the color subcarrier frequency f _SC .
For example, in the so-called NTSC standard, which is one of the well-known television standard systems, the color subcarrier frequency (f _SC = (455/2) f _H ) is about 3.58 MHz, and the CCD of 500,000 pixels is used. Horizontal transfer frequency (about 18
The system clock frequency f of the camera considering
_S is 5f, which is 5 times the color subcarrier frequency f _SC
SC (17.897725MHz). It is preferable to use the system clock of the frequency 5f _{SC as} a clock for driving the CCD in order to perform signal processing in pixel units such as defect correction.

[0004]

By the way, 5f _SC , which is the system clock frequency f _S in the case of the television standard system NTSC system, is equal to the horizontal frequency f _H (1
137 + 1/2) times, that is, f _S = 5f _SC = (1137 + 1/2) f _H.

Therefore, when the CCD image pickup device is driven by the system clock having the frequency of 5 f _SC , the position of the pixel of the video signal read from the image pickup device is 1/2 pixel for each line (horizontal scanning line). Will gradually shift,
This is not preferable because the image displayed on a CRT (cathode ray tube) monitor is disturbed.

The present invention has been made in view of such a situation, and is (N + 1/2) of the frequency of the horizontal synchronizing signal.
Double, where N is an integer, and C is the system clock frequency
An object of the present invention is to provide a driving device for an image pickup device that can drive an image pickup device such as a CD and can easily perform signal processing in pixel units such as defect correction.

[0007]

According to the image pickup device driving apparatus of the present invention, an image pickup device composed of a plurality of two-dimensionally arranged pixels is driven by an image pickup device read clock signal of a predetermined frequency to generate an image pickup video signal. in the driving device of the image sensor for reading one horizontal frequency f _H for integer value N and the value times the sum of the 1/2 frequency _{f S (f S = (N} + 1 /
2) The above problem is solved by using the system clock of f _H ) and inverting this system clock for each horizontal scanning to obtain the image pickup element reading clock signal.

In the so-called NTSC system, which is one of the well-known television standard systems, the horizontal transfer frequency of the CCD image pickup device of about 500,000 pixels is about 18M.
Hz, and the system clock frequency f _S becomes 18 MHz
If the neighboring 5f _SC (f _SC is the NTSC color subcarrier frequency), then the horizontal frequency f _H is (1137 + 1/2)
Times, that is, f _S = (1137 + 1/2) f _H ,
This corresponds to the case of N = 1137.

[0009]

The image sensor can be driven by the system clock having a frequency of (N + 1/2) times the horizontal frequency, and pixel-based signal processing such as defect correction can be easily performed.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of an embodiment of an image pickup device driving apparatus according to the present invention. In FIG. 1, an image pickup device 11 such as a CCD (charge coupled device) reads out an image pickup video signal (analog signal) at a system clock having a frequency 5f _{SC which is} five times the color subcarrier frequency f _SC of the NTSC system.
This analog video signal is amplified by the preamplifier 12, converted into a digital signal by the A / D converter 13, and the defect correction circuit 14 corrects the defect for each pixel. (Sampling rate converter) 16 sent to the above frequency 5f _SC
To 4f _SC the sampling clock frequency is converted. The rate-converted signal is sent to the encoder circuit 17
Via the output terminal 18 as a so-called D-2 format digital video signal. In addition,
The rate conversion circuit 16 can be arranged at any position in the range from the front stage of the signal processing circuit 15 to the rear stage of the encoder circuit 17.

Synchronous signal generation circuit (sync generator)
From 21, and vertical and horizontal synchronizing signals are defined by the standard of the NTSC system, D-2 format sampling clock frequency frequency 4f _SC of (f _SC is a subcarrier frequency) are output signals of a vertical The sync signal and the horizontal sync signal are the timing generator 2 for driving the CCD.
The sampling clock signal having a frequency of 4f _SC is sent to the 1/4 frequency divider 23. Also, various synchronization signals are sent to the encoder 17 and the like. 1/4 frequency divider 2
The frequency-divided output signal (frequency f _SC ) from 3 is sent to the phase comparison circuit 24, and the output signal from this phase comparison circuit 24 is sent to the control terminal of the VCO (voltage controlled oscillator) 25 as an oscillation frequency control signal. ing. This VCO25 is the subcarrier frequency f and oscillates at 10 times the frequency 10f _SC of _SC, becomes a signal of the oscillation output signal is divided by the 1/10 frequency divider 26 frequency f _SC, the phase comparator circuit 24
Have been sent to. The VCO 25, the 1/10 frequency divider 26, and the phase comparison circuit 24 constitute a so-called PLL (phase locked loop) circuit, and the phase of the signal of the frequency f _SC from the 1/10 frequency divider 26 is The oscillation of the VCO 25 is controlled so as to match the phase of the signal of the same frequency f _SC from the 1/4 frequency divider 23.

Further, the oscillation output signal of the VCO 25 having a frequency of 10f _SC is divided by the 1/2 frequency divider 27 to obtain a frequency of 5f.
It becomes the _SC signal and the timing generator 22 for driving the CCD
Have been sent to. The 1/2 frequency divider 27 is set by the horizontal synchronizing signal from the synchronizing signal generating circuit 21, whereby the clock signal of frequency 5f _SC is supplied for each horizontal scanning (for each line). ) Will be reversed. The signal of frequency 5f _SC from the 1/2 frequency divider 27 is sent to the CCD 11 as a CCD reading clock via the timing generator 22.

Here, FIG. 2 shows a conventional frequency of 5f.
An example in which the CCD image pickup device is driven by the _SC clock signal is shown. The signals A ₁ and A ₂ are horizontal synchronization signals of the NTSC system, and the signals B ₁ and B ₂ are the above-mentioned frequency 5f _SC (= f
_S , the cycle T _S ) of the read clock signal, the signal C ₁ ,
C ₂ shows a specific example of the video signal read from the CCD image pickup device. The signals A _{1 to} C ₁ for scanning one line (scanning line) and the signals A _{2 to} C ₂ for scanning the next line are shown.

In FIG. 2, first, a system clock signal B ₁ having a period T _S with respect to an NTSC horizontal synchronizing signal A _{1 of} an arbitrary line, and a system clock having a period T _S with respect to a horizontal synchronizing signal A ₂ of the next line. the signals B _2, reverse phase relationship to each other, i.e. located in offset relationship by a half period T _S / 2, the video signal C ₁ that has been read from the CCD, C ₂ also by a half period T _S / 2 It will appear displaced. When this is displayed on the CRT screen, a good image cannot be obtained.

Therefore, the CCD read clock signal of the frequency 5f _SC (= f _S , period T _S ) is inverted for each line, and specifically, it is 1/2 time for generating the signal of the frequency 5f _SC. By setting the frequency divider 27 with a horizontal synchronizing signal of frequency f _H , the phases of the CCD read clocks for each line are aligned. A specific example of the operation at this time will be described with reference to FIG.

In FIG. 3, the synchronizing signal generating circuit 21
The horizontal synchronizing signal A from is sent to the 1/2 frequency divider 27,
The 1/2 frequency divider 27 is set. At this time, 1/2
In the output signal B of the frequency 5f _SC from the frequency divider 27, the inversion (transition) operation is blocked once every half cycle in the cycle next to the cycle in which the fall of the horizontal synchronizing signal A occurs. .. This blocked inversion is a falling edge as shown by the broken line in the example of FIG. 3B, and this inversion (falling edge) occurs after T _S / 2. Interval) is (3/2) T _S ,
The clock signal has the same phase as the previous line. This CCD
In response to the read clock signal B, the CCD image pickup device 11
From, an image pickup video signal as shown in C of FIG. 3 is read. Also, the horizontal sync signal of the next line and CC
The relationship with the D read clock signal B is the same as in FIG.

According to such an embodiment of the present invention, CC
The D image sensor 11 can be driven by the system clock of the camera with a frequency of 5 f _SC , and the pixel-based processing such as defect correction is performed as it is (without performing rate conversion or the like).
It can be carried out.

The present invention is not limited to the above-described embodiment, and the relationship between the system clock frequency and the horizontal synchronizing signal frequency is not limited to the numerical values of the above-mentioned embodiment, and various other values. Can be

[0019]

As is apparent from the above description, according to the image pickup device driving apparatus of the present invention, the image pickup device such as the CCD is set to an integer value with respect to a predetermined frequency, that is, one horizontal frequency f _H. Value times the sum of N and 1/2 (f _S = (N + 1 /
2) When the image pickup video signal is read by driving with the system clock having the frequency set to f _H ), the system clock is inverted line by line to form the clock signal for driving the image pickup element. The image sensor can be driven in synchronization with the system clock, and signal processing for each pixel such as defect correction can be easily performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of an image pickup device driving apparatus according to the present invention.

FIG. 2 is a timing chart for explaining a conventional image sensor driving operation.

FIG. 3 is a diagram showing a timing chart for explaining the operation of the embodiment.

[Explanation of symbols]

11 ... CCD image pickup device 13 ... A / D converter 14 ... Defect correction circuit 15 ... Signal processing circuit 16 ... Rate conversion circuit 16 ... ... Encoder 18 ... D-2 format digital video signal output terminal 21 ... Synchronous signal generation circuit 22 ... CCD drive timing signal generator 23 ... 1 / Frequency divider 24: Phase comparison circuit 25: VCO (voltage controlled oscillator) 26: 1/10 frequency divider 27: 1/2 frequency divider

Claims (1)

[Claims] 1. A driving device of an image sensor for reading an image video signal by driving the imaging device read clock signal of a predetermined frequency an image sensor comprising a plurality of pixels arrayed two-dimensionally, integer for a horizontal frequency f _H The frequency f _S (f _S = (N + 1/2)) set to a value times the sum of the numerical values N and 1/2
f _H ) system clock is used, and this system clock is inverted every horizontal scanning to obtain the image pickup device reading clock signal.