JPH01132285A - Picture memory control device - Google Patents

Abstract

PURPOSE:To reduce horizontal jitter or large image swinging in a horizontal direction by setting write start timing by a horizontal sync signal from a sync separation circuit, and at the same time, setting read start timing by the frequency divided output signal of a PLL circuit. CONSTITUTION:The horizontal sync signal Hs from the sync separation circuit 25 is given to a write signal input terminal 19a, and the write start timing of the line.memory of a 1H delay circuit 11' is set by this signal. The frequency divided output signal from a frequency divider 28 is given to a read signal input terminal 19b, and the read start timing of the line.memory of the 1H delay circuit 11' is set by this signal. An input video signal is written in the line.memory of one side at the timing of the horizontal sync signal, and from the line.memory of other side, it is read out at the timing of the frequency divided output signal of a VCO. Thus, the horizontal shift of a vertical line comes legs in the picture of a TV receiver.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a control device for an image memory used in a digital television receiver or the like.

(b) Conventional technology In recent years, television receivers (hereinafter referred to as rTV imitators) have been using standard No. 48 for on-air broadcasting, where the ratio of horizontal synchronization No. 18 and the frequency of the burst signal is constant. signal)
and non-standard signals (signals where the ratio of the frequency of the horizontal synchronization signal and the burst signal is not constant) such as the playback signal of a video tape recorder (hereinafter abbreviated as 'VTRJ), i.e. In VTRs, the horizontal synchronization frequency f8 varies from the normal frequency (15.7 kHz) due to factors such as expansion and contraction of the playback tape (causing sick).
Therefore, the reproduced signal is called a non-i quasi signal.

Figure 8 is a block diagram of a general TV receiver, in which a composite video signal applied to a terminal (1) is demodulated by a video chroma circuit (2) to generate R, G, and B primary color signals. , these R, G, and B primary color IDs are sent to the cathode ray tube (6) via the R, G, and B signal drive circuits (3), (4, and
) can be supplied. On the other hand, the composite video signal is input to a synchronization separation circuit (7), where a horizontal synchronization signal (Hs) and a vertical synchronization signal (Vs) are extracted. The horizontal synchronizing signal (Ha) is supplied to the horizontal deflection circuit (1o) via the horizontal AFC circuit (9).

In the above TV receiver, when inputting standard signals, A
Reduce the time constant of the FC circuit (9) to speed up the AFC pull-in response, and when a non-standard signal is input, the AFC circuit (9)
The time constant of is increased to slow down the retraction response. The reason for this is that the period of the horizontal synchronization signal for non-standard signals is not constant and there is jitter. In order to improve this, the output of the horizontal deflection circuit (lO) is slowed down by the horizontal synchronization signal and the output of the horizontal deflection circuit (10) is changed. The output is made to have a constant horizontal period without being affected by the fine jitter of the horizontal synchronization signal.

A skew (S K EW) distortion signal is usually used to study the time constant of the AFCcfl path as described above. The 5KEW distortion signal referred to here is obtained from a test pattern signal generator, and the specific horizontal scanning period of each field is 63,5+ atill as shown in Figure 9.
(■), 63.5-aus (■). When such a 5KEW distorted signal is reproduced on a TV receiver, the cathode ray tube screen will appear as shown in FIG. This 10th
In the figure, the places where the vertical lines (thick lines) are interrupted are the corresponding ■■ in Figure 9.
■Compatible with. Since the time required for the point ■■ to return to its original state corresponds to the time constant of the AFC circuit, the time constant of the AFC circuit can be visually evaluated using the 5KEW distortion signal as described above.

Horizontal jitter and large image shake in the horizontal direction in non-standard signals such as VTR playback signals can be considered to be the same phenomenon caused by the 5KEW distortion signal, and therefore, the performance of the TV receiver depends on the 5KEW distortion signal. It is said that it is good if the horizontal shift of the screen that occurs is small, and the time it takes for vertical lines to return to their original state is appropriately short.

Incidentally, as digital technology has progressed in recent years, video signal processing circuits using digital memory have come to be installed in TV receivers as well.

Figure 11 shows the line memory (
12) shows an IH (horizontal period) delay circuit (11) using (13). In the delay circuit (11), (14> is an input terminal into which a digital video signal is input, (15) is an output terminal, (16) is a clock input terminal, (17) is a write changeover switch, and (18) is a readout terminal. The changeover switch (19) is a changeover signal input terminal into which a changeover signal such as a horizontal synchronization signal can be input, and also, as is well known, a line memory (12).
) and (13) are digital memories each capable of storing digital video signals for IH.

FIG. 12 is a timing chart for explaining the operation of the IH delay circuit (11), in which (a) shows the mode of the line memory (12), and (b) shows the mode of the line memory (13). ), and each time the switching signal [(C) in the figure] is input to the input terminal (19), each of the memories (12) and (13) becomes in an opposite mode.

That is, during any IH period, the switch (17)
When (18) is in the position shown in Figure 11, line memory (1
2), digital video signals are sequentially written through the switch (17), and at the same time, the line memory (13)
From there, the IH signal immediately before the IH signal written to the memory (12) is read out via the switch (18). Then, in the next IH period, switch (17) (1
8) is switched and the next I is stored in the line memory (13).
H-minute digital video signals are written, and IH-minute signals are read out from the licensee memory (12). By repeating such operations, it functions as an IH delay circuit. Such an IH delay circuit (11) is used, for example, in a digital TV that doubles the number of horizontal scanning lines to improve the vertical resolution.

FIG. 13 shows a block diagram of the main parts of such a digital TV.

In FIG. 13, an analog composite video signal applied to an input terminal (20) is demodulated by a video chroma circuit (21), and then converted to a digital video signal by an A/D converter (22). IH delay circuit (11
) is written to line memory. The digital video signal read from the line memory of the IH delay circuit (11) is converted into an analog video signal by the D/A converter (23) and then output from the output terminal (24). On the other hand, the analog composite video signal is processed by a synchronization separation circuit (25)
The horizontal synchronization signal (Hs
) can be supplied as one input to the phase comparator (26). (27) is applied to the A/D converter (22), IH delay circuit (11) and D/A converter (23)
VCO [voltage controlled oscillator] that supplies the clock signal of
This vCON' frequency-divided output signal is supplied as the other input of the phase comparator (26). This phase comparator (26) compares the phases of the horizontal synchronizing signal (Hs) and the frequency-divided output signal of the frequency divider (28), and adjusts the oscillation frequency of vCo (27) so that the comparison result becomes zero. Control. Therefore, these phase comparators (2
6), VCO (27) and frequency divider (28)
Configure the elocked 1loop) circuit. Horizontal synchronization signal (Hs) output from the synchronization separation circuit (25)
is connected to the horizontal deflection circuit (30) via the horizontal AFC circuit (29).
). The signal output from the horizontal deflection circuit (30) is output from the terminal (31).

Next, the operation when a non-standard signal is input to the circuit shown in FIG. 13 will be explained by taking as an example the case where the above-mentioned 5 KEW distortion signal is input, with reference to the time chart of FIG. 14.

In FIG. 14, (a) is the input video signal;
b) C horizontal synchronous signal 'i+, same 11 (c) C V CO
(27) (7) Frequency-divided output signal, (d) of the same figure shows the VCO (2
7) oscillation frequency, the same HQ(e) is the IH delay circuit (1
The video signal completely read out from the memory in 1), (f') in the same figure shows the output signal (flyback pulse) of the horizontal deflection circuit (30).

Now, when a 5KEW distortion signal is generated at the 0 point in Fig. 14, the phase comparator (26) compares the phases of the signals shown in Fig. 14 (b) and (c), and changes the oscillation frequency of the V CO (27) to Fig. 14 (2). d). At this time, the switching of the start point of writing and reading of the line memory of the IH delay circuit (11) in Fig. 13 [switching of the switches (17) and (18) in Fig. 11] is performed horizontally by the horizontal synchronizing signal (Hs). There is no problem because it is carried out within the retrace line.

However, as shown in FIG. 13, the horizontal deflection circuit (30) transmits the horizontal synchronization signal (Hs) to the horizontal AFC circuit (
29), so the AF
Due to the time constant of the C circuit (29), Fig. 14 (f'
The timing of the flyback pulse shown in ) is approximately the same as that of the frequency-divided output signal shown in FIG.

As a result, as shown in FIGS. 14(e) and 14(f), the video signal output from the IH delay circuit (11) and the flyback pulse are largely out of phase, so the screen of the TV receiver is
It will look like the figure.

In order to eliminate such drawbacks, for example, Japanese Patent Laid-Open No. 55-5
As described in Publication No. 3981 (HO4N 5/783), measures have been taken to reduce jitter on the VTR side, but these have not been sufficient.

(c) Problems to be Solved by the Invention The present invention has been devised in view of the above points, and involves devising control of the image memory into which non-standard signals such as playback signals from VTRs and the like are input. This is intended to reduce horizontal distortion and large horizontal image shaking. Another object of the present invention is to change the reproduction screen when a weak electric field is applied.

(d) Means for Solving the Problems The image memory control device of the present invention includes a memory that stores an input video signal for at least one horizontal period, and a synchronization separation circuit that extracts a horizontal synchronization signal from the input video signal. , a PLL circuit whose reference signal is a horizontal synchronization signal provided from the synchronization separation circuit, and a horizontal AFC provided with a frequency-divided output signal synchronized with the horizontal synchronization signal obtained by the PLL circuit.
The memory has a write start timing set by a horizontal synchronization signal from the sync separation circuit and a read start timing set by a frequency-divided output signal of the PLL circuit, and the sync separation circuit is designed to output a horizontal synchronization signal by free oscillation when the electric field is weak.

(e) Effect With the above configuration, a signal (divided output signal) synchronized with the memory read timing is input to the AFC circuit, so even if the IH period changes, the video signal read from the memory and The phase difference with the output signal of the horizontal deflection circuit is made as small as possible. Moreover, the playback screen also becomes better when the electric field is weak.

(f) Examples An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of the main parts of a digital TV receiver embodying the present invention, and the same parts as in FIG. 13 are given the same reference numerals and their explanation will be omitted.

That is, in the present invention, the IH delay circuit (11') as shown in FIG. 2, in which the same parts as in FIG.
), that is, a write signal input terminal (19a) for switching the switch (17), and a bladder release signal input terminal (19b) for switching the switch (18).
1') is used, and the write signal input terminal (19a
) has a horizontal synchronization signal (Hs
) is given, and thereby the writing start timing of the line memory of the IH delay circuit (11') can be set.

Further, the read signal input terminal (19b) is connected to a frequency divider (
28), which provides a frequency-divided output signal from I
The read start timing of the line memory of the H delay circuit (11') is set.

It goes without saying that the switches (17) and (18) can be switched alternately as in the past.
Also, unlike the conventional case, the horizontal AFC circuit (29) is supplied with the frequency-divided output signal of the frequency divider (28). It shows an operation timing chart when a signal is input, and in FIG. 3, (a) is an input video signal,
The same figure (b) shows the horizontal synchronizing signal, and the same figure S (c) shows the V CO (
28), the divided output signal of the same figure (d) is the IH delay circuit (1
FIG. 1(e) shows the output signal (flyback pulse) of the horizontal deflection circuit (30).

As can be seen from the timing chart in Fig. 3 above, the input video signal is written to one line memory at the timing of the horizontal synchronization signal [Fig.
It is read out from the memory at the timing of the frequency-divided output signal of vCO [FIG. 4(C)]. And horizontal deflection circuit (30)
is driven by the frequency-divided output signal [FIG. 3(C)] of V CO (28) via the horizontal AFC circuit (29), so the timing of the horizontal deflection output is as shown in FIG. 3(e), As a result, even if the IH period changes due to the 5KEW distortion signal, the difference between the video No. 18 read out from the memory [Fig. 3(d)] and the output signal of the horizontal deflection circuit (30) [Fig. 3(e)] The phase difference is made as small as possible.As a result, the horizontal shift of the vertical lines on the screen of the TV receiver is reduced as shown in FIG.

By the way, in a normal synchronization separation circuit, a horizontal synchronization signal as shown in FIG. 5(b) is obtained from a composite video signal as shown in FIG. 5(a) by amplitude separation. However, when the antenna input of a TV receiver becomes a weak electric field, a lot of noise is included in the video signal as shown in Figure 5 (C), and the horizontal synchronization signal obtained by synchronously separating this noise is also shown in Figure 5 (d). It will contain a lot of noise like this.

When the antenna input to the TV receiver becomes weak one-field in this way, the period of the horizontal synchronization signal becomes random, and if no antenna is connected to the TV receiver (no antenna), no horizontal synchronization signal can be obtained. If such a situation occurs in the circuit shown in FIG. 1, the following problems will occur. In other words, when the electric field is weak, the write start pulse that can be input to the IH delay circuit (11') becomes random, so the video signal input to the A/D converter (22) is as shown in Figure 5 (C). Even if there is, it is written completely randomly to the line memory,
The data read out will not become the original video signal, and when there is no antenna, no write start pulse will be obtained, so the data in the line memory will retain the data written immediately before. Since this is read out repeatedly, all the scanning lines forming the screen are the same.

In a normal analog TV receiver, snow noise occurs on the screen when the electric field is weak or there is no antenna, but the TV receiver shown in Figure 1 does not produce such snow noise, and the user does not receive the TV image. This gives the impression that the machine is out of order.

Therefore, in the present invention, the synchronous separation circuit (25) shown in FIG.
A circuit as shown in Fig. 6 is used.

That is, in Fig. 6, (40) is a synchronous deflection integrated circuit (IC) manufactured by Sanyo Electric Co., Ltd. [Product number: LA7801]
A video signal as shown in Fig. 7(a) is input to the ■ pin, and a horizontal synchronizing signal of positive polarity [Fig. 7(b) is input from the ■ pin.
)] is obtained. This horizontal synchronization signal is sent from the ■ pin to the IC (
40), the AFC circuit compares the phase with the feedback input voltage input from the ■ pin, and as a result of this comparison, a DC control voltage is output from the ■ pin. This DC control voltage is applied via a resistor (R2) and a variable resistor (VR
t), a resistor (R+), and a capacitor (C+) are external components that control the horizontal synchronous frequency oscillation circuit, and a horizontal drive pulse [Fig. 7 (C)] of the horizontal synchronous frequency is output from the ■ pin. . This horizontal drive pulse is then used as the output of the synchronous separation circuit (25) in FIG. At this time, if the time constant of the AFC circuit is made small by alting the value of (Rs) (C*) (C), a horizontal drive pulse that is substantially synchronized with the input video signal can be obtained.

If the synchronous separation circuit shown in FIG. 6 is used as the synchronous separation circuit (25) shown in FIG. 1, the screen that can be reproduced in a weak electric field and in the absence of an antenna will be a snow noise screen.

(G) Effects of the Invention As described above, according to the present invention, it is possible to reduce jitter and large image shake in the horizontal direction that occur when a non-standard signal such as a reproduced signal from a VTR or the like is completely input. Furthermore, the screen that is reproduced during a weak electric field will no longer give a false impression to the user.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the main parts of a television receiver embodying the present invention, FIG. 2 is a diagram showing details of the main parts, FIG. 3 is a diagram for explaining the operation of FIG. 1, and FIG. The figures are diagrams for explaining the present invention in detail, Figure 5 is a signal waveform diagram, Figure 6 is a circuit diagram of the main part of the invention, Figure 7 is its operation waveform diagram, and Figure 8 is a general TV. Block diagram of main parts of John receiver, No. 9
Figures 1 and 10 are diagrams for explaining skew distortion signals,
Fig. 11 is a diagram showing the IH delay circuit, Fig. 12 is an explanatory diagram of its operation, Fig. 13 is a block diagram of main parts of a television receiver using the IH delay circuit, Fig. 14 is an explanatory diagram of its operation, FIG. 15 is a diagram for explaining the conventional drawbacks. (11')...IH delay circuit (memory), (25)...
... Synchronization separation circuit, (26) ... Phase comparator, (27
)・V CO, (28)... Frequency divider, (29)...
Horizontal AFC circuit.

Claims (1)

[Claims] (1) A memory that stores an input video signal for at least one horizontal period, a synchronization separation circuit that extracts a horizontal synchronization signal from the input video signal, and a PLL that uses the horizontal synchronization signal provided from the synchronization separation circuit as a reference signal. circuit, and a horizontal AFC circuit to which a frequency-divided output signal synchronized with the horizontal synchronization signal obtained by the PLL circuit is provided, and the memory has a write start timing set by the horizontal synchronization signal from the synchronization separation circuit. Said PLL
An image memory control device, wherein a read start timing is set by a frequency-divided output signal of a circuit, and the synchronization separation circuit outputs a horizontal synchronization signal by free oscillation in a weak electric field.