JPH05251667A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] A semiconductor device including a thin film transistor is provided.
While maintaining good performance of the thin film transistor,
Do not contact the semiconductor layer and wiring layer that will be the
The purpose is to make good conduction without doing. [Structure] On the first insulating film 3,8,9 above the semiconductor substrate 1
The gate electrode Gp formed at least on the lower side.₁Thin with
Membrane transistor t_{twenty one}, t_{twenty two}In a semiconductor device having
The thin film transistor t_{twenty one}, t_{twenty two}Half of the channel area
The first conductor film 11 is formed on the first insulation films 3, 8, 9
Through the contact hole 10 of the semiconductor substrate 1
The thin-film transistor extends over the electrotype layer 7 and
Tat_{twenty one}, t _{twenty two}Formed on the second insulating film 14 that covers
A second part of which overlaps with the first contact hole 1
The wiring layer 16 passing through the contact hole 15 of
It is configured to include being formed on the insulating film 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a thin film transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art SRAM (s) composed of MOS transistors
The tatic random access memory cell has a circuit configuration as shown in FIG. 7A, and has two CMOs composed of driving MOSFETs t ₁₁ and t ₁₂ and load MOSFETs t ₂₁ and t _22.
SFETs q ₁ and q ₂ and two transfer MOSFETs t ₃₁ ,
and t ₃₂ .

Two CMOSFETs q ₁ and q ₂
Of the CMOSFETs q ₂ and q ₁ of the other side.
Source / drain (S / D) of different transfer MOSFETs t ₃₁ and t _32.
Are connected to different bit lines BL ₁ and BL ₂ via. The gates of the transfer MOSFETs t ₃₁ and t ₃₂ are connected to the same word line WL.

Further, the load MOSFET t_{twenty one}, T_{twenty two}of
The voltage Vcc is applied to the source, and the driving MOSFET t
₁₁, T₁₂The voltage Vss is applied to the source of the. Toko
If the SRAM is formed on the semiconductor substrate, the driving
MOSFETt ₁₁, T₁₂And transfer MOSFET
t₃₁, T₃₂While forming in bulk, load MOSFE
Tt_{twenty one}, T_{twenty two}The double gate structure thin film transistor (TF
It is recommended to use T) to form and stack on the bulk.
Is being proposed.

Therefore, first, the planar structures of the driving MOSFET and the transfer MOSFET will be described with reference to FIG. In FIG. 8A, a selective oxide film 103 for partitioning a rectangular frame-shaped active region 102 is formed on the upper surface of a semiconductor substrate 101 made of p-type silicon, and a film thickness of 20 nm or less is formed on the surface of the active region 102. An insulating film 104 made of SiO ₂ is formed. However, only a part of the active region 10 is illustrated.

Further, two n-type MOSFETs are formed in two parallel side regions of the rectangular frame-shaped active region 102, and the gate electrodes Gn of the n-type MOSFETs are formed in different active regions across the side regions. Extended into the corner area of 102,
Moreover, the n-type impurity diffusion layer 10 formed in the corner region
It is connected to 5 through contact hole CH ₁ . And 2 connected to each other through the gate electrode Gn
Two n-type MOSFETs for driving SRAM
Used as Tt ₁₁ and t ₁₂ .

Further, the word line WL extends across the remaining two side regions of the above-mentioned rectangular frame-shaped active region 102, and in that region, the word line WL is used as a gate electrode for transfer. MOSFETs t ₃₁ and t ₃₂ are formed, and these transfer MOSFETs t ₃₁ and t ₃₂ are connected to the driving MOSFETs t ₁₁ and t ₁₂ via the n-type impurity diffusion layer 105 of the active region 102 serving as the source / drain thereof. There is.

The n-type impurity diffusion layer 105 is formed in the active layer 102 in a self-aligned manner by using the gate electrode Gn and the word line WL as a mask, and becomes the source / drain layer of the above MOSFET.

Transfer MOSFET formed by this
t₃₁, T₃₂And driving MOSFETt ₁₁, T₁₂Is shown in FIG.
The connection state is as shown in the lower circuit shown in (b). next,
The structure of the load MOSFET is shown in Figs. 8 (b), 9 (c) and (d).
It will be explained based on.

The load MOSFETs t ₂₁ and t ₂₂ are shown in FIG.
It is formed of a double-gate thin film transistor as shown in (d), and is composed of a thin silicon layer 108 having a film thickness of 20 nm to be its channel region and source / drain regions, and upper and lower gate electrodes Gp ₁ and Gp ₂ sandwiching it. Has been done.

The gate electrode Gp ₁ below the load MOSFETs t ₂₁ and t ₂₂ has a transfer MOSF as shown in FIG. 8 (b).
ETt ₃₁ , t ₃₂ and driving MOSFETs t ₁₁ , t ₁₂ are covered
The active region 102 is formed on the SiO ₂ insulating film 105.
Has a planar shape that covers the n-type impurity diffusion layer 105 at the corner and the gate electrode Gn adjacent thereto.

As shown in FIG. 9C, the silicon film 108 formed on the insulating film 107 made of SiO ₂ has a gate electrode Gn of the driving MOSFETs t ₁₁ and t ₁₂ and a word line WL. A planar shape along the above and above the word line WL is the Vcc power supply line L. Further, an upper gate electrode Gp ₂ facing the lower gate electrode Gp ₁ and having the same size as the lower gate electrode Gp ₁ is formed thereon via an insulating film 109 made of SiO ₂ .

In the region of the silicon layer 108 which is not sandwiched between the upper and lower gate electrodes Gp ₁ and Gp ₂ , a p-type impurity diffusion layer 109 serving as a source / drain is formed as shown in FIG. 9C. ing.

Further, the insulating films 104, 106, 107 and 110 located above the corners of the active region 102, the load MOSFETs.
The silicon layer 108 and the lower gate electrode Gp ₁ of t _21, t ₂₂ be formed a contact hole CH _2, the upper and lower gate electrodes Gp ₁ by hanging a part of the upper gate electrode Gp ₁ therein , Gp ₂ , the silicon layer 108, and the n-type impurity diffusion layer 105 are electrically connected to each other, whereby the upper circuit shown in FIG. 7B and the wiring shown by the broken line are formed.

By the way, of the SRAM cells described above,
A cross section taken along the silicon layer 108 of the load MOSFETs t ₂₁ and t _{22 and} the Vcc power supply line L connected to the silicon layer 108 is shown in FIG.
It becomes as shown in (a).

In FIG. 10A, reference numeral 111 is an interlayer insulating film made of SiO ₂ or the like laminated on the load MOSFETs t ₂₁ and t ₂₂ , and is a silicon layer 108 to be the Vcc power supply line L.
A contact hole 112 is formed above the Vcc power supply wiring 113, and the Vcc power supply wiring 113 arranged on the interlayer insulating film 111 is connected to the Vcc power supply wiring L through the contact hole 112. In FIG. 10, the same symbols as those in FIGS. 8 and 9 indicate the same elements.

However, according to such a structure, the contact hole 112 is opened by the dry etching method using CHF ₃ as a reaction gas, so that the contact hole 112 penetrates through the extremely thin silicon layer 108 under the interlayer insulating film 111. Since it is etched further downward, if there is a wiring therebelow, a short circuit will occur. On the other hand, it is conceivable to increase the thickness of the silicon layer 108, but the thicker the semiconductor layer serving as the channel region of the load MOSFETs (thin film transistors) t ₂₁ and t ₂₂ , the worse the performance of the transistor. It is not appropriate to adopt the method.

Therefore, an apparatus having another structure as shown in FIG. 10 (b) has been proposed. In FIG. 10 (b), reference numeral 11
Reference numeral 4 is a contact hole formed by opening the insulating film 107 covering the gate electrodes Gp ₁ below the load MOSFETs t ₂₁ and t ₂₂ and the insulating films 106 and 104 thereunder, and is a p-type impurity diffusion inside the N well 115. The silicon layer 108 is formed on the layer 116 and is connected to the p-type impurity diffusion layer 116 through the contact hole 114. Further, another contact hole 117 is formed in the insulating films 104, 106, 107, 110 and the interlayer insulating film 111 on the p-type impurity diffusion layer 116, and the Vcc power supply wiring layer 113 is formed in the contact hole 11.
It is configured to be connected to the p-type impurity diffusion layer 116 through 7 and to be electrically connected to the silicon layer 108.

In this case, the p-type impurity diffusion layer 116 has a p-type load MOSFET (p-type thin film transistor) t ₂₁ ,
Since it is connected to the p-type source layer at t ₂₂ , current cannot flow unless it is p-type. Therefore, the Vcc power supply wiring 113
Are formed in the N well 115 outside the area of the SRAM cell.

According to this structure, after the contact hole 114 for connecting the silicon layer 108 to the p-type impurity diffusion layer 115 is formed, the photoresist (not shown) is removed by O ₂ plasma. Since the cleaning treatment with sulfuric acid is performed, the surface of the semiconductor substrate 101 exposed from the contact hole 114 is oxidized to form a natural oxide film, which needs to be removed with hydrofluoric acid.

However, when removing the natural oxide film with hydrofluoric acid, as shown in FIG. 10 (c), the lower gate electrode Gp _{1 is formed.}
There is a problem that the surface of the SiO ₂ insulating film 107 covering the same is damaged at the same time and becomes thin in a scattered spot, and the breakdown voltage between the lower gate electrode Gp ₁ and the silicon layer 108 is significantly lowered.

Therefore, as shown in FIG. 11A, a silicon layer 118 containing impurities is formed on the insulating film 107 covering the lower gate electrode Gp ₁ , and the p-type silicon layer 118 is formed before patterning the silicon layer 118. A contact hole 120 is formed on the diffusion layer 116, and then the p exposed from the contact hole 120 is formed.
A method of removing the natural oxide film on the surface of the type impurity diffusion layer 116 with hydrofluoric acid is adopted.

According to this, since the insulating film 107 covering the lower gate electrode Gp ₁ is protected by the silicon layer 118, it is not damaged by hydrofluoric acid. Also after this,
In order to connect the load transistors t ₂₁ and t ₂₂ to the p-type impurity diffusion layer 116, the second silicon layer 12 containing impurities is used.
8 in the contact hole 120 and the second silicon layer 128
The first layer silicon layer 118 and the p-type impurity diffusion layer 116 are electrically connected to each other through the second layer silicon 128. Then, the first and second silicon layers 118 and 128 are successively patterned by using one mask, and the pattern shown in FIG.
The same shape as the silicon layer 108 shown in FIG. 11 (FIG. 11B),
Thereby, the channel regions and the source / drain regions of the load transistors t ₂₁ and t ₂₂ are formed.

After stacking the interlayer insulating film 111,
Another contact hole 121 is opened on the p-type impurity diffusion layer 116, and Vcc power supply wiring 113 passing therethrough is formed.
And the silicon layer 11 is formed through the p-type impurity diffusion layer 116.
8,128 and the Vcc power supply wiring 113 are electrically connected (FIG. 11 (c)).

[0025]

However, when the performance of the thin film transistor thus formed was measured,
According to the thin film transistor having a structure in which the silicon layer forming the channel region is formed twice, there arises a problem that the source / drain current in the on state is reduced by about two digits and the leak current in the off state is increased several times.

The present invention has been made in view of the above problems, and maintains the performance of the thin film transistor without contacting the semiconductor layer and the wiring layer which will be the channel region thereof with other wiring layers. It is an object of the present invention to provide a semiconductor device that conducts well and a manufacturing method thereof.

[0027]

[Means for Solving the Problems]
, The first insulating film 3, above the semiconductor substrate 1,
Gate electrode Gp ₁ formed on at least the lower side
In a semiconductor device having a thin film transistor t _21, t ₂₂ having a semiconductor film 11 serving as a channel region of the thin film transistor t _21, t ₂₂ is first formed on the first insulating film 3, 8, 9 The second insulating film 14 extends through the contact hole 10 onto the conductive type layer 7 in the semiconductor substrate 1 and covers the thin film transistors t ₂₁ and t ₂₂ , and at least a part of the first contact is formed. The wiring layer 16 passing through the second contact hole 15 overlapping the hole 10
This is achieved by a semiconductor device characterized in that it is formed on the second insulating film 14.

Alternatively, the thin film transistors t ₂₁ and t ₂₂
Is a load transistor of an SRAM cell, which is achieved by a semiconductor device. Alternatively, the thin film transistors t ₂₁ , t ₂₂ are formed on the first insulating film 8 on the semiconductor substrate 1.
The step of forming the gate electrode Gp ₁ of
The step of forming the second insulating film 9 covering p ₁ and the step of selectively etching the insulating films 3, 8 and 9 on the conductive type layer 7 formed in the upper layer portion of the semiconductor substrate 1 The step of forming the first contact hole 10 and the channel regions of the thin film transistors t ₂₁ and t ₂₂ without removing the native oxide film formed on the surface of the semiconductor substrate 1 exposed from the first contact hole 10. The semiconductor film 11 to be the second
Forming the third insulating film 14 on the insulating film 9 and along the inner circumference and the bottom surface of the first contact hole 10, and after forming the third insulating film 14 covering the semiconductor film 11. Patterning 14 to form a second contact hole 15 that at least partially overlaps the first contact hole 10 and reaches the semiconductor layer 11 at least partially; and part of the second contact hole 10. A wiring layer 16 reaching the bottom surface of 15 and connected to the semiconductor film 11 is formed on the third insulating film 14 by a method of manufacturing a semiconductor device.

[0029]

According to the present invention, a part of the semiconductor film 11 to be the channel region of the thin film transistor is formed on the conductive type layer 7 in the semiconductor substrate 1 so as to overlap with the conductive type layer 7 and the semiconductor film 11. A contact hole 15 is formed in the insulating film 14 covering the overlapping area of the contact hole 15
The wiring layer 16 is connected to the semiconductor film 11 through.

Therefore, when the insulating film 14 is etched to form the contact hole 15, even if the semiconductor film 11 in that region disappears, the wiring layer 16 of the wiring layer 16 remains.
Securely connect on the side of. Moreover, even if the bottom of the semiconductor film 11 is largely etched to form a recess in the conductive layer 7, there is no inconvenience because the conductive layer 7 is present to electrically connect the semiconductor film 11 and the wiring layer 16.

In this case, since the semiconductor film 11 serving as the channel region of the thin film transistor is brought into direct contact with the wiring layer 16, even if a natural oxide film is formed on the surface of the conductive layer 7 of the semiconductor substrate 1, this is removed. The insulating film 9 formed between the semiconductor layer 11 and the gate electrode Gp ₁ therebelow is not thinned, and the channel region and the gate electrode Gp ₁ are not short-circuited.

[0032]

1 and 2 are cross-sectional views showing a manufacturing process of an embodiment of the present invention, and FIGS. 3 to 6 are plan views showing a manufacturing process of the embodiment of the device. FIG. 7 shows a MOSFET
FIG. 6 is a general circuit diagram of an SRAM cell using the. In addition,
1 and 2 are cross-sectional views taken along the line AA shown in FIG.

Therefore, an embodiment of the device of the present invention will be described along the steps of forming the SRAM cell shown in FIGS. First,
As shown in FIG. 1 (a), an N well 2 is formed outside the SRAM cell formation region of a semiconductor substrate 1 made of p-type silicon, and a rectangle of the surface of the semiconductor substrate 1 as shown in FIG. 3 (a) is formed. Part that defines the frame-shaped active region X and part of the N well 2
An oxide film 4 for element isolation having a thickness of about several hundreds nm is formed by a selective oxidation method in a portion surrounding the film, and then an insulating film 3 made of SiO _{2 having a} thickness of 10 nm or less is formed on the surface of other regions by a thermal oxidation method. grow up.

In the plan view of the active region X, a part thereof is omitted. Subsequently, as shown in FIG. 3 (a), the photoresist covering the N well 2 and a part of the insulating film 3 in the corner regions of the four corners of the active region X are removed by photolithography to form an opening. 5 is formed, and a part of the semiconductor substrate 1 is exposed from the opening 5.

Next, a polycrystalline silicon film is deposited on the semiconductor substrate 1 by a vapor deposition method (CVD method) to a thickness of several hundreds nm,
After introducing an n-type impurity such as phosphorus or arsenic into the inside, this is patterned to form a driving MOSFE shown in FIG. 7 (a).
The word line WL is formed with the gate electrodes Gn of Tt ₁₁ and t ₁₂ . A mixed gas of CCl ₄ and O ₂ is used for etching the polycrystalline silicon (the same applies hereinafter).

As shown in FIG. 3B, two gate electrodes Gn are formed in two parallel side regions of the rectangular frame-shaped active region X so as to cross the side regions.
It is shaped so as to extend to the opening 5 in the corner region of another active region X. Further, the word line WL extends in a direction orthogonal to the remaining two side regions of the above-mentioned active region X, and a portion intersecting with the side region transfers the transfer MOSFET t.
It becomes the gate electrodes of ₃₁ and t ₃₂ .

Thereafter, as shown in FIGS. 1B and 3B, arsenic is formed in the active region X of the semiconductor substrate 1 by using the gate electrode Gn, the word line WL and the element isolation oxide film 4 as a mask. Are ion-implanted and diffused to form an n-type impurity diffusion layer 6.

The n-type impurity diffusion layer 6 is thereby provided with the driving MOSFETs t ₁₁ and t ₁₂ and the transfer MOSFET t.
₃₁ and t ₃₂ source / drain. Further, the n-type impurity diffusion layer 6 also functions as a bulk wiring, whereby the driving MOSFETs t ₁₁ and t ₁₂ and the transfer MOSFETs ₃₁ and t.
₃₂ is connected as shown in the lower side of FIG. 7 (b).

Further, the active region X is covered with a photomask (not shown), boron is ion-implanted into a partial region of the N well 2, and this is activated to form a p-type impurity diffusion layer 7. Note that the heat treatment for forming the n-type impurity diffusion layer 6 and the p-type impurity diffusion layer 7 may be performed independently, or heat may be used in the subsequent film formation process.

Next, an insulating film 8 made of SiO ₂ is grown to a thickness of 100 nm on the entire surface by the CVD method, and then a polycrystalline silicon film is deposited thereon to a thickness of 50 nm by the CVD method. After introducing arsenic by means of photolithography, patterning is carried out,
As shown in FIGS. 4C and 4C, a gate electrode Gp ₁ below the thin film transistor is formed.

The lower gate electrode Gp ₁ is formed in a region covering the n-type impurity diffusion layers 6 at the four corners of the active region X and the gate electrodes Gn of the driving MOSFETs t ₁₁ and t ₁₂ whose drains are these regions. ..

Subsequently, as shown in FIG. 1 (d), the CVD
Forming an insulating film 9 of SiO _{2 having a} thickness of 20 nm by
Further, regions other than the p-type impurity diffusion layer 7 are covered with a photoresist (not shown), and the insulating films 3, 8 and 9 on the p-type impurity diffusion layer 7 are subjected to reactive ion etching (RI).
The contact hole 10 is formed by removing it by the E) method. A mixed gas of CHF ₃ and He is used for etching SiO ₂ .

Next, it was exposed from the contact hole 10.
Without removing the natural oxide film on the surface of the p-type impurity diffusion layer 7,
As shown in Fig. 2 (e), exposed from the contact hole 10.
From the surface of the p-type impurity diffusion layer 7 to the uppermost insulating film 9
Polycrystalline silicon film with a film thickness of 20 nm in the entire area along the surface
11 is formed by the CVD method. In this case SiH_Four, Si ₂H
₆And other gases are used.

Then, a photoresist (not shown) is formed on the lower side of the thin film transistor so as to overlap the gate electrode Gp _1, and the acceleration energy is 10 keV and the dose is 1 × 10 ¹⁴ /
Boron is ion-implanted under the condition of cm ³ to form a polycrystalline silicon film 1
Introducing a p-type impurity into 1.

After that, the polycrystalline silicon film 11 is patterned by the photolithography method, and as shown in FIG. 4D, a region along the word line WL and a transfer MOSFET t ₁₁ extending from the region are formed. , t ₁₂ gate electrode G
The planar shape is such that it reaches n.

In this case, the polycrystalline silicon film 11 remaining along the word line WL serves as a Vcc voltage wiring, and further extends through the contact hole 10 to the upper surface of the p-type impurity diffusion layer 7.

Next, as shown in FIG. 2F, an insulating film 12 made of SiO ₂ is deposited to a thickness of 50 nm by the CVD method. In this case, the reason why the insulating film 9 is thicker than the insulating film 9 covering the lower gate electrode Gp _{1 is} that the hydrofluoric acid treatment or the like at the time of growing the polycrystalline silicon to be the upper gate electrode Gp ₂ formed in the next step is taken into consideration. is there.

Thereafter, as shown in FIGS. 2 (f) and 5 (e), the insulating films 8, 9, 12 and the polycrystalline silicon film 11 above the gate electrodes Gn of the driving MOSFETs t ₁₁ , t ₁₂ are formed.
Then, the lower gate electrode Gp ₁ is etched by a photolithography method to form an opening 13, and then natural oxidation is formed on the surface of the gate electrode Gn of the driving MOSFETs t ₁₁ and t ₁₂ exposed from the opening 13. The film is removed with hydrofluoric acid.

Further, a polycrystalline silicon film is formed by the CVD method, phosphorus is ion-implanted, and then this is patterned by the photolithography method to form a region facing the lower gate electrode Gp ₁ of the thin film transistor in FIG. ), Fig. 5
An upper gate electrode Gp ₂ as shown in (e) is formed.

A part of the gate electrode Gp _{2 on} the upper side enters into the opening 13 under the gate electrode Gp ₁ and Gp ₂ of the thin film transistor, and the polycrystalline silicon film 11 becomes the drain of another thin film transistor. And are electrically connected to the n-type impurity diffusion layer 6 serving as the drains of the driving MOSFETs t ₁₁ and t ₁₂ .

FIG. 5 (f) shows the polycrystalline silicon film 11 formed as described above and the two gate electrodes Gp ₁ and Gp ₂ formed above and below the insulating films 9 and 14, respectively. If such thin film transistors t ₂₁ and t ₂₂ are completed and are used as load MOSFETs, the circuit on the upper side of FIG. 7B and the wiring shown by the broken line are formed.

[0052] After this, after forming the entire insulating film 20 as shown in FIG. 6, the region between the active region X in MOSFETt drive formed adjacent _{11, t 11, t 21,} t 22 Contact hole 21 exposing n-type impurity diffusion layer 6
And a wiring (not shown) for supplying the voltage Vss therethrough is formed.

Next, as shown in FIG. ₂ (g), SiO 2 on the entire
After depositing the interlayer insulating film 14 made of a laminated film of BPSG and BPSG, the insulating films 12 and 20 and the interlayer insulating film 14 on the p-type impurity diffusion layer 7 are opened by a dry etching method using a gas containing CHF ₃ . Another contact hole 15 that overlaps the contact hole 10 on the p-type impurity diffusion layer 7 is formed. At the same time, the driving MO of the source / drain n-type impurity diffusion layer 6 of the transfer MOSFETs t ₃₁ and t ₃₂ is also used.
A contact hole 22 is provided to expose a portion that is not connected to SFETs t ₁₁ and t ₁₂ .

Next, an aluminum film is deposited by the sputtering method, and is patterned by the photolithography method to form the contact hole 15 on the p-type impurity diffusion layer 7.
When the Vcc power supply wiring layer 16 passing through the
The power supply wiring layer 16 comes into contact with the polycrystalline silicon film 11 and becomes conductive. At the same time, by forming the bit lines BL ₁ and BL ₂ passing through the contact hole 22 exposing the n-type impurity diffusion layer 6, the SRAM cell of the circuit as shown in FIG. 7A is completed.

According to the SRAM cell described above, the polycrystalline silicon film 11 is thinned when the contact hole 15 is formed on the p-type impurity diffusion layer 7, or the p-type impurity diffusion is performed through the film. Although reaching the upper portion of the layer 7, the polycrystalline silicon film 11 is in a state of being connected to either the side edge portion or the lower surface of the Vcc power supply wiring layer 16.

Even if a natural oxide film is present on the surface of the p-type impurity diffusion layer 7, there is no problem because the polycrystalline silicon film 11 is in contact with the side portion of the Vcc power supply wiring layer 16. In addition, when the polycrystalline silicon film 11 is desired to be connected to the p-type impurity diffusion layer 7, if the contact hole 15 is formed by penetrating the polycrystalline silicon film 11, the natural oxide film is removed. Conduction can be achieved between the wiring layer 16 and the p-type impurity diffusion layer 7. If the natural oxide film is attached to the p-type impurity diffusion layer 7 exposed from the contact hole 15, there is no problem in removing it with hydrofluoric acid.

[0057]

As described above, according to the present invention, a part of the semiconductor film which becomes the channel region of the thin film transistor is formed on the conductive type layer in the semiconductor substrate, and
Since the contact hole is formed in the insulating film covering the region where the conductive type layer and the semiconductor film overlap, and the wiring layer is connected to the semiconductor film through the contact hole, the insulating film is etched to form the contact hole. Even if the semiconductor film disappears at this time, the wiring layer can be surely connected to the side surface of the semiconductor layer to achieve conduction.

Further, even if the semiconductor film is deeply etched to form a recess in the conductive layer, the conductive layer is present to electrically connect the semiconductor film and the wiring layer.
A short circuit with other wiring layers can be prevented.

In this case, since the semiconductor film to be the channel region of the thin film transistor is brought into direct contact with the wiring layer,
Even if a natural oxide film is formed on the surface of the conductive layer of the semiconductor substrate, it is not necessary to remove it, and the insulating film formed between the semiconductor layer and the gate electrode thereunder is formed into a thin layer by hydrofluoric acid treatment. Therefore, short circuit between the channel region and the gate electrode can be prevented in advance.

[Brief description of drawings]

FIG. 1 is a cross-sectional view (1) showing a manufacturing process of a device according to an embodiment of the present invention.

FIG. 2 is a sectional view (No. 2) showing the manufacturing process of the device according to the embodiment of the present invention.

FIG. 3 is a plan view (1) showing the manufacturing process of the device according to the embodiment of the present invention.

FIG. 4 is a plan view (No. 2) showing the manufacturing process of the device according to the embodiment of the present invention.

FIG. 5 is a plan view (3) showing the manufacturing process of the device of the embodiment of the present invention.

FIG. 6 is a plan view (No. 4) showing the manufacturing process of the device according to the embodiment of the present invention.

FIG. 7 is a circuit diagram showing an SRAM cell.

FIG. 8 is a plan view (part 1) showing a pattern of each layer of a conventional SRAM cell.

FIG. 9 is a plan view (part 2) showing a pattern of each layer of a conventional SRAM cell.

FIG. 10 is a cross-sectional view showing first and second examples of a conventional SRAM cell.

FIG. 11 is a sectional view showing a third example of a conventional SRAM cell.

[Explanation of symbols]

X active region WL the word line t _11, t ₁₂ driving MOSFET t _31, t ₃₂ transfer MOSFET t _21, t ₂₂ load MOSFET Gn, Gp _1, Gp ₂ gate electrode 1 semiconductor substrate 2 N-well 3 insulating film 4 elements Isolation oxide film 5, 13 Opening 6 n-type impurity diffusion layer 7 p-type impurity diffusion layer (conductive layer) 8, 9, 12 Insulating film 10, 13, 15 Contact hole 11 Polycrystalline silicon film (semiconductor layer) 14 Interlayer Insulation film 16 Vcc Power supply wiring layer layer

Claims (3)

[Claims] 1. A thin film transistor (t ₂₁ , t ₂₂ ) formed on a first insulating film (3, 8, 9) above a semiconductor substrate ( ₁ ) and provided with a gate electrode (Gp ₁ ) at least on the lower side. In a semiconductor device having a first contact hole formed in the first insulating film (3, 8, 9), the semiconductor film (11) serving as a channel region of the thin film transistor (t ₂₁ , t ₂₂ ). At least a second insulating film (14) that extends through the (10) on the conductive type layer (7) in the semiconductor substrate (1) and covers the thin film transistors (t ₂₁ , t ₂₂ ). The wiring layer (16), which partially passes through the second contact hole (15) overlapping the first contact hole (10), is formed into the second insulating film (1).
4) A semiconductor device characterized by being formed on. 2. The thin film transistors (t ₂₁ , t ₂₂ ) are
The semiconductor device according to claim 1, wherein the semiconductor device is a load transistor of an SRAM cell. 3. A step of forming a gate electrode (Gp ₁ ) of a thin film transistor (t ₂₁ , t ₂₂ ) on a first insulating film (8) on a semiconductor substrate (1), and the gate electrode (Gp ₁ ) A step of forming a second insulating film (9) covering the semiconductor substrate (1), and selecting an insulating film (3, 8, 9) on the conductive type layer (7) formed on the upper part of the semiconductor substrate (1). Forming a first contact hole (10) by performing a selective etching, and without removing a native oxide film formed on the surface of the semiconductor substrate (1) exposed from the first contact hole (10). Then, a semiconductor film (11) to be a channel region of the thin film transistor (t ₂₁ , t ₂₂ ) is formed on the second insulating film (9) and along the inner circumference and the bottom surface of the first contact hole (10). And a step of forming a third insulating film (14) covering the semiconductor film (11). After that, the third insulating film (14) is patterned so as to at least partially overlap the first contact hole (10) and to reach the semiconductor layer (11) at least in the second contact hole (15). ) Is formed, and a wiring layer (16) that partially reaches the bottom surface of the second contact hole (15) and connects to the semiconductor film (11) is provided with the third insulating film (14). A method of manufacturing a semiconductor device, the method comprising: