JPH03205870A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable miniaturization of the size of a memory transistor and the distance between a memory transistor and a select transistor by constituting the gate electrode of a select transistor of the lower layer electrode consisting of a floating-gate electrode constituent and the upper layer electrode consisting of a control-gate electrode constituent, or by other methods. CONSTITUTION:In a semiconductor device comprising the following: memory transistors, having select transistors and tunnel insulation films 5a that constitute a 2-transistor memory cell, floating gate electrodes 6, and control electrodes 8; and transistors constituting the peripheral circuit, the control gate electrode 8 and the floating gate electrode 6 of a memory transistor are formed in self- alignment, and the gate electrode of a select transistor is constituted of the lower layer electrode 9 consisting of a floating-gate electrode constituent and the upper layer electrode 9a consisting of control gate electrode constituent: these electrodes 9a, 9 are formed in self-alignment so that this device can be constituted by electric connection of the electrodes 9, 9a.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a select transistor of an electrically rewritable nonvolatile semiconductor memory.

rPrior art] Electrically rewritable non-volatile semiconductor memory (E
E P R. The memory cell OM> is composed of a memory 1 transistor and a select l-1 transistor, and conventionally, the gate electrode of the select l- transistor is made of the same material as the control gate electrode of the memory transistor.

A cross-sectional view of an example of a conventional EEPROM memory cell is shown in FIG.

A field oxide film (
After forming the first gate oxide M4 and the tunnel insulating film 5a, the first layer of polycrystalline Si film is deposited and processed to form the floating gate electrode. 6
form.

Subsequently, a second gate oxide film 7 is formed by thermal oxidation, and a second layer of polycrystalline Si film is deposited. Next, by etching the second layer polycrystalline Si film, the control gate electrode 8 and the select transistor electrode (hereinafter referred to as
A selection gate electrode 9 is formed.

Next, a side oxide film 10 is formed by thermal oxidation on the surfaces of the control gate electrode 8 and the selection gate electrode 9, as well as on the surfaces exposed by the etching process of the control gate electrode 8 and the selection gate electrode 9. Using the electrode 8 and selection gate electrode 9 as a mask, phosphorous is ion-implanted to form an n-type diffusion layer 11.

Subsequently, an interlayer insulating film 12 is deposited, an n-type diffusion layer contact hole 13 is opened, an aluminum layer and wiring 15 are formed,
The horizontal structure of the memory cell shown in FIG. 8 is formalized.

In the above memory cell, the control gate electrode 8 and the selection gate electrode 9 are formed in the same process, and the control gate electrode 8 and the floating gate electrode 6 are not formed in a self-aligned manner. There is also a method of forming the control gate electrode 8 and the floating gate electrode 6 in a self-aligned manner, and forming the control gate electrode 8 and the selection gate electrode 9 in separate steps.

[Problem to be solved by the invention]

In the structure in which the control gate electrode 8 and the selection gate electrode 9 are formed in the same process and the control gate electrode 8 and the floating gate electrode 6 are not formed in a self-aligned manner, the control gate electrode 8 and the selection gate electrode 9 are Although the margin can be made small, it is necessary to provide a margin between the control gate electrode 8 and the selection gate electrode 9. Therefore, the distance between the memory transistor and the select transistor becomes the minimum value, but the size of the memory transistor itself becomes larger, and there is a disadvantage that the size of the memory cell cannot be reduced to the minimum value. .

On the other hand, in a method in which the control gate electrode 8 and the floating gate electrode 6 are formed in a self-aligned manner and the control gate electrode 8 and the selection gate electrode 9 are formed in separate steps, the size of the memory I-transistor is set to the minimum value. However, it is necessary to provide a margin between the control gate electrode 8 and the selection gate electrode 9. For this reason, the distance between the memory transistor/transistor and the select transistor does not reach the minimum value, and in this case as well, there is a drawback that the size of the memory cell cannot be reduced to the minimum value.

Note that if the selection gate electrode 9 can be formed at the same time as the control gate electrode 8 and the floating gate electrode 6 are formed in a self-aligned manner, the size of the memory transistor can be minimized, and the size of the memory transistor can be reduced to a minimum value. Since the distance between the memory cell and the select transistor can be minimized, the size of the memory cell can be minimized. However, if the structure of the conventional selection gate electrode 9 remains unchanged, it is very difficult to manufacture such a memory cell elliptical structure.

That is, in the etching process that forms the control gate electrode 8 and the floating gate electrode 6 in a self-aligned manner and also forms the selection gate electrode 9, only the second layer of polycrystalline Si film is etched on the selection transistor side. On the other hand, on the memory transistor side, it is necessary to etch the second layer of polycrystalline Si film, the second gate oxide film 7, and the first layer of polycrystalline Si film. The second gate oxide film 7 on the region to be formed will be completely etched away, and the p-type Si semiconductor substrate 1 will be exposed and damaged in this region.

[Means to solve the problem]

The semiconductor device of the present invention includes a select transistor and a tunnel insulating film that form a two-channel transistor memory cell.
In a semiconductor device including a memory transistor having a floating gate electrode and a control gate electrode, and a transistor forming an oval peripheral circuit, the control gate electrode and the floating gate electrode of the memory transistor are formed in a self-aligned manner, and the control gate electrode and the floating gate electrode are formed in a self-aligned manner. The gate electrode of the transistor is horizontally arranged as a two-layer electrode consisting of a lower layer electrode made of an electrode material forming a floating gate electrode and an electrode material forming an oval control gate electrode,
The upper layer electrode and the lower layer electrode are formed in a self-aligned manner, and
The lower layer electrode and the upper layer electrode are electrically connected to form an ellipse.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a layout diagram of the first embodiment of the present invention, and FIGS. 2 and 3 are cross-sectional views along the line xx' and Y-Y'' of FIG. Only a memory cell portion consisting of a transistor is illustrated.

In this example, a floating case is formed by the first layer of polycrystalline Si film.
1. Electrode 6 and select I-1 - An electrode 9 is formed on the select case 1 which becomes the lower gate electrode of the transistor, and the second layer of polycrystalline Si film serves as the control gate electrode 8 and the select gate electrode. (Upper layer gate electrode) 9a is formed, and the selection gate electrode 9 and the selection gate 1 to electrode 9a are electrically connected to the selection gate 1 to electrode contact 1 through the hole 14 by an aluminum wire 15. .

The manufacturing method of this example will be explained.

First, a thick field oxide film 2 made of Si02 is selectively formed on a p-type Si semiconductor substrate 1. Next, arsenic is selectively implanted and heat treated to achieve a concentration of 5X.
An n-type diffusion layer 3 of about 1018 cm-3 is formed to serve as a source train region of a memory transistor. Then, by wet oxidation at, for example, 900°C, a thickness of 4. 0nm
The first gate oxide film 4 is formed with an energy of 150 keV and a dose of 7×10” to control the threshold voltage.
cm-2 and energy-50keV, dose 1×10
Boron ion implantation is performed twice with I1cm-2.

Next, the first gate oxide film 4 in the tunnel region 5 is removed, and a tunnel insulating film 5a made of Si02 and having a thickness of 8 nm is formed by dilute oxidation.

Next, a first layer of polycrystalline Si film is deposited to a thickness of 250 nm over the entire surface by chemical vapor deposition, and phosphorus is added by thermal diffusion.

Next, primary processing for forming a floating gate electrode is performed. By this process, the first layer of polycrystalline Si film is left in the areas where select 1 to transistors are formed, and the first layer of polycrystalline Si film is left in the area (not shown) where transistors forming the peripheral circuit are formed. Remove membrane.

Subsequently, after removing the exposed first gate oxide film 4, the surface of the first layer polycrystalline S1 film and the P-type Si semiconductor substrate 1 are removed.
A second gate oxide film 7 having a thickness of 30 nm is formed on the exposed surface by thermal oxidation.

Next, a second layer of polycrystalline Si film is deposited on the entire surface to a thickness of about 400 nm by chemical vapor deposition, and phosphorus is added by thermal diffusion to improve conductivity.

Next, using anisotropic dry etching, the second layer polycrystalline SJ film is processed in an aF manner, and the second gate oxide film 7 and the first layer polycrystalline Si film are successively selected. to remove. Due to this anisotropic dry etching, in the region where the memory transistor is formed, the floating gate electrode 6 made of the first layer of polycrystalline Si film and the control case 1/electrode 8 made of the second layer of polycrystalline Si film are formed. are formed in a self-aligned manner, and in the region where the select transistor is formed, a lower layer gate I consisting of the first layer polycrystalline Si film to the select gate electrode 9 which is the electrode and the second layer polycrystalline Si film are formed. The selection gate electrode (upper layer gate electrode) 9a is formed in a self-aligned manner. Note that at this time, the second layer of polycrystalline Si film is left unprocessed in the region where a transistor is to be formed, which is adjacent to the peripheral circuit.

Next, the second layer of polycrystalline Si film on the region where the transistors forming the peripheral circuit will be formed is processed by anisotropic try-soching to form the gate electrode ( (not shown). During this etching, the selection gate electrode (upper layer gate electrode) 9a in the vicinity of which the selection gate electrode contact 1/hole will be formed in a later step is selectively removed.

Subsequently, gate electrodes 6, 8, 9.9a,
A side oxide film 10 having a thickness of 150 nm is formed by dry oxidation at 900 DEG C. on the exposed surface and side surfaces of the polycrystalline Si of the gate L-electrode of the I-transistor for the peripheral circuit. Next, using the gate electrode 8.9a and the gate electrode of the transistor for the peripheral circuit as a mask, phosphorus is applied at an energy of 7.
0keV. Ion implantation was performed at a dose of 5 x 1014 cm-2, and the temperature was 1000°C in a mixed atmosphere of oxygen and inert gas.
Heat treatment is performed for 20 minutes to form the n-type diffusion layer l1 and at the same time further thicken the side oxide film 10.

Thereafter, an interlayer insulating film 12 made of PSG is deposited, and an n-type diffusion layer contact hole 13 and a selection gate electrode contact hole 14 are formed at the position where the selection gate electrode (upper layer gate electrode>9a is selectively removed). Next, an aluminum wiring 15 is formed, thereby electrically connecting the selection gate electrode 1 and the selection gate electrode (upper layer gate electrode) 9a.

FIG. 4 is a layout diagram of a second embodiment of the present invention,
FIG. 5 is a sectional view taken along the line Z--Z'' in FIG. 4.

In this embodiment, the first and second polycrystalline Si contact holes 16
Therefore, the selection gate 1 to the electrode (upper layer gate electrode>9a) are directly connected to the selection gate 1 and electrode 9.

The formation of the first and second polycrystalline Si contact holes 16
Etching is performed after the gate oxide film 7 has been shaped.

In this embodiment, since the opening area of the contact 1 and the hole 16 is large, the resistance of the gate electrode of the select transistor can be lowered compared to the first embodiment. Furthermore, in this embodiment, since the aluminum wiring 15 is not required for connecting the selection gate electrode (upper layer gate electrode) 9a and the selection gate electrode 9, the size of the memory cell can be made smaller than in the first embodiment. .

〔Effect of the invention〕

As described above, the present invention provides a semiconductor device including a memory transistor having a select transistor, a tunnel insulating film, a floating gate electrode, and a control gate electrode constituting a two-transistor memory cell, and a transistor forming a peripheral circuit. , forming a control gate electrode and a floating gate electrode of a memory transistor in a self-aligned manner,
The gate electrode of the select transistor is composed of a lower layer electrode made of an electrode material forming a floating gate electrode and an upper layer electrode made of an electrode material forming a control gate electrode, and the upper layer electrode and the lower layer electrode are formed in a self-aligned manner. , and by electrically connecting the lower layer electrode and the upper layer electrode and placing them horizontally, the size of the memory transistor can be minimized, and the distance between the memory transistor and the select transistor can also be minimized. As a result, the size of the memory cell can be minimized.

[Brief explanation of drawings]

FIG. 1 is a layout diagram of the first embodiment of the present invention, FIGS. 2 and 3 are cross-sectional views taken along the line xx' and Y-Y'' of FIG. 1, and FIG. 4 is a cross-sectional view taken along the line 5 is a sectional view taken along line zz' in FIG. 4, and FIG. 6 is a sectional view of a conventional semiconductor device. 1...p-type Si semiconductor Substrate, 2... Field oxide film, 3, 11... N-type diffusion layer, 4... First gate oxide film, 5... Tunnel region, 5a... Tunnel insulating film, 6... Floating gate electrode, 7... Second gate oxide film, 8... Control gate electrode, 9... Selection gate electrode, 9a... Selection gate electrode (upper layer gate electrode), 10
... Side oxide film, 12... Interlayer insulating film, 13...
n-type diffusion layer contact hole, 14... selection gate electrode contact hole, 15... aluminum wiring, l6...
First and second polycrystalline Si contact holes.

Claims (1)

[Scope of Claim] A semiconductor device comprising a memory transistor having a select transistor, a tunnel insulating film, a floating gate electrode, and a control gate electrode constituting a two-transistor memory cell, and a transistor constituting a peripheral circuit, the memory transistor comprising: The control gate electrode and the floating gate electrode are formed in a self-aligned manner, and the gate electrode of the select transistor is made of a lower layer electrode made of an electrode material making up the floating gate electrode and an electrode material making up the control gate electrode. an upper layer electrode, the upper layer electrode and the lower layer electrode are formed in a self-aligned manner, and the lower layer electrode and the upper layer electrode are electrically connected. Semiconductor equipment.