KR0142602B1 - Method for manufacturing a flash Y pyrom device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for manufacturing a flash EEPROM device. The present invention relates to a method for manufacturing a flash easy pyrom device comprising an ONO (lower oxide film-nitride film-top oxide film) structure of a dielectric film of a memory cell. A method of manufacturing a flash Y pyrom device in which a gate oxide film of a high voltage transistor formed in a peripheral region is formed by using an upper oxide film of a dielectric film to improve the gate oxide film characteristics of the transistor, thereby improving the reliability of the device and simplifying the process. It is about.

Description

Method for manufacturing a flash EEPROM device.

1A to 1D are cross-sectional views of a device for explaining a method of manufacturing a conventional flash ypyrom device.

2A through 2E are cross-sectional views of a device for explaining a method of manufacturing a flash y-pyrom device according to the present invention.

* Explanation of symbols for main parts of the drawings

1: Silicon substrate 2: Field oxide film

3 and 13: tunnel oxide 4 and 14: first polysilicon layer

4A and 14A: Floating gates 5 and 12: Dielectric film

6 and 18: second polysilicon layer 6A and 18A: control gate

7: insulating film 8 and 20: interlayer insulating film

9 and 19: source and drain regions 10 and 10A: primary and secondary gate oxides

11 and 21: gate oxide 15 and 17: lower and upper oxide

16: Nitride film 18B: Gate electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a flash EEPROM device, and more particularly, in the manufacture of a flash Y pyrom device in which a dielectric film of a memory cell has an ONO (lower oxide film-nitride film-top oxide film) structure. The present invention relates to a method for manufacturing a flash Y pyrom device in which a gate oxide film of a high voltage transistor formed in a region is formed by using an upper oxide film of a dielectric film to improve the characteristics of the gate oxide film and simplify the process.

In general, an electrically erasable read only memory (EEPROM) device having both an electric program and an erase function in a semiconductor device manufacturing process has a high voltage. The circuit requires a high voltage transistor and a low voltage transistor, respectively.

A method of manufacturing a conventional flash ypyrom device will now be described with reference to FIGS. 1A to 1D.

1A to 1D are cross-sectional views of a device for describing a method of manufacturing a conventional flash ypyrom device.

FIG. 1A shows a field oxide film 2 in the field region F of the silicon substrate 1 to electrically separate the memory cell region MC, the high voltage transistor region HV and the low voltage transistor region LV, respectively. After the formation, the tunnel oxide film 3, the first polysilicon layer 4, the dielectric film 5, and the second polysilicon layer 6 are sequentially formed on the entire upper surface, and TEOS is deposited thereon to form an insulating film ( It is sectional drawing of the state which formed 7).

FIG. 1B is a photosensitive film (not shown) applied to the entire upper surface, and the photoresist is patterned through a photolithography and etching process using a gate electrode mask of a memory cell, and self-aligned using the patterned photoresist as a mask. The memory cell region MC by sequentially patterning the insulating film 7, the second polysilicon layer 6, the dielectric film 5, the first polysilicon layer 4, and the tunnel oxide film 3 by an etching method. ), A gate electrode having a structure in which the tunnel oxide film 3, the floating gate 4A, the dielectric film 5, the control gate 6A, and the insulating film 7 are stacked.

After that, the source and drain regions 9 are formed in the exposed silicon substrate 1 in the memory cell region MC by performing an impurity ion implantation process.

FIG. 1C shows a high-temperature oxide film and a nitride film sequentially formed on the entire upper surface after impurity ion implantation for the threshold voltage is applied to the exposed silicon substrate 1 of the high voltage transistor region HV and the low voltage transistor region LV. The insulating film 8 is formed and the interlayer insulating film 8 is patterned so that the silicon substrate 1 of the high voltage transistor region HV is exposed, and then an oxidation process is performed to apply the high voltage to the exposed silicon substrate 1. It is sectional drawing of the state which formed the primary gate oxide film 10 of a transistor.

In FIG. 1D, the interlayer insulating film 8 is patterned so that the silicon substrate 1 of the low voltage transistor region LV is exposed in the state of FIG. 1C and then subjected to an oxidation process to perform a low voltage on the exposed silicon substrate 1. A cross-sectional view of the gate oxide film 11 of the transistor for forming is shown, wherein the primary gate oxide film 10 of the high voltage transistor is also grown to form a thick secondary gate oxide film 10A.

However, since the gate oxide film of the high voltage transistor formed as described above undergoes two oxidation processes, it is difficult to control its thickness, and impurities are added between the first oxidation process and the second oxidation process and contamination by the photoresist film occurs during the photo process. As a result, the gate oxide film is degraded.

In addition, the nitride film used as the interlayer insulating film is worn as a cause of defect generation.

Accordingly, in the manufacture of a flash Y pyrom device in which a dielectric film of a memory cell is formed of an ONO (lower oxide film-nitride film-top oxide film) structure, a gate oxide film of a high voltage transistor formed in a peripheral region is formed by using an upper oxide film of a dielectric film. It is an object of the present invention to provide a method for manufacturing a flash Y pyrom device that can solve the above-mentioned disadvantages by forming.

In order to achieve the above object, the present invention provides a field oxide film in a field region of a silicon substrate to electrically separate a memory cell region, a high voltage transistor region, and a low voltage transistor region, respectively. Sequentially forming the polysilicon layer, the lower oxide film, and the nitride film, and sequentially forming the nitride film, the lower oxide film, the first polysilicon layer, and the tunnel oxide film through a photolithography and an etching process using a mask for the floating gate electrode from the step. Forming a structure in which a tunnel oxide film, a floating gate, a lower oxide film, and a nitride film are stacked in a memory cell region by patterning, and from the step, an impurity ion for adjusting a threshold voltage on an exposed silicon substrate of the high voltage transistor region and the low voltage transistor region; After the injection, the upper oxide film and the second upper surface Sequentially forming the silicon layer, patterning the second polysilicon layer and the upper oxide layer in the memory cell region sequentially through the photolithography and etching process using the mask for the control gate electrode. And forming a gate electrode having a structure in which the control gates are stacked, and sequentially patterning the second polysilicon layer and the upper oxide layer remaining in the photo and etching process using the gate electrode mask of the high voltage transistor. Forming a gate electrode in the semiconductor transistor region, and performing source impurity ion implantation from the step to form source and drain regions on the exposed silicon substrate of the memory cell region; After forming the insulating film, seal in the transistor region for low voltage Patterning the interlayer insulating film so that the cones substrate is exposed and is characterized in that by performing an oxidation process comprising a step of forming a gate oxide film of low-voltage transistor on the exposed silicon substrate.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A through 2E are cross-sectional views of a device for describing a method of manufacturing a flash y-pyrom device according to the present invention.

2A shows a field oxide film 2 in the field region F of the silicon substrate 1 to electrically separate the memory cell region MC, the high voltage transistor region HV, and the low voltage transistor region LV, respectively. After formation, it is sectional drawing of the state which formed the tunnel oxide film 3, the 1st polysilicon layer 4, the lower oxide film 15, and the nitride film 16 sequentially on the whole upper surface.

FIG. 2B illustrates the nitride cell 16, the lower oxide layer 15, the first polysilicon layer 14 and the tunnel oxide layer 13 by sequentially patterning the photolithography and etching processes using a mask for a floating gate electrode. It is sectional drawing of the state which formed the structure in which the tunnel oxide film 13, the floating gate 14A, the lower oxide film 15, and the nitride film 16 were laminated | stacked in the area | region MC.

FIG. 2C shows the upper oxide film 17 and the second poly on the entire upper surface of the silicon substrate 1 of the high voltage transistor region HV and the low voltage transistor region LV. It is sectional drawing of the state which formed the silicon layer 18 sequentially.

FIG. 2D illustrates a pattern of the second polysilicon layer 18 and the upper oxide layer 15 of the memory cell region MC sequentially and through the photolithography and etching process using a mask for a control gate electrode on the nitride layer 16. A gate electrode having a structure in which the upper oxide film 17 and the control gate 18A are stacked is formed.

Subsequently, the second polysilicon layer 18 and the upper oxide layer 17 remaining in the photolithography and etching processes using the gate electrode mask of the high voltage transistor are sequentially patterned to form the gate electrode 18B in the high voltage transistor region HV. The upper oxide film 17 is used as a gate oxide film of a high voltage transistor.

FIG. 2E illustrates an impurity ion implantation process to form a source and a drain region 19 on the exposed silicon substrate 1 of the memory cell region MC, and deposit TEOS on the entire upper surface to form the interlayer insulating layer 20. After the formation, the interlayer insulating layer 20 is patterned so that the silicon substrate 1 of the low voltage transistor region LV is exposed and subjected to an oxidation process, thereby forming a gate oxide layer of the low voltage transistor on the exposed silicon substrate 1. It is sectional drawing of the state which formed 21).

As described above, according to the present invention, in the fabrication of a flash Y pyrom device in which a dielectric film of a memory cell has an ONO (lower oxide film-nitride film-top oxide film) structure, a gate oxide film of a high voltage transistor formed in a peripheral region is formed on top of a dielectric film. It is easy to control the thickness by using the oxide film, and it is possible to prevent contamination due to the penetration of impurities and the use of the photoresist film, so that the characteristics of the gate oxide film can be improved, and the process yield can be increased by simplifying the process. Excellent effect

Claims (2)

In the method of manufacturing a flash Y pyrom device, in order to electrically isolate the memory cell region, the high voltage transistor region and the low voltage transistor region, a field oxide film is formed in the field region of the silicon substrate, and the tunnel oxide film, Sequentially forming the polysilicon layer, the lower oxide film, and the nitride film, and sequentially forming the nitride film, the lower oxide film, the first polysilicon layer, and the tunnel oxide film through a photolithography and an etching process using the mask for the floating gate electrode from the step. Forming a structure in which a tunnel oxide film, a floating gate, a lower oxide film, and a nitride film are stacked in a memory cell region by patterning the impurity ions in the exposed silicon substrate of the high voltage transistor region and the low voltage transistor region from the step; After the injection, the upper oxide film and the second upper part Sequentially forming the silicon layer, and patterning the second polysilicon layer and the upper oxide layer in the memory cell region sequentially through the photolithography and etching process using the mask for the control gate electrode. And forming a gate electrode having a structure in which the control gates are stacked, and sequentially patterning the second polysilicon layer and the upper oxide layer, which are left in the photolithography and etching processes, using the gate electrode mask of the high voltage transistor. Forming a gate electrode in the transistor region, forming a source and a drain region on an exposed silicon substrate in the memory cell region by performing an impurity ion implantation process from the step; Silicon in the low voltage transistor region after forming an insulating film Patterning the interlayer insulating film to expose a substrate and performing an oxidation process to form a gate oxide film of a low voltage transistor on the exposed silicon substrate. The method of claim 1, wherein TEOS is deposited on the interlayer insulating layer.