KR0147256B1 - Ipyrom and Ipyrom Manufacturing Process - Google Patents
Ipyrom and Ipyrom Manufacturing ProcessInfo
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- KR0147256B1 KR0147256B1 KR1019940015089A KR19940015089A KR0147256B1 KR 0147256 B1 KR0147256 B1 KR 0147256B1 KR 1019940015089 A KR1019940015089 A KR 1019940015089A KR 19940015089 A KR19940015089 A KR 19940015089A KR 0147256 B1 KR0147256 B1 KR 0147256B1
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- oxide film
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/681—Floating-gate IGFETs having only two programming levels
- H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체 기억소자인 이이피롬에 관한 것으로, 특히 고농도 불순물의 매몰산화막을 형성시키지 않아 셀크기 및 공정단계를 감소시킨 이이피롬에 적합하도록 한 새로운 구조의 이이피롬소자와 이의 제조공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a ypirom, a semiconductor memory device, and more particularly, to a new pyromium device having a novel structure suitable for ypirom, which has reduced cell size and process steps by not forming a buried oxide film of high concentration impurities. .
이를 위하여 자기정렬 LDD(Self aligning Lightly Doped Drain)공정을 도입하여 소오스영역 및 드레인영역을 형성시키고, 터널산화막에 의한 게이트산화막의 산화를 방지하였으며, 플로팅게이트와 콘트롤게이트의 위치가 반전되고 고농도 불순물의 매몰산화막(P형 반도체기판인 경우 n+매몰산화막)의 역할을 콘트롤게이트가 대신하도록 하였다.To this end, self-aligning lightly doped drain (LDD) processes are introduced to form source and drain regions, to prevent oxidation of gate oxides by tunnel oxides, to reverse the positions of floating gates and control gates, The control gate replaces the buried oxide film (n + buried oxide film in the case of P-type semiconductor substrate).
Description
제1도는 종래의 이이피롬셀을 도시한 도면.1 is a view showing a conventional ypyrom cells.
제2도는 본 발명에 따른 이이피롬의 제조공정단계를 도시한 도면.2 is a view showing the manufacturing process step of ypyrom according to the present invention.
제3도는 본 발명에 따른 이이피롬셀을 도시한 도면.3 is a diagram showing an ipyrom cell according to the present invention.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10.30:이이피롬셀 10-1.30-1:레이아웃10.30: ipromcel 10-1.30-1: layout
11.20.32:반도체기판 12.27.33:소오스영역11.20.32: Semiconductor substrate 12.27.33: Source area
13.28.31:드레인영역 14:n+매몰산화막13.28.31: Drain region 14: n + investment oxide
15.21-1.34-1:게이트산화막 16.25.35:터널산화막15.21-1.34-1: Gate oxide 16.25.35: Tunnel oxide
16-1:터널 창 17.26.37:플로팅게이트16-1: Tunnel window 17.26.37: Floating gate
18.21.34:콘트롤게이트 19.24.38:층간절연층18.21.34: Control gate 19.24.38: Interlayer insulation layer
21-2.34-2:측면산화막 22:사진감광제21-2.34-2: Side oxide film 22: Photosensitive agent
23.36:n-영역 A.A' :활성영역23.36: n-region A.A ': active region
본 발명은 반도체 기억소자인 이이피롬(EEPROM;Electrically Erasable Programmable Read Only Memory)에 관한 것으로, 특히 고농도 불순물의 매몰산화막을 형성시키지 않아 셀크기 및 공정단계를 감소시킨 이이피롬에 적합하도록 한 새로운 구조의 이이피롬소자와 이의 제조공정에 관한 것이다.The present invention relates to an electronically erasable programmable read only memory (EEPROM), which is a semiconductor memory device. It relates to a two pyrom device and a manufacturing process thereof.
종래의 이이피롬은 국부산화(Local Oxidation of Silicon;LOCOS) 공정에 의해 형성된 두꺼운 산화막이 성장되어 있고 대칭적으로 위치한 소오스(Source) 및 드레인(Drain)영역을 포함하여 구성된 반도체기판에서, 소오스와 드레인 간 채널영역에 대응하는 게이트산화막(gate oxide)과 드레인쪽의 산화막을 식각하여 형성시킨 터널산화막(Tunnel Oxide)상에 차례대로 형성된 플로팅게이트(floating gate),층간절연층,콘트롤게이트(control gate)로 구성되어 있다.Conventional ypyrom is a semiconductor substrate including a source and drain region in which a thick oxide film formed by a local oxidation of silicon (LOCOS) process is grown and symmetrically positioned, and a source and a drain are formed. A floating gate, an interlayer insulating layer, and a control gate sequentially formed on a tunnel oxide formed by etching a gate oxide and a drain oxide corresponding to an inter channel region. Consists of
제1도는 P형 반도체기판에 형성된 종래의 이이피롬셀(10)을 나타낸 것으로서, 제1도의 (a)는 종래의 이이피롬셀의 레이아웃(lay out)(10-1)도를 나타낸 것이고 제1도의 (b)는 제1도의 (a)도면의 I-1선 단면구조도이며, 도면을 참고로 이이피롬의 제조공정 및 동작을 개략적으로 설명하겠다.FIG. 1 shows a conventional Y. pyrom cell 10 formed on a P-type semiconductor substrate, and FIG. 1A shows a layout 10-1 of a conventional Y. pyrom cell. FIG. (B) is a cross-sectional view taken along the line I-1 of FIG. 1 (a), and a manufacturing process and operation of this pyrom will be briefly described with reference to the drawings.
종래의 이이피롬제조과정에서는 먼저 반도체기판(11)의 표면을 산화막을 성장시킨 후에 사진감광제(Photoresist)를 이용하여 게이트 형성영역을 정의한 다음, 사진식각공정(Photolithography Process)에 의하여 소오스영역 및 드레인영역의 매몰층이 형성될 곳(도면에 표시안함)을 개방(open)하여 고농도 N형불순물(n+)을 이온상태로 주입 및 확산시켜 n+매몰층(Buried n+Layer;Bn+)을 형성시킨다.In the conventional Y pyrom fabrication process, the oxide film is grown on the surface of the semiconductor substrate 11, and then a gate forming region is defined using a photoresist, and then a source region and a drain region are formed by a photolithography process. A buried layer of buried n + layer (Bn +) is formed by implanting and diffusing a high concentration N-type impurity (n +) in an ionic state by opening a place where a buried layer of (not shown) is formed.
물론 반도체기판(11)의 내부에서 소오스영역(12) 및 드래인영역(13)의 n+매몰층이 형성되는 동안에 기판표면에는 다시 산화막을 형성시키는데, 이 산화막은 인접한 트랜지스터 사이에 형성되는 기생트랜지스터의 동작을 방해하고 기판누설전류를 차단하기 위한 n+매몰산화막(Buried n+Oxide)(14)이며, 이 산화막은 소오스영역 및 드래인영역의 n+매몰층의 상단에서 선택적 열산화공정을 이용하여 LOCOS에 의해 형성되는 산화막과 같이 두텁게 형성된다.Of course, while the n + buried layers of the source region 12 and the drain region 13 are formed inside the semiconductor substrate 11, an oxide film is again formed on the surface of the substrate, which is formed by the parasitic transistors formed between adjacent transistors. the n + buried oxide film (buried n + oxide) (14 ) to obstruct the operation and block the substrate leakage current, the oxide film by using a selective thermal oxidation process at the top of the n + buried layer of the source region and the drain region It is formed thick like an oxide film formed by LOCOS.
그 후에, 소오스영역(12) 및 드레인영역(13)의 n+매몰산화막(14)사이의 반도체기판(11) 표면에는 소오스와 드레인 간 채널영역에 대응하는 게이트산화막(15)을 형성시킨다.Thereafter, a gate oxide film 15 corresponding to the source and drain channel region is formed on the surface of the semiconductor substrate 11 between the n + buried oxide film 14 of the source region 12 and the drain region 13.
그 후에 n+매몰산화막(14)의 소정 부분을 습식식각(wet etching)하여 드레인영역(13)을 노출시키는 터널창(16-1)을 형성한다. 드레인영역(13)의 터널창(16-1)에 의해 노출된 부분 상에 열산화방법에 의해 70Å 정도 두께의 터널산화막(16)을 형성시키며, 반도체기판(11) 상에서 게이트산화막(15) 및 n+매몰산화막(14)에 의해 기판과 절연되게 플로팅게이트(17)를 형성시키는 공정이 수행되고 최총적으로 콘트롤게이트(18)가 플로팅게이트(17)를 덮은 형태로 형성되며, 플로팅게이트(17)와 콘트롤게이트(18)의 사이에는 층간절연층(19)인 ONO (oxide/nitride/oxide)가 형성되어 콘트롤게이트와 플로팅게이트가 분리된 구조의 이이피롬셀이 제조된다.Thereafter, a predetermined portion of the n + buried oxide film 14 is wet etched to form the tunnel window 16-1 exposing the drain region 13. A tunnel oxide film 16 having a thickness of about 70 Å is formed on the portion exposed by the tunnel window 16-1 of the drain region 13 by a thermal oxidation method, and the gate oxide film 15 and the gate oxide film 15 are formed on the semiconductor substrate 11. A process of forming the floating gate 17 to be insulated from the substrate by the n + buried oxide film 14 is performed, and the control gate 18 is formed to cover the floating gate 17 at the maximum, and the floating gate 17 ) And an interlayer insulating layer 19 (ONO) (oxide / nitride / oxide) is formed between the control gate 18 and the control gate 18 to produce an ipyrom cell having a structure in which the control gate and the floating gate are separated.
종래의 이이피롬에 정보를 기록시킬 때에는 콘트롤게이트(18)에는 큰 전압을 가하고 드레인영역(13)과 반도체기판(11)에는 OV을 가하고, 소스영역(12)에는 OV 또는 플로팅(floating)상태로 두어 드레인영역내 n+매몰층의 전자가 터널산화막(16)을 통하여 플로팅게이트(17)에 충전되게 한다.When information is recorded in the conventional Y-pyrom, a large voltage is applied to the control gate 18, OV is applied to the drain region 13 and the semiconductor substrate 11, and OV or floating state is applied to the source region 12. The electrons of the n + buried layer in the drain region are charged to the floating gate 17 through the tunnel oxide film 16.
그 결과 충전된 전자에 의해 플로팅게이트(17)는 음(-)으로 대전되고 상대적으로 이이피롬셀의 문턱전압(Threshold Voltage)은 증가하여 정보는 기록된다.As a result, the floating gate 17 is negatively charged by the charged electrons, and the threshold voltage of the ypyrom cell is relatively increased so that the information is recorded.
반대로 정보를 소거시킬때에는 콘트롤게이트(18)와 반도체기판(11)에 큰 전압을 가하고 소오스영역(12)를 플로팅시킨 후 드레인영역(13)에 큰 전압을 가하여 플로팅게이트(17)에 충전되어 있는 전자를 방전시켜 수행된다.On the contrary, when the information is erased, a large voltage is applied to the control gate 18 and the semiconductor substrate 11, the source region 12 is floated, and a large voltage is applied to the drain region 13 to charge the floating gate 17. It is performed by discharging electrons.
종래의 이이피롬에서 두꺼운 n+매몰산화막(14)은 인접한 트랜지스터 사이에 형성되는 기갱트랜지스터의 동작을 방해하고 정보 소거시에 드레인영역(13)쪽에 인가되는 고전압에 의해 빈도체기판(11)으로 흐르게 되는 기판누설전류를 차단시키는 역할을 한다.In the conventional ypyrom, the thick n + buried oxide film 14 interferes with the operation of the microcavity transistors formed between adjacent transistors, and flows to the frequency substrate 11 by the high voltage applied to the drain region 13 at the time of erasing information. It serves to block the substrate leakage current.
그러나, n+매몰산화막은 이이피롬의 셀크기(cell size)를 증가시키는 문제점이 있었다.However, the n + buried oxide film has a problem of increasing the cell size of ypyrom.
또한, 터널창에 의해 노출된 부분을 산화하여 터널산화막을 형성시킬 때 게이트산화막도 같이 산화되므로 게이트산화막의 두께가 터널산화막의 두께에 따라 변하게 되는 문제점이 있다.In addition, since the gate oxide film is also oxidized when the tunnel oxide film is formed by oxidizing a portion exposed by the tunnel window, the thickness of the gate oxide film is changed according to the thickness of the tunnel oxide film.
따라서 본 발명의 목적은 이러한 문제를 개선하기 위하여, 제2도 및 제3도에서 도시한 바와 같이, 이이피롬제조시에 자기정렬 LDD(Self aligning Lightly Doped Drain)공정을 도입하여 소오스영역 및 드레인영역을 형성시키고, 터널산화막에 의한 게이트산화막의 산화를 방지하였으며, 플로팅게이트와 콘트롤게이트의 위치가 반전되고 n+매몰산화막의 역할을 콘트롤게이트가 대신하도록 하여 크기를 축소시킨 새로운 구조의 이이피롬과 이의 제조공정을 제공함에 있다.Accordingly, an object of the present invention is to introduce a self-aligning lightly doped drain (LDD) process in the manufacturing of EPyrom, as shown in FIGS. 2 and 3, to solve this problem. To prevent oxidation of the gate oxide film by the tunnel oxide film, and to reduce the size of the floating gate and the control gate by inverting the positions of the floating gate and the control gate so that the control gate replaces the role of the n + buried oxide film and its preparation. In providing a process.
본 발명에서 도입된 자기정렬 LDD공정에서는 건식식각(dry etching)에 의하여 반도체기판상의 다결정 실리콘게이트와 소오스영역 및 드레인영역의 표면산화막을 제거하는 과정에서 게이트의 양옆의 측면산화막(Sidewall oxide)은 식각시키지 않은 채로 남겨 놓는데, 이 측면산화막과 다결정 실리콘게이트를 경계면으로 하여 소오스영역과 드레인영역의 이온주입 공정을 자기정렬의 방법으로 수행하게 한다.In the self-aligned LDD process introduced in the present invention, sidewall oxides on both sides of the gate are etched in the process of removing the surface oxide film of the polycrystalline silicon gate, the source region and the drain region on the semiconductor substrate by dry etching. It is left unattended, and the ion implantation process of the source region and the drain region is performed by the self-aligning method with the side oxide film and the polycrystalline silicon gate as the interface.
본 발명에 따른 이이피롬소자의 제조방법은 이이피롬소자의 제조방법에 있어서, 반도체기판 상에 게이트산화막과 콘트롤게이트를 형성하는 공정과, 상기 콘트롤게이트 일측의 터널산화막이 형성될 부위에 상기 반도체기판과 반대 도전형의 저농도 분순물영역을 형성시키는 공정과, 상기 콘트롤게이트의 양측에 측면산화막을 형성시킨 공정과, 상기 콘트롤게이트가 형성된 반도체기판의 표면에 층간절연층을 형성시키는 공정과, 상기 저농도 불순물영역의 상기 층간절연층을 일부를 식각하여 터널산화막을 형성시키는 공정과, 상기 층간절연층과 터널산화막위에 상기 콘트롤게이트 및 반도체기판과 절연되고 상기 콘트롤게이트를 덮은 형태로 플로팅게이트를 형성하는 공정과, 상기 플로팅게이트를 마스크로 사용하여 상기 반도체기판의 상기 플로팅게이트의 양쪽에 상기 반도체기판과 반대 도전형의 소스 및 드레인영역을 형성하는 공정을 포함한다.In a method for manufacturing an y-pyrom device according to the present invention, a method of manufacturing an y-pyrom device includes: forming a gate oxide film and a control gate on a semiconductor substrate, and at the site where the tunnel oxide film on one side of the control gate is to be formed. Forming a low concentration contaminant region of a conductivity type opposite to that of the opposite type; forming a side oxide film on both sides of the control gate; forming an interlayer insulating layer on the surface of the semiconductor substrate on which the control gate is formed; Etching a portion of the interlayer insulating layer in the impurity region to form a tunnel oxide film, and forming a floating gate on the interlayer insulating layer and the tunnel oxide film, insulated from the control gate and the semiconductor substrate and covering the control gate. And the flow of the semiconductor substrate using the floating gate as a mask. On either side of the gate comprises the step of forming the semiconductor substrate and the source and drain regions of the opposite conductivity type.
또한 본 발명에 따른 이이피롬소자는 반도체 기판내에 반대도전형의 불순물이 고농도로 도핑되어 형성된 소스 및 드레인 영역과, 상기 드레인영역의 일측에 상기 반도체기판과 반대도전형의 불순물이 저농도로 도핑되어 형성된 저농도 불순물영역과, 상기 저농도 불순물영역의 상측 일부에 형성된 터널산화막과, 상기 소스 및 드레인 영역사이위에 절연막으로 절연되게 형성된 콘토롤게이트를 포함하여 구성되어서 플로팅게이트가 콘트로게이트 위에 위치하는 것이 특징인 이이다.In addition, the ypyrom device according to the present invention has a source and a drain region formed by doping a high concentration of anti-conductive impurities in a semiconductor substrate, and a low concentration doped with impurities of the anti-conductive type and a semiconductor substrate on one side of the drain region. And a low concentration impurity region, a tunnel oxide film formed on an upper portion of the low concentration impurity region, and a control gate formed to be insulated with an insulating film between the source and drain regions so that the floating gate is positioned on the control gate. This is it.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2도는 본 발명에 의한 이이피롬의 제조공정을 나타낸 것으로 도면을 참고로 본 이이피롬의 제조공정을 설명하면 다음과 같다.2 is a view showing a manufacturing process of ypyrom according to the present invention.
본 발명에서 제공하는 이이피롬셀을 제조하기 위해서 제2도의 (가)와 같이 준비된 P형 반도체기판(20)상에 산화막 및 다결정실리콘층을 순차적으로 성장시킨다. 그리고, 다결정실리콘층 상에 사진감광제를 도포한 후 산화막 및 다결정실리콘층을 사진식각방법으로 패터닝하여 게이트산화막(21-1) 및 콘트롤게이트(21)를 형성한다.An oxide film and a polysilicon layer are sequentially grown on the P-type semiconductor substrate 20 prepared as shown in FIG. After the photosensitive agent is coated on the polysilicon layer, the oxide film and the polysilicon layer are patterned by photolithography to form the gate oxide film 21-1 and the control gate 21.
그 후에, 게이트산화막(21-1)과 콘트롤게이트(21)가 형성된 반도체기판(20)의 표면에, 제2도의 (나)와 같이, 사진감광제(22)를 다시 도포한 후 노광 및 현상하여 터널산화막이 형성될 부분을 노출시킨다. 그리고, 사진감광제(22)를 마스크로 사용하여 반도체기판(20)의 노출된 부분에 N형 불순물(n-)을 이온상태로 저농도로 주입한다.Thereafter, the photosensitive agent 22 is again coated on the surface of the semiconductor substrate 20 on which the gate oxide film 21-1 and the control gate 21 are formed, and then exposed and developed. The portion where the tunnel oxide film is to be formed is exposed. Then, using the photosensitive agent 22 as a mask, the N-type impurity (n-) is implanted at a low concentration into an exposed portion of the semiconductor substrate 20.
그리고, 제2도의 (다)와 같이 반도체기판(20) 상에 잔류하는 사진감광제(22)를 제거하고 주입된 불순물을 활성화되도록 아닐링(Annealing)하여 반도체기판(20)에 n-영역(23)을 형성한다. 이 때, 이온 주입에 의해 반도체기판(20)의 결정구조를 원상태로 회복시킨다.Then, as shown in FIG. 2C, the photosensitive agent 22 remaining on the semiconductor substrate 20 is removed, and annealing is performed to activate the implanted impurities so that the n-region 23 is formed on the semiconductor substrate 20. ). At this time, the crystal structure of the semiconductor substrate 20 is restored to its original state by ion implantation.
그 후에 아닐링공정을 통하여 n-영역(23)을 형성시킨 반도체기판(20)의 표면에 산화막을 증착한 후 에치백하여 콘트롤게이트의 양측에 측면산화막(21-2)을 형성시킨다.Thereafter, an oxide film is deposited on the surface of the semiconductor substrate 20 on which the n-region 23 is formed through an annealing process and then etched back to form side oxide films 21-2 on both sides of the control gate.
이어서 제2도의 (라)와 같이, n-영역(23)과 콘트롤게이트(21) 및 측면산화막(21-2)을 포함한 반도체기판(20)의 표면에 ONO나 기타절연막으로 층간절연층(24)을 형성시킨 후에, n-영역(23) 상단의 층간절연층(24)을 사진식각공정에 통해 일부 또는 전부를 소정 두께를 이루도록 식각한 후 터널산화막(25)을 형성시킨다. 이 때 터널산화막(25)의 두께는 n-영역(23)의 전자가 터널산화막을 통하여 방전되거나 충전될 수 있을 만한 두께로 형성된다. 또한 층간절연층(24)이 형성될 때 플로팅게이트의 게이트산화막도 같이 형성된다.Subsequently, as shown in FIG. 2D, the interlayer insulating layer 24 is formed on the surface of the semiconductor substrate 20 including the n − region 23, the control gate 21, and the side oxide film 21-2 with ONO or another insulating film. ) Is formed, and then the tunnel oxide layer 25 is formed by etching the interlayer insulating layer 24 over the n − region 23 to have a predetermined thickness through a photolithography process. At this time, the thickness of the tunnel oxide film 25 is formed to a thickness such that electrons in the n − region 23 can be discharged or charged through the tunnel oxide film. When the interlayer insulating layer 24 is formed, the gate oxide film of the floating gate is also formed.
그리고 제2도의 (마)와 같이, 다결정실리콘을 증착한 후 사진식각공정으로 패터닝하여 플로팅게이트(26)을 형성하는데, 이 플로팅게이트(26)는 층간절연층(24)과 터널산화막(25)에 의하여 콘트롤게이트(21) 및 반도체기판(20)과 절연되고, 또 콘트롤게이트(21)를 덮은 형태로 형성된다.As shown in FIG. 2E, polycrystalline silicon is deposited and then patterned by photolithography to form a floating gate 26. The floating gate 26 includes an interlayer insulating layer 24 and a tunnel oxide film 25. It is formed to be insulated from the control gate 21 and the semiconductor substrate 20 and to cover the control gate 21.
그 다음에 제2도의 (바)와 같이, 다결정실리콘인 플로팅게이트(26)를 마스크로 사용하여, 플로팅게이트(26)의 양쪽에 고농도 n형불순물(n+)를 이온주입하여 소오스영역(27) 및 드레인영역(28)을 형성시키다.Next, as shown in FIG. 2B, using a floating gate 26 which is polycrystalline silicon as a mask, high concentration n-type impurities (n + ) are ion-implanted on both sides of the floating gate 26 to form a source region 27 ) And drain region 28 are formed.
즉 소오스영역(27) 및 드레인영역(28)을 형성시키기 위해 다결정실리콘인 플로팅게이트(26)를 마스크로 사용하여, 플로팅게이트(26)의 양쪽에 대칭적으로, 고농도 n형불순물(n+)를 이온상태로 반도체기판내에 주입시킨다.That is, using the floating gate 26, which is polycrystalline silicon, as a mask to form the source region 27 and the drain region 28, a high concentration n-type impurity (n + ) symmetrically on both sides of the floating gate 26. Is implanted into the semiconductor substrate in an ion state.
본 발명의 이이피롬셀의 제조공정에 의하면, 종래의 n+매몰산화막 형성단계가 생략되었고 플로팅게이트와 콘트롤게이트의 위치는 서로 반전되며 이피롬셀의 크기도 축소되게 된다.According to the manufacturing process of the ipyrom cell of the present invention, the conventional n + buried oxide film forming step is omitted, and the positions of the floating gate and the control gate are inverted from each other and the size of the ipyrom cell is also reduced.
제3도는 본 발명에 의한 이이피롬셀을 나타낸 도면으로, 제3도의 (가)는 본 발명의 이이피롬셀의 레이아웃도이고 제3도의 (나)는 제3도(가)의 II-II 선 단면구조도로서, 도면을 참고로 하여 본 이이피롬셀의 정보 기록 및 소거시의 동작을 설명하면 다음과 같다.FIG. 3 is a diagram showing an ipyrom cell according to the present invention. FIG. 3 (a) is a layout diagram of an ipyrom cell of the present invention, and FIG. 3 (b) is a II-II line of FIG. 3 (a). As a cross-sectional structure diagram, the operation at the time of information recording and erasing of this Y pyrom cell with reference to the drawings is as follows.
본 이이피롬셀(30)에 정보를 기억시킬때에는 제3도의 (가)도면의 활성영역(A )내에서 드레인영역(31)과 반도체기판(32)은 접지(ground)시키고 소오스영역(33)는 플로팅(floating)상태로 둔후, 콘트롤게이트(34)에 큰 전압을 가하여 터널산화막(35)을 통해 n-영역(36)의 전자가 플로팅게이트(37)에 충전되어 수행하게 되며, 정보를 소거시킬때에는 콘트롤게이트와 반도체기판 및 소오스영역을 모두 접지시킨 후에, 드레인영역에 큰 전압을 인가하여 플로팅게이트에 있는 전자가 터널산화막을 통해 방전되도록 하여 수행된다.When the information is stored in this EPI cell 30, the drain region 31 and the semiconductor substrate 32 are grounded in the active region A of FIG. 3A, and the source region 33 is stored. After the floating (floating) state is applied, a large voltage is applied to the control gate 34 to charge electrons in the n − region 36 through the tunnel oxide film 35 to the floating gate 37 to be performed, and erase the information. When the control gate, the semiconductor substrate and the source region are all grounded, a large voltage is applied to the drain region to discharge electrons in the floating gate through the tunnel oxide film.
본 발명에 의한 이이피롬은 기존구조에서 인접한 트랜지스터 사이에 형성되는 기생트랜지스터의 동작을 방해하고 정보 소거시에 드레인영역쪽에 인가되는 고전압에 의해 게이트산화막과 터널산화막사이에서 생성되는 기판누설전류를 차단하기위해 형성된 n+매몰산화막을 형성시키지 않고, n+매몰산화막의 역할을 콘트롤게이트가 대신하도록하여 셀크기를 감소시켰으며, 또한, 터널산화막 형성시 게이트산화막이 재산화되지 않도록 하여 이 게이트산화막이 두꺼워지는 것을 방지할 수 있는 잇점이 있다.The ypyrom according to the present invention prevents the parasitic transistors formed between adjacent transistors in the conventional structure and blocks the substrate leakage current generated between the gate oxide film and the tunnel oxide film due to the high voltage applied to the drain region when erasing information. without forming the n + buried oxide film, reduced the size of the cell so as to act as a n + buried oxide film instead of the control gate, also, the tunnel oxide film when the gate oxide film from being re-oxidized thicker the gate oxide film is formed for There is an advantage to prevent losing.
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| KR1019940015089A KR0147256B1 (en) | 1994-06-29 | 1994-06-29 | Ipyrom and Ipyrom Manufacturing Process |
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| KR1019940015089A KR0147256B1 (en) | 1994-06-29 | 1994-06-29 | Ipyrom and Ipyrom Manufacturing Process |
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