JPH05315623A - Nonvolatile semiconductor storage device - Google Patents

Abstract

(57) [Summary] [Object] The present invention provides a non-volatile semiconductor memory device capable of reducing the memory cell and reducing the source resistance. [Structure] Source diffusion layer 3 formed on semiconductor substrate 1
In a nonvolatile semiconductor memory device having a memory cell provided with a drain diffusion layer 2, a floating gate 6 and a control gate 7 which are insulated by a laminated structure, side walls of the floating gate and the control gate which are insulated by the laminated structure. The side wall insulating film 9 formed to face the side wall, the side wall insulating film formed to face the source diffusion layer, and the side wall insulating film formed to face the drain diffusion layer. A conductive film 11 is provided, and the conductive film 11 on the source diffusion layer is arranged in parallel with the source diffusion layer. The side wall insulating film 9 can secure a design margin with a certain distance to the floating gate and the control gate, and the conductive film 11 on the source diffusion layer suppresses the rise of the source resistance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device.

[0002]

^2. Description of the Related Art Conventional EPROM and flash E ² PR
A nonvolatile semiconductor memory device represented by OM mainly has a structure as shown in FIGS.
Various measures have been taken in order to reduce the size of memory cells with high integration. When the size of the memory cell of the EPROM is reduced, the gate length of the memory cell, the contact margin between the floating gate 26 and the drain diffusion layer 22 shown in FIG. 10, and the source width of the source diffusion layer 23 are regulated. There are three points. Of these, with respect to the gate length, the source diffusion layer 23 and the drain diffusion layer 22 provided on the semiconductor substrate 31 from around 1.0 μm.
The punch-through phenomenon between them becomes apparent and it becomes difficult to shorten the channel.

Therefore, various measures have recently been taken to reduce the remaining two factors. First, as shown in FIG. 10, the floating gate 26 and the drain diffusion layer 22 are
In order to increase the alignment margin, a silicide pad 35 which is a conductive film is provided. As a result, a short circuit between the floating gate 26 and the bit line 33 does not occur unless at least the drain contact extends over the silicide pad 35. Therefore,
Conventionally, the required alignment margin may be provided between the drain contact and the silicide pad 35, and as a result, the design margin between the floating gate 26 and the drain contact can be made smaller than before.

Further, as to the source width, which is becoming smaller as the memory cell size is further reduced, in order to prevent the source resistance from increasing as a result, as shown in FIG. 11, silicide is formed in parallel on the source diffusion layer 23. A layer 35a is provided, and as shown in FIG. 12, a strap region is provided for every several bits to make a contact 39 with the source diffusion layer 23. In FIGS. 10 and 11, reference numeral 30 is an interlayer insulating film, and 34, 37 and 38 are insulating films. Further, FIG. 11 is a sectional view taken along line XX of FIG.

[0005]

However, even in the case of the conventional structure as described above, there is a limit in reducing the size of the memory cell. For example, even if the silicide pad 35 is provided, this time, the design margin between the contact between the silicide pad 35 and the drain diffusion layer 32 and the floating gate 26 and the control gate 27 (distance indicated by x in FIG. 10). Must allow for at least the alignment margin.

Further, even if the silicide layer 35a is provided to prevent an increase in the source resistance, an extra strap region for making contact with the source diffusion layer 23 must be provided, which prevents the memory cell from being reduced in size. There was a point.

The present invention has been made under the above circumstances, and provides a nonvolatile semiconductor memory device capable of improving the structure, reducing the size of a memory cell, and reducing the source resistance. The purpose is to

[0008]

The present invention for achieving the above object comprises a source diffusion layer and a drain diffusion layer formed on a semiconductor substrate, and a floating gate and a control gate insulated by a laminated structure. In a non-volatile semiconductor memory device having a memory cell including: a sidewall insulating film formed to face sidewalls of a floating gate and a control gate insulated by the laminated structure; and a source diffusion layer formed to face the source diffusion layer. And a conductive film formed by directly covering the drain diffusion layer and the side wall insulating film formed opposite to the drain diffusion layer, and the conductive film on the source diffusion layer is parallel to the source diffusion layer. It is characterized by being placed in.

[0009]

According to the nonvolatile semiconductor memory device having the above-described structure, the floating gate and the control gate are insulated from each other by the sidewall insulating film formed opposite to the sidewalls of the floating gate and the control gate, which are insulated by the laminated structure. A contact on the drain diffusion layer and a contact on the source diffusion layer having a space of 1 are determined. Further, the side wall insulating film formed on the side wall portion electrically insulates the floating gate and the control gate from the conductive film on the drain diffusion layer and the source diffusion layer. Furthermore, the conductive film on the drain diffusion layer can secure the same alignment margin for the subsequent bit contact as the conventional purpose, while the conductive film on the source diffusion layer can be contacted at any position on the source diffusion layer. Because you can
The strap region can be eliminated and the size of the memory cell can be reduced without impairing the function of suppressing the rise in the source resistance.

[0010]

EXAMPLES Next, examples of the present invention will be described in detail. EP, which is the nonvolatile semiconductor memory device in the first embodiment of the present invention
It is sectional drawing of ROM. The nonvolatile semiconductor memory device shown in FIG. 1 includes a source diffusion layer 3 and a drain diffusion layer 2 formed on a semiconductor substrate 1, and a first insulating film 4 and a second insulating film 5 having a stacked structure on the semiconductor substrate 1. It comprises an insulated floating gate 6 and a control gate 7. A sidewall insulating film 9 is formed on the sidewalls of the floating gate 6, the control gate 7, the first insulating film 4, and the second insulating film 5.

The side wall insulating films 9 and 9 formed to face the source diffusion layer 3 and the side wall insulating films 9 and 9 formed to face the drain diffusion layer 2 are directly coated with a conductive film 11. .. The conductive film 11 on the source diffusion layer 3 is arranged in parallel with the source diffusion layer 3. In FIG. 1, 8 is a cap insulating film, 10 is an interlayer insulating film, and 13 is a bit line (aluminum wiring).

Next, a manufacturing process of the above-mentioned semiconductor memory device will be described with reference to FIGS. First, on the conductive type semiconductor substrate 1, the first insulating film 4, the floating gate 6,
The second insulating film 5, the control gate 7, and the cap insulating film 8 are sequentially formed in a self-aligning manner, and the cell gate electrode 20 is patterned. Then, conductive impurities are added to the cell gate electrode 20 in a self-alignment manner, for example, 50 to Ion implantation is performed under the conditions of 70 keV and a dose amount of 1 to 5 × 10 ¹⁵ cm ^-2.
By performing heat treatment under the temperature condition of 00 to 900 ° C., the drain diffusion layer 2 and the source diffusion layer 3 are respectively formed as shown in FIG.

Next, 300 to 500 nm is formed by the CVD method.
After forming a film of the same material as that of the cap insulating film 8 with the film thickness of 3, the side wall insulating film 9 is formed on the side wall portion of the cell gate electrode 20 by etching back by the RIE method as shown in FIG.

Next, a conductive material is deposited by a sputtering method and patterned to form a conductive film 11 for covering the source diffusion layer 3, the drain diffusion layer 2 and each side wall insulating film 9, as shown in FIG. Form.

Further, as shown in FIG. 5, drain diffusion
The opening is formed only above the contact portion between the layer 2 and the conductive film 11.
The photoresist film 10 is formed, and the photoresist film 10 is formed.
As a mask, 50 to 70 k of conductive impurities are provided above the contact portion.
eV, dose 1-3 x 10 ¹⁵cm^-2Ion injection under the conditions
To enter. This is to reduce the contact resistance.

Next, as shown in FIG. 6, the drain diffusion layer 2
After forming a plug 12 made of a polycrystalline silicon layer doped with conductive impurities on the upper conductive film 11, a bit line 13 is patterned.

Through the above steps, the nonvolatile semiconductor memory device shown in FIG. 1 can be manufactured.

Next, another embodiment of the present invention will be described with reference to FIGS.
Will be described. 7 to 9 are sectional views of an E ² PROM which is a nonvolatile semiconductor memory device according to the second embodiment of the present invention. First, as shown in FIG. 7, the cell gate electrode 20 is formed on the semiconductor substrate 1 as in the case shown in FIG. 2, and then the source diffusion layer 3 is formed by the photoresist film 14.
Mask other areas except.

Next, conductive impurities are added to the accelerating voltage of 40 to 70.
Ion implantation is performed under conditions of keV and a dose amount of 1 to 5 × 10 ¹⁴ cm ⁻² , and heat treatment is performed at a temperature of 200 to 900 ° C. to form the low concentration source diffusion layer 3 a.

Further, as shown in FIG. 8, this time, the region other than the drain diffusion layer 2 is masked with the photoresist film 14, and the conductive type impurities are accelerated at a voltage of 50 to 70 kev and the dose is 3 to 5 × 10 ¹⁵ cm. Ion implantation is performed under the condition of ^-2 to form the low concentration drain diffusion layer 2a.

Thereafter, in the same manner as described above, after forming the sidewall insulating film 9 and again masking with the photoresist film 14a so as to open only the source diffusion layer 3a portion, conductive impurities are removed. Ion implantation is performed under the conditions of 30 to 50 keV and a dose amount of 3 to 5 × 10 ¹⁵ cm ⁻² to form a high concentration source diffusion layer 3b. As a result, the high-concentration source diffusion layer 3b and the low-concentration drain diffusion layer 2a in the flash E ² PROM can be formed. After that, the flash E ² PROM can be manufactured by performing the same steps as in the case of the EPROM described above.

The present invention is not limited to the above-mentioned embodiments, but various modifications can be made within the scope of the invention.

[0023]

According to the present invention described above, with the above-described structure, the conductive film on the drain diffusion layer can be provided in a self-aligned manner with no alignment margin for the floating gate. In addition, since the conductive film can be simultaneously formed on the source diffusion layer by using the same material as that of the conductive film to reduce the source resistance, a strap region is not required, and thus a nonvolatile memory cell can be realized. A semiconductor memory device can be provided.

[Brief description of drawings]

FIG. 1 is a sectional view of an EPROM which is a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of the EPROM according to the first embodiment.

FIG. 3 is a cross-sectional view showing a manufacturing process of the EPROM according to the first embodiment.

FIG. 4 is a sectional view showing a manufacturing process of the EPROM according to the first embodiment.

FIG. 5 is a cross-sectional view showing a manufacturing process of the EPROM according to the first embodiment.

FIG. 6 is a cross-sectional view showing a manufacturing process of the EPROM according to the first embodiment.

FIG. 7 is a sectional view of an E ² PROM which is a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 8 is a cross-sectional view showing the manufacturing process of the E ² PROM which is the second embodiment.

FIG. 9 is a cross-sectional view showing the manufacturing process of the E ² PROM which is the second embodiment.

FIG. 10 is a sectional view showing a conventional EPROM.

FIG. 11 is a cross-sectional view showing another example of a conventional EPROM.

FIG. 12 is a plan view of the conventional EPROM shown in FIG.

[Explanation of symbols]

 1 semiconductor substrate 2 drain diffusion layer 3 source diffusion layer 6 floating gate 7 control gate 9 sidewall insulating film 11 conductive film

Claims (1)

[Claims] 1. A non-volatile semiconductor memory device having a memory cell having a source diffusion layer and a drain diffusion layer formed on a semiconductor substrate, and a floating gate and a control gate insulated by a laminated structure. A side wall insulating film formed to face the side walls of the floating gate and the control gate insulated from each other, a side wall insulating film formed to face the source diffusion layer, and a drain insulating layer to face the drain diffusion layer. A nonvolatile semiconductor memory device, comprising: a side wall insulating film formed and a conductive film directly covering the conductive film, and the conductive film on the source diffusion layer is arranged in parallel with the source diffusion layer.