JPH0737997A - Memory cell of static ram and its manufacture - Google Patents

Abstract

PURPOSE:To reduce the area of a memory cell and at the same time improve reliability by laying out first and second word lines so that they nearly cross first and second active regions and they correspond to each on one part of the gate electrodes of first and second driver transistors CONSTITUTION:Two first and second active regions 3 and 4 are formed in parallel to a semiconductor substrate 2 within a memory cell 1 of SRAM. A first driver transistor 7 is formed at the first active region 3 at one side in diagonal direction of the memory cell 1. Then, a second driver transistor 8 is formed at a second active region 4 at the opposite side in diagonal direction. A first word line 17 is formed in a state so that it nearly cross the first and second active regions 3 and 4 or a second word line 18 is formed on one part of a second crate electrode 14 and in a state so that it nearly crosses the first and second active regions 3 and 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static RAM memory cell.

[0002]

2. Description of the Related Art In a static RAM (hereinafter referred to as SRAM) having a memory capacity of 256 kilobits or more and 4 megabits or less, two driver transistors are arranged on one side of one word line forming a word transistor. . However, in SRAMs having a memory capacity of 16 megabits or more, memory cells using a thin film transistor (TFT) as a load are mainstream, and a pattern suitable for this is required.

Therefore, a CMOS type static RAM (hereinafter referred to as SRAM) having a pattern structure as shown in FIG.
Memory cell) is proposed. In the figure, as an example, a so-called split word line type SRAM memory cell 102 is shown. The illustration of the load element of the SRAM and various insulating films (for example, insulating film for element isolation, gate insulating film, interlayer insulating film, etc.) are omitted.

As shown in the figure, in a memory cell 102 of a semiconductor substrate 101, a substantially L-shaped active region 103 is formed.
An element isolation region 105 is formed so as to surround a side portion of the active region 104 having a substantially inverted L shape.

A word line 111 that crosses the active area 103 in the left-right direction of the drawing and the active area 1
The word lines 112 that cross 04 in the left-right direction in the drawing are arranged substantially in parallel. Each word line 111, 11
A driver transistor 107 using the active region 103 as a source / drain region and a driver transistor 108 using the active region 104 as a source / drain region are provided between the two.

The driver transistors 107 and 108
Of the gate electrodes 113, 114 of the word line 111,
They are provided so as to be substantially perpendicular to 112 and to be substantially parallel to each other. Moreover, the gate electrode 113
The contact formation portion 115 formed by extending the above is connected to the active region 104. In addition, the gate electrode 11
The contact forming portion 116 formed by extending 4 is connected to the active region 103.

A node contact 117 is provided in the contact forming portion 115, and a node contact 118 is provided in the contact forming portion 116.

Further, in the active region 103 on the node contact 118 side with respect to the gate electrode 113,
The drain region 119 of each driver transistor 107 is provided. The drain region 119 also serves as the active region of the word transistor 109. A source region 120 is provided in the active region 103 on the side opposite to the drain region 119 with respect to the gate electrode 113. A Vss contact 121 is provided on the source region 120.

On the other hand, the drain region 122 of each driver transistor 108 is provided in the active region 104 on the node contact 117 side with respect to the gate electrode 114. The drain region 122 also serves as the active region of the word transistor 110. Further, a source region 123 is provided in the active region 104 on the side opposite to the drain region 122 with respect to the gate electrode 114. Vss contact 1 on the source region 123
24 are provided.

Bit contacts 125 and 126 connected to the word lines 111 and 112 are provided on the active regions 103 and 104 on the opposite side of the driver transistors 107 and 108, respectively. .

A memory cell structure has also been proposed in which the memory cells are formed in a horizontally long shape and a sufficient bit line interval is secured. An example thereof will be described with reference to the layout diagram of FIG. In the figure, as an example, a so-called split word line type static RAM (hereinafter referred to as SRAM) is used.
The memory cell 202 is shown. The illustration of the load element of the SRAM and various insulating films (for example, insulating film for element isolation, gate insulating film, interlayer insulating film, etc.) are omitted.

As shown in the figure, in the memory cell 202 of the semiconductor substrate 201, a substantially S-shaped active region 203 is formed.
The element isolation region 204 is formed so as to surround the side portion (the region indicated by the dashed diagonal lines).

In the drawing, two word lines 211 and 212 (areas indicated by solid diagonal lines) are arranged substantially parallel to each other so as to traverse the active area 203 in the left-right direction. Between the word lines 211 and 212, driver transistors 205 and 206 using the active region 203 as the source and drain regions are provided.

The driver transistors 205 and 206
Of the gate electrodes 213, 214 of the word line 211,
For example, they are provided in a state of being inclined at about 45 ° with respect to 212 and in a state of being substantially parallel to each other. Moreover, the contact forming portion 215 formed by extending the gate electrode 213.
Are formed to overlap on the word line 211. The contact formation portion 216 formed by extending the gate electrode 214 is formed so as to overlap the word line 212.

A gate contact 217 is provided in the contact forming portion 215, and a gate contact 218 is provided in the contact forming portion 216.

Further, each of the gate electrodes 213 and 214
A source region 219 including the active region 203 of each driver transistor 205, 206 is provided between them. Vss contact 2 is formed on the source region 219.
20 are provided.

Between the word lines 211 and 212,
The drain region 221 of the driver transistor 205 is provided on the opposite side of the gate electrode 213 from the Vss contact 220. This drain region 2
Reference numeral 21 includes the active region 203, which also serves as the active region of the word transistor 207. A node contact 222 connected to the drain region 221 is provided on the drain region 221.

Similarly, between the word lines 211 and 212,
A drain region 223 of the driver transistor 206 is provided on the opposite side of the gate electrode 214 from the Vss contact 220. This drain region 2
Reference numeral 23 includes the active region 203, which also serves as the active region of the word transistor 208. A node contact 224 connected to the drain region 223 is provided on the drain region 223.

Bit contacts 225 and 226 connected to the word lines 211 and 212 are provided on the active region 203 on the side opposite to the driver transistors 205 and 206 side.

[0020]

However, in the SRAM memory cell described above with reference to FIG.
The memory cell has a rectangular shape that is long in the vertical direction. The bit line is arranged in the longitudinal direction of the memory cell. Therefore, when attempting to arrange a bit line in a memory cell, the bit line width and the bit line interval must be narrowed to form the bit line. Therefore, the reliability of the SRAM as a whole is lowered due to stress migration and electromigration of the chip. In addition, the area of the memory cell is increased, which prevents the chip size from being reduced.

Further, since the word lines that should originally be driven in the same phase are formed by being divided into two, if the line width of the word lines is not formed uniformly due to manufacturing factors, the signal It causes a phase difference in transmission. Therefore, SR
It interferes with AM drive.

Further, the SR having the above-mentioned structure and described with reference to FIG.
The AM memory cell has a structure in which the contact formation portion formed by extending the gate electrode of the driver transistor overlaps the word line. Therefore, the gate electrode of the driver transistor is formed after forming the word line and then performing gate oxidation. Will be formed. Usually, since the word line is used as a wiring, it has a refractory metal layer having a low wiring resistance or a compound layer containing a refractory metal such as silicide or polycide. Therefore, when gate oxidation is performed, heavy metal is out-diffused from the refractory metal layer or the compound layer containing refractory metal such as silicide or polycide, and the active region or the like is contaminated with the heavy metal.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a static RAM memory cell having a reduced area and improved reliability.

[0024]

SUMMARY OF THE INVENTION The present invention is an SRAM memory cell made to achieve the above object. That is, a static RAM memory cell in which two word lines are arranged in parallel in one memory cell,
A first active region and a second active region on the semiconductor substrate in the memory cell;
The active region is formed substantially parallel to the active region. A first driver transistor is formed in a first active region on one side of the memory cell in the diagonal direction, and a second driver transistor is formed in a second active region on the other side of the diagonal direction. . Moreover, each 1st, 2nd
First and second word lines are arranged in a state substantially orthogonal to the active region and corresponding to at least a part of the gate electrodes of the first and second driver transistors, respectively.

Further, the gate electrodes of the first and second driver transistors and the first and second word lines are arranged substantially in parallel.

Further, first and second node contacts are arranged corresponding to substantially the respective central portions of the first and second active regions between the first and second word lines, and the first driver is further provided. A first connecting portion formed by extending the gate electrode of the transistor is connected to the second node contact, and a second connecting portion formed by extending the gate electrode of the second driver transistor is connected to the first node contact.

For one point in the center of the memory cell,
At least one or both of the gate electrodes of the first and second driver transistors or the first and second word lines are arranged point-symmetrically.

The first and second word lines are connected at least in a memory cell array region having a plurality of the memory cells.

As a method of manufacturing the memory cell of the SRAM, in the first step, first and second active regions are provided substantially parallel to each other on the semiconductor substrate, and then the first and second active regions are formed on the respective first and second active regions. A second gate insulating film is formed corresponding to each of them, and then a cap insulating film is provided on the upper layer.
The gate electrode of the second driver transistor is formed across the first and second active regions, and the first and second connection portions connected to the respective gate electrodes are formed on the second and first active regions on the other side. It is formed so as to reach the formation region of the node contact. Then in the second step,
First sidewalls are formed on the sidewalls of the gate electrodes of the first and second driver transistors. Then, in a third step, first and second word lines having a cap insulating film as an upper layer are formed so as to at least partially overlap the gate electrodes of the first and second driver transistors. Further, in the fourth step, second sidewalls are formed on the sidewalls of the first and second word lines.
Form sidewalls. Then, in a fifth step, an insulating film is formed so as to cover the first and second word lines. Then, in a sixth step, after forming an etching mask on the insulating film and forming an opening in the etching mask on each node contact region, the first and second active regions below the opening are exposed by etching. Then, the first and second node contacts exposing the first and second connection portions are formed on the side wall side.

Alternatively, after forming the node contact, the first node contact is formed by extending the gate electrode of the first thin film transistor (hereinafter referred to as the first TFT) forming the load element of the SRAM or the gate electrode. In addition to connecting one pattern, the second node contact is connected to a gate electrode of a second thin film transistor (hereinafter referred to as a second TFT) forming a load element of the SRAM or a second pattern formed by extending the gate electrode.

[0031]

In the memory cell of the SRAM, the first and second word lines are arranged corresponding to at least a part of the gate electrodes of the first and second driver transistors, respectively. At least the memory cell area is reduced by the amount of stacking the second word lines. Furthermore, the first and second active regions are formed substantially parallel to each other on the semiconductor substrate in the memory cell, and the first and second word lines are arranged so as to be substantially orthogonal to the first and second active regions. Therefore, when the bit line is formed, the bit line is arranged with sufficient space.

In the above memory cell, the gate electrodes of the first and second driver transistors and the first and second word lines are arranged substantially parallel to each other, so that the first and second transistors are inevitably formed. The active region and each of the first and second word lines are arranged so as to be orthogonal to each other. As a result, for example, in the first active region, the source region of the first driver transistor, its channel region, the drain region of the first driver transistor that also serves as the source / drain region of the second word transistor, the channel region of the word transistor,
The source / drain regions are sequentially arranged. A Vss contact is provided on the source region of the first driver transistor. A first node contact is provided on the drain region of the first driver transistor.
Further, a first bit contact is provided on the source / drain region of the second word transistor. In this way, the first active area is used without waste. The second active area is also used without waste in the same manner as above. Therefore, the memory cell is reduced in size.

Further, the second connection portion formed by extending the gate electrode of the second driver transistor is connected to the first node contact, and the first connection portion formed by extending the gate electrode of the first driver transistor is formed as the second connection portion. By connecting to the node contacts, the layout structure is simplified.

Further, the gate electrode of each driver transistor or at least one or both of the first and second word lines are arranged symmetrically with respect to the central portion of the memory cell, so that the memory cell can be designed. It will be easier.

Since the first and second word lines are connected at least in the memory cell array region including a plurality of the memory cells, signals transmitted by the word lines are transmitted in the same phase.

In the method of manufacturing the memory cell of the static RAM, the first and second word lines are formed after forming the gate electrodes of the first and second driver transistors. Does not cause heavy metal contamination even if it is formed of a material having a refractory metal layer or a compound layer containing a refractory metal such as silicide or polycide. Therefore, the gate electrodes of the first and second driver transistors can be formed of single-layer polysilicon.

Further, after forming the gate electrodes of the first and second driver transistors with the cap insulating film provided in the upper layer, the first sidewalls are formed on their side walls, and the cap insulating film is provided in the upper layer. After forming the first and second word lines, the second sidewalls are formed on their side walls. Then, after forming an insulating film so as to cover the first and second word lines, etching is performed to remove the insulating film, the gate insulating film, and the gate electrodes of the first and second driver transistors in the region where the node contact is formed. Thereby, the first and second node contacts are formed in a self-aligned manner. Moreover, the gate electrodes of the first and second driver transistors are exposed on their sidewalls.

Further, after forming the first and second node contacts, the first (second) node forming the load element of the static RAM is formed on the first (second) node contact.
By connecting the gate electrode of the TFT or the first (second) pattern formed by extending the gate electrode, the first
(Second) Drain region of driver transistor and second
The first region is formed on the drain region of the (first) word transistor and the gate electrode of the second (first) driver transistor.
(Second) The gate electrode of the TFT is connected.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the layout diagram of FIG. In the figure, so-called split word line type S
1 shows a memory cell 1 of RAM. It should be noted that the illustration of the load elements of the SRAM and various insulating films (for example, insulating films for element isolation, gate insulating films, etc.) are omitted in the figure.

That is, as shown in FIG.
The semiconductor substrate 2 in the memory cell 1 is provided with two first and second active regions 3 and 4 which are parallel to each other in the vertical direction of the drawing, and the first and second active regions 3 are also provided. , 4 are formed so as to surround the sides of the element isolation regions 5.

A first driver transistor 7 is provided in the first active region 3 on one diagonal side of the memory cell 1 of the SRAM. The first driver transistor 7 has a first gate electrode 11 formed so as to cross the first active region 3.
A source region 12 is formed in the active region 3 on one side of the first gate electrode 11, and a drain region 13 is formed in the active region 3 on the other side.

A second driver transistor 8 is provided in the second active region 4 on the other side of the memory cell 1 of the SRAM in the diagonal direction. This second
The driver transistor 8 includes the second active region 4
It has the 2nd gate electrode 14 formed in the state of traversing. A source region 15 is formed in the active region 4 on one side of the second gate electrode 14, and a drain region 16 is formed in the active region 4 on the other side. Further, Vss contacts 71 and 72 are arranged in the source regions 12 and 15.

Further, on at least a part of the first gate electrode 11 and the first and second active regions 3, 4
The first word line 17 is arranged in a state substantially orthogonal to and. A second word line 18 is arranged on at least a part of the second gate electrode 14 and in a state substantially orthogonal to the first and second active regions 3 and 4.

The portion of the first word line 17 that crosses the second active region 4 becomes the gate electrode (hereinafter referred to as the first word electrode) 19 of the first word transistor 9. Source / drain regions 20 and 21 are formed in the second active region 4 on both sides of the first word electrode 19. Further, the portion of the second word line 18 that crosses the first active region 3 becomes the gate electrode (hereinafter referred to as the second word electrode) 22 of the second word transistor 10. Source / drain regions 23 and 24 are formed in the first active region 3 on both sides of the second word electrode 22. The drain region 13 and the source / drain regions 24 are formed of the same diffusion layer, for example.
The drain region 16 and the source / drain region 21 are formed of, for example, the same diffusion layer. Also,
Bit contacts 73 and 74 are provided on the source / drain regions 20 and 23.

Furthermore, each of the first and second word lines 17, 18
A first node contact 25 is arranged substantially above the central portion of the first active region 3 between them. Further, the second node contact 2 is formed on the substantially central portion of the second active region 4 between the first and second word lines 17 and 18.
6 are provided.

Further, the first gate electrode 11 is formed with a first connecting portion 27 which is an extension of the first gate electrode 11 and is connected to the second node contact 26. Further, the second gate electrode 14 is formed with a second connection portion 28 which is an extension of the second gate electrode 14 and is connected to the first node contact 25.

As described above, the SRAM memory cell 1 is laid out.

In the memory cell 1 of the SRAM, the first word line 17 is arranged so as to be laminated on at least a part of the first gate electrode 11 of the first driver transistor 7, so that the memory cell 1 of the SRAM is formed. Area is reduced. Similarly, the second word line 18 is also arranged to be laminated on at least a part of the second gate electrode 14 of the second driver transistor 8, so that SR
The area of the AM memory cell 1 is reduced. Further SRA
The first and second active regions 3 and 4 are formed substantially parallel to the semiconductor substrate 2 in the M memory cell 1, and the first and second word lines 17 and 18 are arranged in a state substantially orthogonal to them. Due to the provision, the SRAM memory cell 1 is formed horizontally long. Therefore, the bit lines (not shown) connected to the bit contacts 73 and 74 are arranged with a sufficient space.

In the SRAM memory cell 1, the first and second gate electrodes 11 and 14 and the first and second gate electrodes are formed.
Since the word lines 17 and 18 are arranged substantially parallel to each other, the first and second active regions 3 and 4 and the first and second word lines 17 and 18 are inevitably arranged so as to be orthogonal to each other. Set up. Therefore, for example, in the first active region 3, the first driver transistor 7 is arranged on one side, the second word transistor 10 is arranged on the other side, and the first node contact 25 is arranged in the middle thereof. It In the second active region 4, the second driver transistor 8 is arranged on one side, the first word transistor 9 is arranged on the other side, and the second node contact 26 is arranged in the middle thereof. Thus, each of the first and second active areas 3,
4 is used without waste, so SRAM memory cell 1
Is reduced.

Furthermore, the second connection portion 28 formed by extending the second gate electrode 14 is connected to the first node contact 25, and the first connection portion 27 formed by extending the first gate electrode 11.
Is connected to the second node contact 26, the layout structure is simplified.

As described above with reference to FIG. 1, the first and second driver transistors 3 and 4 of the first and second driver transistors 3 and 4 are defined with the central portion (for example, the point O) of the SRAM memory cell 1 as a point symmetry point. At least one or both of the gate electrodes 11 and 14 or the first and second word lines 17 and 18 are preferably arranged point-symmetrically. Like this
Second gate electrodes 11, 14 or first and second word lines 1
Arranging 7, 18 facilitates the design of the SRAM memory cell 1. In particular, when designing as a memory cell array, the design time is greatly shortened.

Further, with respect to the central portion (point O) of the memory cell, each of the first and second gate electrodes 11 and 14 or the first and second gate electrodes is formed.
By arranging at least one or both of the second word lines 17 and 18 in point symmetry, the design of the memory cell 1 of the SRAM becomes easy.

Further, as shown in FIG. 2, the first and second word lines 17 and 18 are connected at least in a region of a memory cell array 6 in which a plurality of memory cells 1 of the SRAM are provided.

For example, as shown in the layout diagram of FIG. 3, the first and second word lines 17 and 18 are provided with openings 29 and 30 which open above the first and second node contacts 25 and 26, respectively. It is connected.

Since the first and second word lines 17 and 18 are connected at least in the area of the memory cell array 6 having a plurality of SRAM memory cells 1, the first and second word lines 17 and 18 are connected. , 18 are transmitted in the same phase. Therefore, no signal delay occurs.

Next, a method of manufacturing the memory cell 1 of the SRAM having the word lines described in FIG. 3 will be described with reference to the manufacturing process diagrams (1), (2), (of FIGS. 4, 5 and 6). Part 3) will be described. Incidentally. The same components as those described in FIG. 1 above are designated by the same reference numerals as those shown in FIG.

As shown in FIG. 4A, first, the first step is performed. In this step, the semiconductor substrate 2 is formed by, for example, the LOCOS method as a usual method for forming the element isolation region.
The element isolation region 5 is formed in a state where the first and second active regions 3 and 4 are arranged substantially parallel to each other.

After that, the first and second gate insulating films 31 and 32 are formed on the upper surface of the semiconductor substrate 2 in the first and second active regions 3 and 4, for example, by a thermal oxidation method. Then, the electrode forming film 33 for forming the gate electrode of the driver transistor is formed by, for example, the CVD method. The electrode forming film 33 is made of, for example, polycrystalline silicon and has a film thickness of, for example, about 30 nm.
Furthermore, the electrode forming film 33 is formed by, for example, a CVD method.
A cap insulating film 34 is formed on the upper surface of the. The cap insulating film 34 is made of, for example, silicon oxide, and is formed to have a film thickness of, for example, about 100 nm capable of ensuring a withstand voltage.

Thereafter, the cap insulating film 34 and the electrode forming film 33 are patterned by the usual photolithography technique and etching. Then, as shown in (2) of FIG. 4, the first gate electrode 11 of the first driver transistor 7 is made to cross the first active region 3.
And a first connection portion 27 connected to the first gate electrode 11 and reaching the formation region 52 of the second node contact on the second active region 4 on the other side. At the same time, the second active area 4 is crossed to the second
The second gate electrode 14 of the driver transistor 8 is formed, and the second connection portion 28 connected to the second gate electrode 14 and reaching the formation region 51 of the first node contact on the other side of the first active region 3 is formed. Form. After that, low-concentration diffusion layers (not shown) of the first and second driver transistors 7 and 8 are formed by a normal ion implantation method.

Then, the second step shown in FIG. 4C is performed. In this step, the first sidewalls 35 and 36 are formed on the sidewalls of the first and second gate electrodes 11 and 14 by a normal sidewall formation technique by forming a silicon oxide film and etching back. By the etching back at this time, the gate insulating films (31) and (32) not covered with the first and second gate electrodes 11 and 14 and the like are etched and removed. After that, a high concentration diffusion layer (not shown) of the first and second driver transistors 7 and 8 is formed by a normal ion implantation method.

Subsequently, the third step shown in FIG. 5D is performed. In this step, gate insulating films (not shown) and 38 are formed on the first and second active regions 3 and 4, for example, by a thermal oxidation method. Then, the word linear film formation 39 for forming the first and second word lines is formed by, for example, the CVD method. The word linear film 39 is made of polycide, for example, and has a film thickness of, for example, about 100 nm. Further, a cap insulating film 40 is formed on the upper surface of the word linear film formation 39 by, for example, the CVD method. The cap insulating film 40 is made of, for example, silicon oxide and has a film thickness of, for example, about 100 nm to 150 nm. Then, the cap insulating film 40 and the word linear film 39 are patterned by the usual photolithography technique and etching.

Then, as shown in FIG. 5 (5), the first gate electrode 11 is at least partially overlapped with the first gate electrode 11 and the first and second active regions 3 and 4 are crossed. The word line 17 is formed. At the same time, the second word line 18 is formed so as to cross at least a part of the second gate electrode 14 and cross the first and second active regions 3 and 4. Usually, the first and second word lines 17 and 18 are integrally formed. After that, low-concentration diffusion layers (not shown) of the first and second word transistors 9 and 10 are formed by a normal ion implantation method.

Further, a fourth step shown in FIG. 5 (6) is performed. In this step, the second sidewalls 41 and 42 are formed on the sidewalls of the first and second word lines 17 and 18 by a normal sidewall formation technique by forming a silicon oxide film and etching back. By the etching back at this time, the gate insulating films (37), (38) formed on the first and second active regions 3, 4 which are not covered with the first and second word lines 17, 18 and the like. Is also removed. After that, by the usual ion implantation method, the first and second
A high-concentration diffusion layer (not shown) of the word transistors 9 and 10 is formed.

Then, the fifth step shown in FIG. 6 (7) is performed. In this step, an insulating film 43 made of, for example, silicon oxide is formed by a normal CVD method so as to cover the entire surfaces of the first and second word lines 17, (18).

Thereafter, the sixth step shown in FIG. 6 (8) is performed. In this step, an etching mask 44 (a hatched portion) made of, for example, a resist is formed on the insulating film 43 by a normal photolithography technique, and then the first and second node contact forming regions 51 and 52 are formed. Openings 45 and 46 are formed in the upper etching mask 44.

Then, as shown in FIG. 6 (9), the insulating film 43 below the opening 45, the cap insulating film 34, and the like are removed by etching, and the second connection portion 28 is formed on the side wall.
A first node contact 25 exposing the is formed. At the same time, the insulating film 43 below the opening 46, the cap insulating film 34, and the like are removed to form the second node contact 26 exposing the first connection portion 27 on the side wall. After that, the etching mask 44 is removed by usual asher processing or wet etching.

Further, as shown in FIG. 7, a first node diffusion layer 47 is formed in the first active region 3 of the first node contact 25 by a normal ion implantation method, and
A second node diffusion layer 48 is formed in the second active region 4 of the second node contact 26. Then, the electrode forming film 61 is formed by, for example, the CVD method. After that, a portion indicated by a chain double-dashed line of the electrode forming film 61 is removed by a photolithography technique and etching, and the remaining electrode forming film (61) constitutes a load element of the SRAM.
The gate electrode 62 of the TFT [or a first pattern (not shown) formed by extending the gate electrode 62] is used as the first
Connect to the node contact 25. At the same time, the gate electrode 63 of the second TFT (or a second pattern (not shown) formed by extending the gate electrode 63) that constitutes the load element of the SRAM is connected to the second node contact 2
Connect to 6.

The SRAM memory cell 1 is laid out as described above.

In the method of manufacturing the SRAM memory cell 1 described above, the first and second gate electrodes 11 and 14 of the first and second driver transistors 7 and 8 are formed, and then the first and second driver transistors 7 and 8 are formed.
By forming the second word lines 17 and 18, for example, the first and second gate electrodes 11 and 14 are formed of a single layer of polysilicon, and then gate oxidation is performed, and then the refractory metal layer or the silicide is formed. And second word lines 17 and 1 having a compound layer containing a refractory metal such as metal or polycide
Forming 8 does not cause heavy metal contamination. Therefore, each of the first and second gate electrodes 11 and 14 is formed by one film formation.

In addition, after forming the first and second gate electrodes 11 and 14 with the cap insulating film 34 provided in the upper layer, the first sidewalls are formed on their side walls, and the cap insulating film 40 is provided in the upper layer. Provided first and second word lines 17,
After forming 18, the second sidewalls 41 and 42 are formed on their side walls. And the first and second word lines 1
After forming the insulating film 43 so as to cover 7 and 18, the first and second node contacts 25 and 26 are etched by etching.
To form at least the first and second word lines 17, 1 of the first and second node contacts 25, 26.
The 8 side is formed in a self-aligned manner. Moreover, the first and second connection portions 27 and 28 are exposed on the respective sidewalls of the first and second node contacts 25 and 26.

Next, a method of forming the first and second node contacts 25 and 26 in the case of the first and second word lines 17 and 18 described in FIG. 3 will be described with reference to the manufacturing process chart of FIG. As shown in (1) of FIG.
As described with reference to FIGS. 1 and 3, the first and second driver transistors 7 and 8 and the first and second word transistors 9 and 10 are provided. Also, the first and second word lines 1
7 and 18 are connected to both ends of the SRAM memory cell 1 and to the central portion thereof, and openings 29 and 30 are provided on the first and second node contact formation regions 51 and 52. .

Further, as shown in (2) and (3) of FIG.
A cap insulating film 40 is provided on each upper surface of each of the first and second word lines 17, 18, and second sidewalls 41, 42 are formed on each side wall. The insulating film 43 is formed on the semiconductor substrate 2 having the above structure in the same manner as described in (7) of FIG.

Thereafter, in the same manner as described with reference to FIG. 6 (8), an ordinary photolithography technique is carried out to form an etching mask 44 made of, for example, a resist (hatched portion) on the insulating film 43. Form. Then, openings 45 and 46 are formed in the etching mask 44 on the formation regions 51 and 52 of the first and second node contacts.

Then, as shown in (4) and (5) of FIG. 9, in the same manner as described in (9) of FIG. 6, the insulating film 43 below the opening 45 and the cap insulation are etched by etching. The film 34 and the like are removed to expose the first active region 3 at the bottom and form the first node contact 25 at which the second connection portion 28 is exposed at the sidewall. At the same time, the insulating film 43 below the opening 46, the cap insulating film 34, and the like are removed to expose the second active region 4 at the bottom and the first connection portion 27 at the sidewall. 26 is formed. At this time,
The respective thicknesses of the second sidewalls 41 and 42, the cap insulating film 40, and the insulating film 43 form the first and second node contacts 25 and 26 in a self-aligned manner. After that, the etching mask 44 is removed by usual asher processing or wet etching.

Although not shown, the first and second node contacts 25, 2 are further processed in the same manner as described with reference to FIG.
The gate electrodes 62 and 63 of the TFT connected to 6 are formed.

A method of forming the first node contact in the case where the first word lines 17 are formed deviated in (2) of FIG. 8 will be described with reference to FIG. As shown in (1) of FIG. 10, the first word line 17 is formed on the side opposite to the first node contact forming region 51 side. In such a case, the side surface 45a of the opening 45 formed in the etching mask 44 determines one side surface of the first node contact (25). The other side surface of the first node contact 25 is determined in a self-aligned manner. Although not shown, the same applies to the formation region 52 of the second node contact.

Further, as shown in (2) of FIG.
When the word line 17 is stacked on the first gate electrode 11 and the first gate electrode 11 is formed adjacent to the first node contact formation region 51 side,
An etching mask 4 is formed on the first gate electrode 11 so that the first gate electrode 11 is not exposed by etching.
The opening 45 is formed in a state of being covered with 4. Therefore, the side surface 45a of the opening 45 is etched by etching.
Determines one side of the first node contact (25) to be formed. The other side surface of the first node contact 25 to be formed is determined in a self-aligned manner. Although not shown, the same applies to the formation region 52 of the second node contact.

In the above manufacturing method, due to misalignment,
Even if the openings 45 and 46 formed in the etching mask 44 are formed deviating from the prescribed positions, the first and second node contacts 25 and 26 are formed in a self-aligned manner.
For example, the first and second word lines 17 and 18 are not exposed to the first and second node contacts 25 and 26.

The numerical values used in the description of the above embodiments are examples, and the values are not limited to them.

[0080]

As described above, the SRAM of the present invention is as described above.
According to this memory cell, the first and second word lines are arranged corresponding to a part of each gate electrode of the first and second driver transistors, so that the memory cell area can be reduced. Further, the semiconductor substrate in the memory cell is
By forming the active regions substantially in parallel and arranging the first and second word lines in a state of being substantially orthogonal to them, the memory cell becomes laterally long. As a result, a sufficient bit line interval can be ensured.

If at least one or both of the gate electrodes of the respective driver transistors or the first and second word lines are arranged point-symmetrically with respect to the central portion of the memory cell of the SRAM, the memory cell Easy to design.

If at least the first and second word lines are connected in a memory cell array region having a plurality of the memory cells, signals transmitted by the word lines can be transmitted in the same phase. Therefore, there is no phase shift.

In the method of manufacturing the memory cell of the SRAM, the gate electrodes of the first and second driver transistors can be formed in one layer, so that the thin film gate electrode can be formed. Therefore, the step difference of the device can be reduced, and the coverage of the upper layer film can be improved. Further, it is possible to reduce the manufacturing process and the manufacturing cost.

Further, the first and second word lines are the first and second word lines.
Since it is formed after the gate electrode of the driver transistor is formed, it can be formed of a refractory metal material or a material having a compound layer containing a refractory metal such as silicide or polycide. In addition, since heavy metal contamination does not occur at the time of its formation, the yield can be improved.

Further, since the sidewalls formed on the sidewalls of the first and second word lines and the cap insulating film are formed,
The first and second node contacts can be formed in a self-aligned manner. Moreover, the first and second connection parts can be exposed on those side walls.

[Brief description of drawings]

FIG. 1 is a layout diagram of an example.

FIG. 2 is a layout diagram of word lines in a memory cell array.

FIG. 3 is another layout diagram of word lines.

FIG. 4 is a manufacturing process diagram (1) of the embodiment.

FIG. 5 is a manufacturing process diagram (2) of the embodiment.

FIG. 6 is a manufacturing process diagram (3) of the embodiment.

FIG. 7 is a manufacturing process diagram of a TFT.

FIG. 8 is a manufacturing process diagram of another node contact (No. 1)
Is.

FIG. 9 is a manufacturing process diagram of another node contact (No. 2)
Is.

FIG. 10 is an explanatory diagram of positioning of node contacts.

FIG. 11 is a layout diagram of a conventional example.

FIG. 12 is a layout diagram of another conventional example.

[Explanation of symbols]

 1 SRAM Memory Cell 2 Semiconductor Substrate 3 First Active Area 4 Second Active Area 6 Memory Cell Array 7 First Driver Transistor 8 Second Driver Transistor 9 First Word Transistor 10 Second Word Transistor 11 First Gate Electrode 14 Second Gate Electrode 17 First word line 18 Second word line 25 First node contact 26 Second node contact 27 First connecting portion 28 Second connecting portion 31 First gate insulating film 32 Second gate insulating film 34 Cap insulating film 40 Cap insulating Film 41 Second sidewall 42 Second sidewall 43 Insulating film 44 Etching mask 45 Opening 46 Opening 51 First node contact formation region 52 Second node contact formation region 62 First TFT gate electrode 63 Second TFT gate Electric very

Claims (7)

[Claims] 1. A static RAM memory cell in which two word lines are arranged substantially in parallel in one memory cell, wherein a first active region formed on a semiconductor substrate in the memory cell and the first active region are formed. A second active region formed on the semiconductor substrate substantially parallel to the region; a first driver transistor formed on the first active region on one side of the memory cell in the diagonal direction; A second driver transistor formed in the second active region on the other side, and a state on at least a part of the gate electrode of the first driver transistor and substantially orthogonal to the first active region and the second active region. At least one of the first word line and the gate electrode of the second driver transistor A memory cell of a static RAM, comprising: the second word line arranged on a part of the first active region and the second active region so as to be substantially orthogonal to the first active region and the second active region. 2. The static RAM memory cell according to claim 1, wherein the gate electrodes of the first and second driver transistors and the first and second word lines are arranged substantially parallel to each other. Memory cell of static RAM. 3. The static RAM memory cell according to claim 1 or 2, wherein the static RAM memory cell is arranged substantially on the central portion of the first active region between the first and second word lines. A first node contact, a second node contact disposed approximately above the center of the second active region between the first and second word lines, and a second node contact connected to the first node contact,
Second extension of the gate electrode of the driver transistor
A connecting part, which connects to the second node contact,
A first extension of the gate electrode of the driver transistor
A static RAM having a connection part
Memory cells. 4. The memory cell of the static RAM according to claim 1, wherein the memory cell of the static RAM has the first, second, and third points with respect to one point at a substantially central portion of the memory cell. At least one or both of the gate electrode of the driver transistor and the first and second word lines are arranged in point symmetry, and the static R is provided.
AM memory cell. 5. The static RAM memory cell according to claim 1, wherein the first and second word lines are provided with a plurality of the memory cells. A memory cell of a static RAM, wherein the memory cells are connected at least in the memory cell array region. 6. A semiconductor substrate is provided with first and second active regions substantially in parallel, and then a first gate insulating film is formed on the first active region and a second gate insulating film is formed on the second active region. The first connection part is formed so as to cross the first active region of the first gate electrode of the first driver transistor having the cap insulating film formed thereon, and the second connection part is connected to the first gate electrode. A second insulating layer is formed so as to reach the formation region of the node contact on the active region, and at the same time, a cap insulating film is formed on the upper layer.
The second gate electrode of the driver transistor is formed so as to cross the second active region, and the second connecting portion connected to the second gate electrode is formed so as to reach the formation region of the node contact on the first active region. First to do
And a second step of forming a first sidewall on a sidewall of the gate electrode of each of the first and second driver transistors, and a cap on the upper layer in a state of at least overlapping a part of the first gate electrode. A third step of forming a first word line provided with an insulating film and forming a first word line provided with a cap insulating film as an upper layer in a state of at least overlapping a part of the second gate electrode; A fourth step of forming a second sidewall on the side walls of each of the first and second word lines; a fifth step of forming an insulating film so as to cover the first and second word lines; After forming an etching mask on the film and then forming an opening in the etching mask on the formation region of each node contact, the first and second portions below each opening are etched. A sixth node contact is formed in which the active region is exposed and the second connection portion is exposed on the side wall side, and a second node contact is formed in which the first connection portion is exposed on the side wall side. A method of manufacturing a memory cell of a static RAM, comprising: 7. The method of manufacturing a memory cell of a static RAM according to claim 6, wherein after forming the first and second node contacts, a gate electrode of a first thin film transistor that constitutes a load element of the static RAM or the gate electrode of the first thin film transistor. A first pattern formed by extending a gate electrode is formed by connecting to the first node contact, and a gate electrode of a second thin film transistor forming a load element of the static RAM or a second pattern formed by extending the gate electrode. A method of manufacturing a memory cell of a static RAM, comprising forming a pattern by connecting to the second node contact.