JPH05251666A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [Object] A semiconductor device including a thin film transistor,
The purpose is to suppress deterioration of the gate insulating film while maintaining good performance of the thin film transistor. [Structure] Two semiconductor layers 10 and 13 sandwiching an insulating film 11 are used as channel regions, and a gate electrode Gp ₁ is formed at least under the semiconductor layers 10 and 13 with an insulating film 9 interposed therebetween. The thin film transistors t ₂₁ and t ₂₂ are included.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a thin film transistor.

[0002]

2. Description of the Related Art SRAM (s) composed of MOS transistors
The tatic random access memory cell has a circuit configuration as shown in FIG. 8A, and has two CMOs composed of driving MOSFETs t ₁₁ and t ₁₂ and load MOSFETs t ₂₁ and t _22.
SFETs q ₁ and q ₂ and two transfer MOSFETs t ₃₁ ,
and t ₃₂ .

Two CMOSFETs q ₁ and q ₂
Of the CMOSFETs q ₂ and q ₁ of the other side.
Source / drain (S / D) of different transfer MOSFETs t ₃₁ and t _32.
Are connected to different bit lines BL ₁ and BL ₂ via. The gates of the transfer MOSFETs t ₃₁ and t ₃₂ are connected to the same word line WL.

Further, the load MOSFET t_{twenty one}, T_{twenty two}of
The voltage Vcc is applied to the source, and the driving MOSFET t
₁₁, T₁₂The voltage Vss is applied to the source of the. Toko
If the SRAM is formed on the semiconductor substrate, the driving
MOSFETt ₁₁, T₁₂And transfer MOSFET
t₃₁, T₃₂While forming in bulk, load MOSFE
Tt_{twenty one}, T_{twenty two}The double gate structure thin film transistor (TF
It is recommended to use T) to form and stack on the bulk.
Is being proposed.

Therefore, first, the planar structures of the driving MOSFET and the transfer MOSFET will be described with reference to FIG. 9 (a). In FIG. 9A, a selective oxide film 103 surrounding a rectangular frame-shaped active region 102 is formed on the upper surface of a semiconductor substrate 101 made of p-type silicon, and a film thickness of 20 nm or less is formed on the surface of the active region 102. An insulating film 104 made of SiO ₂ is formed. However, only a part of the active region 10 is shown.

Further, two n-type MOSFETs are formed in two parallel side regions of the rectangular frame-shaped active region 102, and the gate electrodes Gn of the n-type MOSFETs are formed in different active regions across the side regions. Extended into the corner area of 102,
Moreover, the n-type impurity diffusion layer 10 formed in the corner region
It is connected to 5 through contact hole CH ₁ . And 2 connected to each other through the gate electrode Gn
Two n-type MOSFETs for driving SRAM
Used as Tt ₁₁ and t ₁₂ .

Further, the word line WL extends across the remaining two side regions of the above-mentioned rectangular frame-shaped active region 102, and in that region, the word line WL is used as a gate electrode for transfer. MOSFETs t ₃₁ and t ₃₂ are formed, and these transfer MOSFETs t ₃₁ and t ₃₂ are connected to the driving MOSFETs t ₁₁ and t ₁₂ via the n-type impurity diffusion layer 105 of the active region 102 serving as the source / drain thereof. There is.

The n-type impurity diffusion layer 105 is formed in a self-aligned manner with the active layer 102 using the gate electrode Gn and the word line WL as a mask, and serves as a source / drain layer of the MOSFET.

Transfer MOSFET formed by this
t₃₁, T₃₂And driving MOSFETt ₁₁, T₁₂Is shown in FIG.
The connection state is as shown in the lower circuit shown in (b). next,
The structure of the load MOSFET is shown in FIGS. 9 (b), 10 (c), and (d).
It will be described based on.

The load MOSFETs t ₂₁ and t ₂₂ are shown in FIG.
It is formed of a double-gate thin film transistor as shown in (d), and is composed of a thin silicon layer 108 serving as a channel region and a source / drain region thereof and upper and lower gate electrodes Gp ₁ and Gp ₂ sandwiching the thin silicon layer 108.

The lower gate electrode Gp₁Is shown in Fig. 9 (b)
As shown, transfer MOSFET t ₃₁, T₃₂And drive M
OSFETt₁₁, T₁₂Covering SiO₂Of insulating film 105
N-type impurity formed on the corners of the active region 102
A shape that covers the object diffusion layer 105 and the gate electrode Gn adjacent to it.
It is in a state.

Further, as shown in FIG. 10C, the silicon film 108 formed on the insulating film 107 made of SiO ₂ has a gate electrode Gn of the driving MOSFETs t ₁₁ and t _12.
The planar shape along the word line WL and the portion above the word line WL becomes the Vcc power supply line L. On top of that,
The lower gate electrode G is formed through the insulating film 109 made of SiO _2.
An upper gate electrode Gp ₂ having the same size as p ₁ is formed.

In the region of the silicon layer 108 which is not sandwiched by the upper and lower gate electrodes Gp ₁ and Gp ₂ , a p-type impurity diffusion layer 109 serving as a source / drain is formed as shown in FIG. 10 (c). ing.

Further, the insulating films 104, 106, 107 and 110 located above the corners of the active region 102, the load MOSFETs.
The silicon layer 108 and the lower gate electrode Gp ₁ of t _21, t ₂₂ be formed a contact hole CH _2, the upper and lower gate electrodes Gp ₁ by hanging a part of the upper gate electrode Gp ₁ therein , Gp ₂ , the silicon layer 108, and the n-type impurity diffusion layer 105 are electrically connected to each other, whereby the upper circuit shown in FIG. 8B and the wiring shown by the broken line are formed.

By the way, of the SRAM cells described above,
A cross section taken along the silicon layer 108 of the load MOSFETs t ₂₁ and t _{22 and} the Vcc power supply line L connected to the silicon layer 108 is shown in FIG.
It becomes as shown in (a).

In FIG. 11A, reference numeral 111 is an interlayer insulating film made of PSG or the like laminated on the load MOSFETs t ₂₁ and t ₂₂ , and is a silicon layer 10 to be the Vcc power supply line L.
A contact hole 112 is formed on the wiring 8 and the Vcc power supply wiring 113 arranged on the interlayer insulating film 111.
Is connected to the Vcc power supply line L through the contact hole 112. In FIG. 11, the same symbols as those in FIGS. 9 and 10 indicate the same elements.

However, according to such a structure, the contact hole 112 is opened by the dry etching method using a gas containing CHF ₃ , so that when the silicon layer 108 is an extremely thin film, the interlayer insulating film 111 is formed. Since the lower silicon layer 108 is penetrated and etched further downward, a short circuit will occur if there is another wiring therebelow. On the other hand, although it may be possible to increase the thickness of the silicon layer 108, load MOSFETs (thin film transistors) t ₂₁ and t
This method is not suitable because the performance of the transistor deteriorates as the thickness of the semiconductor layer that becomes the channel region of ₂₂ increases.

Therefore, an apparatus having another structure as shown in FIG. 11 (b) has been proposed. In FIG. 11 (b), reference numeral 11
Reference numeral 4 is a contact hole formed by opening the insulating film 107 covering the gate electrodes Gp ₁ below the load MOSFETs t ₂₁ and t ₂₂ and the insulating films 106 and 104 thereunder, and is a p-type impurity diffusion inside the N well 115. The silicon layer 108 is formed on the layer 116 and is connected to the p-type impurity diffusion layer 116 through the contact hole 114. Further, contact holes 117 are formed in the insulating films 104, 106, 107, 110 and the interlayer insulating film 111 on the p-type impurity diffusion layer 116, and the Vcc power supply wiring 113 has its contact holes 117.
Through the silicon layer connected to the p-type impurity diffusion layer 116 through
It is configured to conduct with 108.

In this case, the p-type impurity diffusion layer 116 has a p-type load MOSFET (p-type thin film transistor) t ₂₁ ,
Since it is connected to the p-type source layer at t ₂₂ , current cannot flow unless it is p-type. Therefore, the Vcc power supply wiring 113
Are formed in the N well 115 outside the area of the SRAM cell.

According to this structure, after the contact hole 114 for connecting the silicon layer 108 to the p-type impurity diffusion layer 115 is formed, the photoresist (not shown) is removed by O ₂ plasma. Since the cleaning treatment with sulfuric acid is performed, the surface of the semiconductor substrate 101 exposed from the contact hole 114 is oxidized to form a natural oxide film, which needs to be removed with hydrofluoric acid.

However, when the natural oxide film is removed by hydrofluoric acid, as shown in FIG. 11 (c), the lower gate electrode Gp ₁
There is a problem that the surface of the SiO ₂ insulating film 107 covering the same is damaged at the same time and becomes thin in a scattered spot, and the breakdown voltage between the lower gate electrode Gp ₁ and the silicon layer 108 is significantly lowered.

Therefore, as shown in FIGS. 12A and 12B, the p-type diffusion layer 116 is formed with the silicon layer 118 containing impurities formed on the insulating film 107 covering the lower gate electrode Gp _1. After forming the upper contact hole 120 and removing the natural oxide film on the surface of the p-type diffusion layer 116 exposed from the contact hole 120 by hydrofluoric acid, a second silicon layer 128 containing impurities is laminated. A method of patterning with the first silicon layer 118 is adopted.

In this case, the second silicon layer 128 and the p-type impurity diffusion layer 116 are connected through the contact hole 120, and then the interlayer insulating film 111 is laminated and the contact hole 121 is formed therein. The Vcc power supply wiring 113 is connected to the p-type impurity diffusion layer 116 through the hole 121.
It is connected to (Fig. 12 (c)).

As a result, the insulating film 107 covering the lower gate electrode Gp ₁ is protected by the silicon layer 118 of the first layer, and is not damaged by the hydrofluoric acid treatment.

[0025]

However, when the performance of a thin film transistor using a silicon layer which constitutes the channel region and which is directly stacked in two steps is measured,
There arises a problem that the source / drain current in the on-state is reduced by about two digits and the leak current in the off-state is increased several times.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of suppressing deterioration of a gate insulating film while maintaining good performance of a thin film transistor. ..

[0027]

As shown in FIG. 3, the above-mentioned problem is solved by the two semiconductor layers 10 and 13 with the insulating film 11 sandwiched therebetween.
And a thin film transistor t ₂₁ , t ₂₂ having a gate electrode Gp ₁ formed via an insulating film 9 at least under the semiconductor layers 10 and 13 as a channel region. To achieve.

Alternatively, as illustrated in FIGS. 1 to 8, the lower gate electrode Gp ₁ formed on the first insulating film 8 on the semiconductor substrate ₁ and the lower gate electrode Gp ₁ are A first semiconductor layer 10 formed on the second insulating film 9 which covers and serves as a channel region and a gate / source region of a transistor;
A third insulating film 11 covering the first-layer semiconductor layer 10 and a part of the conductive layer 7 formed on the semiconductor substrate 1 are exposed by opening a layer below the third insulating film 11. A contact hole 12, a second semiconductor layer 13 formed on the third insulating film 11 and connected to the conductive layer 7 through the contact hole 12, and a second semiconductor layer. This is achieved by a semiconductor device characterized by having thin film transistors t ₂₁ and t ₂₂ each having an upper gate electrode Gp ₂ formed on a layer 13 with a fourth insulating film 14 interposed therebetween.

Alternatively, the thin film transistors t ₂₁ , t ₂₂
Are achieved by a semiconductor device characterized by being a load element of an SRAM cell.

[0030]

According to the present invention, thin film transistors t ₂₁ , t
_{Since the} semiconductor layers 10 and 13 to be the channel region of ₂₂ have a two-layer structure and the insulating film 11 is interposed between them, according to the test results, the semiconductor layers are directly stacked in two steps. No decrease in drain current or generation of leakage current was observed as in the device.

In this way, the semiconductor layer 1 is sandwiched by the insulating film 11.
When 0 and 13 have a two-layer structure, the transistor performance is not deteriorated because the respective crystal growths are performed independently of each other, and the crystals of the respective layers interfere with each other. This is probably because it does not grow and deterioration does not occur.

Further, according to the present invention, when the semiconductor layer which becomes the channel region of the thin film transistors t ₂₁ and t ₂₂ and the conductive layer 7 of the semiconductor substrate 1 are connected, the lower gate electrode Gp ₁
Since the contact hole 12 is formed in a state where the upper first semiconductor layer 10 is covered with the insulating film 11, and the surface of the semiconductor substrate 1 exposed from the contact hole 12 is removed by hydrofluoric acid, the lower gate is formed. The insulating film 9 between the electrode Gp ₁ and the semiconductor layer 10 is not damaged.

In this case, the insulating film 11 covering the first semiconductor layer 10 is damaged, but since it has the same potential as the second semiconductor layer 13 formed thereon, the problem of withstand voltage does not occur.

[0034]

1 to 3 are sectional views showing a manufacturing process of a device according to an embodiment of the present invention, and FIGS. 4 to 7 are plan views showing a manufacturing process of the device according to the embodiment. Further, FIG. 8 is a general circuit diagram of an SRAM cell using a MOSFET. 1 to 3 are sectional views taken along the line AA shown in FIG.

Then, one embodiment of the device of the present invention will be described along the steps of forming the SRAM cell shown in FIGS. First,
As shown in FIG. 1 (a), an N well 2 is formed outside the SRAM cell formation region of a semiconductor substrate 1 made of p-type silicon, and then the surface of the semiconductor substrate 1 as shown in FIG. 4 (a) is formed. N-well 2 and the part that defines the rectangular frame-shaped active region X
An oxide film 4 for element isolation having a thickness of several hundreds nm is formed by a selective oxidation method in a portion surrounding a part of. After that, an insulating film 3 made of SiO ₂ having a thickness of 10 nm is grown in the other region by a thermal oxidation method.

In the plan view of the active region X, a part thereof is omitted. Subsequently, as shown in FIG. 1A, a part of the insulating film 3 in the four corner regions of the rectangular frame-shaped active region X is removed by photolithography to form an opening 5. A part of the semiconductor substrate 1 is exposed through the opening 5.

Next, a polycrystalline silicon film is laminated on the semiconductor substrate 1 by a vapor phase growth method (CVD method) to a thickness of several hundred nm,
After introducing an n-type impurity such as phosphorus or arsenic into the inside, it is patterned to form a driving MOSFE shown in FIG. 8 (a).
The word line WL is formed with the gate electrodes Gn of Tt ₁₁ and t ₁₂ .

As shown in FIG. 4B, two gate electrodes Gn are formed in two parallel side regions of the rectangular frame-shaped active region X so as to cross the side regions and to have different active regions. The shape is such that it extends to the opening 5 in the corner area of the area X.

Further, the word line WL has the above-mentioned active region X.
Of the two remaining side regions of the
The area intersecting the area is the transfer MOSFE shown in Fig. 8 (a).
Tt ₃₁, t₃₂Gate electrode.

Thereafter, as shown in FIG. 1B, the active region of the semiconductor substrate 1 is masked with the photoresist covering the N well 2, the gate electrode Gn, the word line WL and the element isolation oxide film 4. Arsenic is ion-implanted into X and diffused to form an n-type impurity diffusion layer 6.

The n-type impurity diffusion layer 6 is a driving MOS.
The FETs t ₁₁ and t ₁₂ and the transfer MOSFETs t ₃₁ and t ₃₂ serve as sources / drains, and also function as bulk wirings. As a result, the driving MOSFETs t ₁₁ and t ₁₂ and the transfer MOSFETs ₃₁ and t ₃₂ are formed as shown in FIG. The connection state is as shown in the lower circuit of b).

Further, the active region X is covered with a photomask (not shown), boron is ion-implanted into a partial region of the N well 2, and this is activated to form a p-type impurity diffusion layer 7. Note that the heat treatment for forming the n-type impurity diffusion layer 6 and the p-type impurity diffusion layer 7 may be performed independently, or heat may be used in the subsequent film formation process.

Next, an insulating film 8 made of SiO ₂ is grown to a thickness of 100 nm by the CVD method, and then a polycrystalline silicon film is deposited to a thickness of 50 nm by the CVD method. After the introduction, this is patterned by a photolithography method to form a gate electrode Gp ₁ under the thin film transistor to be formed, as shown in FIGS. 1C and 5C.

The lower gate electrode Gp ₁ has an active region X.
Are formed in the regions covering the n-type impurity diffusion layers 6 at the four corners and the gate electrodes Gn of the driving MOSFETs t ₁₁ and t _{12 having} the regions as drains.

Next, as shown in FIG. 2 (d), CVD
After forming an insulating film 9 made of SiO ₂ with a film thickness of 20 nm by a CVD method, a polycrystalline silicon 10 film is grown to a thickness of 20 nm by a CVD method using a gas such as SiH ₄ or Si ₂ H ₆ , and then,
A SiO ₂ film 11 having a film thickness of 10 nm is deposited thereon.

After this, a photoresist (not shown) is formed, and N is formed by reactive ion etching (RIE).
The contact hole 12 is formed by continuously etching from the uppermost insulating film 11 on the p-type impurity diffusion layer 7 of the well 2 to the insulating film 3 on the surface of the semiconductor substrate 1 thereunder.

Next, as shown in FIG. 2E, a second-layer polycrystalline silicon film 13 having a film thickness of 20 nm is formed in the entire region from the bottom surface of the contact hole 12 to the upper surface of the uppermost insulating film 11. Are formed by the CVD method.

Next, a photoresist (not shown) is formed on the lower side of the thin film transistor, which overlaps with the gate electrode Gp _1, and boron is used for accelerating energy of 10 keV and dose of 1 × 1.
Ions are implanted under the condition of 0 ¹⁴ / cm ² , and then the acceleration energy is changed to 20 keV and boron is again implanted at the same dose amount to introduce p-type impurities into the two-layer polycrystalline silicon films 10 and 13.

Here, the reason why the ion implantation is performed twice by changing the energy is that the two-layer polycrystalline silicon films 10 and 1 are used.
This is because the impurities are optimally introduced into each of No. 3, but there is no big problem even if the impurities are introduced simultaneously by one ion implantation.

After that, the two layers of polycrystalline silicon films 10 and 13 and the insulating film 1 between them are formed by photolithography.
1 is patterned using one mask, and
As shown in (d), the region along the word line WL and the gate electrode Gn of the transfer MOSFETs t ₁₁ and t ₁₂ from the region.
To have a planar shape that covers the area up to. In this case, the portion of the two-layer polycrystalline silicon films 10 and 13 formed along the word line WL serves as the Vcc voltage wiring, and the polycrystalline silicon film 13 of the second layer is the contact hole 12
Through, and is connected to the first-layer polycrystalline silicon 10 and the p-type impurity diffusion layer 7 to be in a conductive state.

CC is used for etching polycrystalline silicon.
A mixed gas of l ₄ and O ₂ is used, and CHF ₃ and He are used for etching SiO _2.
Use mixed gas. After that, the insulating film 14 made of SiO ₂ is deposited to a thickness of 50 nm by the CVD method. In this case, the reason why the insulating film 9 is thicker than the insulating film 9 covering the lower gate electrode Gp _{1 is} that hydrofluoric acid treatment during growth of the polycrystalline silicon film forming the upper gate electrode Gp ₂ to be formed next is taken into consideration. is there.

Next, the insulating films 9, ₁₁ , 14 above the gate electrodes Gn of the driving MOSFETs t ₁₁ , t ₁₂ , the polycrystalline silicon films 10, 13, and the lower gate electrode Gp ₁ are etched by photolithography. After forming the opening 15, the drive MO exposed from the opening 15
The natural oxide film formed on the surfaces of the gate electrodes Gn of the SFETs t ₁₁ and t ₁₂ is removed by hydrofluoric acid.

Then, a polycrystalline silicon film is formed by the CVD method, phosphorus is ion-implanted, and then this is patterned by the photolithography method to form a region facing the lower gate electrode Gp ₁ of the thin film transistor in FIG. ), Fig. 6
An upper gate electrode Gp ₂ as shown in (e) is formed.

A part of the gate electrode Gp _{2 on} the upper side enters into the opening 15 to form the double gate electrodes Gp ₁ and Gp ₂ of the thin film transistor and the polycrystalline silicon films 10 and 13 to serve as the drain of another thin film transistor. And conducts them to the n-type impurity diffusion layer 6 serving as the drains of the driving MOSFETs t ₁₁ and t ₁₂ .

As a result, the two-layer polycrystalline silicon film 1 is formed.
0 and 13 and the two gate electrodes Gp ₁ and Gp ₂ formed above and below the insulating films 9 and 14 complete thin film transistors t ₂₁ and t ₂₂ as illustrated in FIG. 6 (f). Is used as the load MOSFET, the upper circuit of FIGS. 6 (f) and 8 (b) and the wiring layer shown by the broken line are formed.

Next, after forming the entire insulating film 23 as shown in FIG. 7, the active region X of the same drive is formed adjacent at sides regions _{MOSFETt 11, t 11, t 12} , t 12
A contact hole 24 exposing the semiconductor substrate 1 between the two is formed, and a wiring (not shown) for supplying the voltage Vss through the contact hole 24 is formed.

Next, as shown in FIG. 3, an interlayer insulating film 20 is deposited on the entire surface, and then the insulating films 3, 8, 9, 14, 20, 23 on the p-type impurity diffusion layer 7 are photolithographically formed. By selective etching to form an opening 21 exposing the p-type impurity diffusion layer 7. At the same time, in the n-type impurity diffusion layer 6 serving as the source / drain of the transfer MOSFETs t ₃₁ and t ₃₂ , the driving MOSFET is used.
A contact hole 25 is provided to expose a portion that is not connected to Tt ₁₁ and t ₁₂ .

After that, an aluminum film is deposited by the sputtering method and is patterned by the photolithography method to form the Vcc power supply wiring 22 passing through the opening 21 on the p-type impurity diffusion layer 7. This gives V
The cc power supply wiring 22 and the polycrystalline silicon films 10 and 13 forming the thin film transistors t ₂₁ and t ₂₂ are electrically connected via the p-type impurity diffusion layer 7. Further, by forming BL ₁ and BL ₂ passing through the contact hole 25, the SRAM cell is completed.

SRA formed by the above steps
In the M cell, when the polycrystalline silicon film which becomes the channel regions of the thin film transistors t ₂₁ and t ₂₂ and the p-type impurity diffusion layer 7 of the semiconductor substrate 1 are connected, the first polycrystalline silicon film 10 is formed by the insulating film 11. Since the contact hole 12 is formed in the covered state and the surface of the semiconductor substrate 1 exposed from the contact hole 12 is removed by hydrofluoric acid, the insulating film 9 directly covering the lower gate electrode Gp ₁ is damaged. I will not receive it.

Further, although the insulating film 11 covering the first-layer polycrystalline silicon film 10 is damaged, it has the same potential as the second-layer polycrystalline silicon film 13 formed on the insulating film 11, so that there is a problem of withstand voltage. Does not happen.

Furthermore, in the present embodiment, the polycrystalline silicon films 10 and 13 which become the channel regions of the thin film transistors t ₂₁ and t ₂₂ have a two-layer structure, and the insulating film 11 is interposed between them. No decrease in drain current or generation of leakage current was observed as in the conventional example in which two layers were stacked to form a polycrystalline silicon film.

When the polycrystalline silicon films 10 and 13 have a two-layer structure with the insulating film 11 sandwiched therebetween as in this embodiment, the transistor performance is not deteriorated because the crystal growth of each is not affected. Since they are performed independently, it is considered that the crystals do not grow due to interference with each other and deterioration does not occur. In addition, the leakage current increases in the structure of the conventional example,
It is considered that the drain current decreases because such crystal growth adversely affects each other.

In the above-mentioned embodiment, the insulating film 11 between the two layers of polycrystalline silicon films 10 and 13 is made of SiO _2. However, since this is not a gate insulating film, Si ₃ N
₄ may be used.

[0064]

As described above, according to the present invention, the semiconductor layer serving as the channel region of the thin film transistor has a two-layer structure, and the insulating film is interposed therebetween. Therefore, according to the test results, the two semiconductor layers are formed. No decrease in drain current or generation of leak current was observed as in the conventional device formed by directly stacking layers.

When the semiconductor layer has a two-layer structure with the insulating film sandwiched in this way, no deterioration in the transistor performance is observed. It is considered that this is because the crystals do not grow due to the interference and the deterioration does not occur.

Further, according to the present invention, when the semiconductor layer which becomes the channel region and the conductive layer of the semiconductor substrate are connected,
A contact hole is formed in a state where the first semiconductor layer is covered with an insulating film, and the surface of the semiconductor substrate exposed from the contact hole may be removed with hydrofluoric acid.
The insulating film between the lower gate electrode and the semiconductor layer can be held well.

In this case, the insulating film covering the first semiconductor layer is damaged, but since the potential is the same as that of the second semiconductor layer formed thereon, the problem of withstand voltage does not occur.

[Brief description of drawings]

FIG. 1 is a cross-sectional view (1) showing a manufacturing process of a device according to an embodiment of the present invention.

FIG. 2 is a sectional view (No. 2) showing the manufacturing process of the device according to the embodiment of the present invention.

FIG. 3 is a sectional view showing an apparatus according to an embodiment of the present invention.

FIG. 4 is a plan view (1) showing the manufacturing process of the device according to the embodiment of the present invention.

FIG. 5 is a plan view (No. 2) showing the manufacturing process of the device according to the embodiment of the present invention.

FIG. 6 is a plan view (3) showing the manufacturing process of the device according to the embodiment of the present invention.

FIG. 7 is a plan view (No. 4) showing the manufacturing process of the device according to the embodiment of the present invention.

FIG. 8 is a circuit diagram showing an SRAM cell.

FIG. 9 is a plan view (part 1) showing a pattern of each layer of a conventional SRAM cell.

FIG. 10 is a plan view (part 2) showing a pattern of each layer of a conventional SRAM cell.

FIG. 11 is a cross-sectional view showing first and second examples of a conventional SRAM cell.

FIG. 12 is a sectional view showing a third example of a conventional SRAM cell.

[Explanation of symbols]

X active region WL the word line t _11, t ₁₂ driving MOSFET t _31, t ₃₂ transfer MOSFET t _21, t ₂₂ load MOSFET Gn, Gp _1, Gp ₂ gate electrode 1 semiconductor substrate 2 N-well 3 insulating film 4 elements Isolation oxide film 5, 15 Opening 6 n-type impurity diffusion layer 7 p-type impurity diffusion layer (conductive layer) 8, 9, 11, 14 insulating film 12 contact hole 10, 13 polycrystalline silicon film (semiconductor layer) 20 interlayer Insulating film 21 Opening 22 Vcc Power supply wiring

Claims (3)

[Claims] 1. A two-layer semiconductor layer (1) sandwiching an insulating film (11).
(0, 13) as a channel region and the semiconductor layer (1
A semiconductor device having thin film transistors (t ₂₁ , t ₂₂ ) provided with a gate electrode (Gp ₁ ) formed via an insulating film (9) at least on the lower side of (0, 13). 2. A lower gate electrode (Gp ₁ ) formed on a first insulating film (8) on a semiconductor substrate (1), and a first gate electrode (Gp ₁ ) covering the lower gate electrode (Gp ₁ ). Formed on the second insulating film (9), the channel region of the transistor, the gate /
A first semiconductor layer (10) serving as a source region, and a third insulating film (11) covering the first semiconductor layer (10)
And a conductive layer (7) formed on the semiconductor substrate (1) by opening a layer below the third insulating film (11).
(2) formed on the third insulating film (11) and connected to the conductive layer (7) through the contact hole (12) exposing a part of the contact hole (12) A second semiconductor layer (13), and a fourth insulating film (14) on the second semiconductor layer (13).
A thin film transistor (t ₂₁ , t ₂₂ ) having an upper gate electrode (Gp ₂ ) formed through the semiconductor device. 3. The thin film transistors (t ₂₁ , t ₂₂ ) are
3. The semiconductor device according to claim 1, which is a load element of an SRAM cell.