JP2987856B2 - Static semiconductor memory device and method of manufacturing the same - Google Patents

Description

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a structure and a method of manufacturing an SRAM memory cell.

[Prior Art] Integrated circuits formed on a semiconductor substrate such as a silicon substrate have been increasing in capacity and density year by year. In particular, a semiconductor memory device has a high memory capacity of 4 megabits, further 16 megabits or more. It is shifting to the degree of integration.

Although a large-scale integrated circuit requires many elements to be formed on one chip, an increase in chip size must be minimized from the viewpoint of product cost and yield.
In order to satisfy both of these requirements, it is most effective to reduce the occupied area per storage element.

For example, static random access memory (SRA
In a semiconductor memory device such as M), as shown in FIG.
A method in which one memory cell is composed of four MOS transistors and two load resistance elements is suitable for increasing the capacity, and is currently mainstream. However, even in such a configuration, 1
In order to realize a storage capacity of 1 megabit or more per chip, it is important to reduce the area per memory cell. In the case of a 4 megabit SRAM, the area occupied by one cell must be about 20 μm ² . However, when the area of one cell is suppressed as described above, the size of the load resistance becomes a problem.

More specifically, high resistance polysilicon has been widely used for the load resistors 23a and 23b of the SRAM memory cell shown in FIG. At both ends of the high-resistance polysilicon, low-resistance contact portions need to be formed in diffusion regions having an impurity concentration of 10 ¹⁹ to 10 ²⁰ cm ⁻³ in order to connect with wirings and metal electrodes. However, when the area of one cell is reduced and the length of the high-resistance polysilicon is also reduced, a depletion layer extending from both ends into the polysilicon is formed by the voltage applied to the low-resistance portion at both ends of the high-resistance polysilicon. A new problem arises in that they begin to overlap with each other and cause a so-called punch-through phenomenon, causing an excessive current to flow through the high-resistance polysilicon.

In order to solve such a problem, a structure shown in FIG. 4 has conventionally been adopted, and this will be described with reference to FIG. Hereinafter, an n-type memory cell will be described. For a p-type memory cell, the impurity type is changed from n-type to p-type.
The same applies if the p-type is replaced with the n-type.

4a denotes a gate electrode of the driving MOS transistor 20b (or 20a), and 4b denotes a transfer MOS transistor 21a.
The diffusion layer 5a corresponds to the gate electrode (or 21b) and the word line 22 and the driving MOS transistor 20a (or 20b).
b) The drain diffusion layer and the transfer MOS transistor 21a (21
This corresponds to the impurity region of b). An impurity is added to a part of the high-resistance polysilicon 8a to form a low-resistance polysilicon 8b. The low-resistance polysilicon 8b is connected to the diffusion layer 5a through the connection hole 7 to connect the node 24a (24b). providing.

On the other hand, the high-resistance polysilicon 17a is connected to the high-resistance polysilicon 8a through the connection hole 10, and the high-resistance polysilicon 8a
And 17a function as load resistors 23a (23b). A part of the high-resistance polysilicon 17a is doped with impurities,
A low-resistance polysilicon 17b functioning as described above is formed.
The aluminum electrode 19 is connected to the bit line 26a (26b), and the connection hole 18 is connected to the bit line 26a (26b) and the transfer MOS transistor 21a.
Bit connection portions 27a (27b), which are connection portions with (21b), respectively.

A manufacturing method for realizing the above structure will be described below. First p
The thickness of the semiconductor substrate 1 is 300
An element isolation oxide film 2 having a thickness of about 1000 nm is formed, and a gate oxide film having a thickness of 5 to 100 nm is formed on the surface of the semiconductor substrate 1. After opening the connection hole 7 between the gate electrode and the diffusion layer by photo-etching, polysilicon is deposited by a well-known LPCVD method, and the gate electrodes 4a and 4b are formed by photo-etching.
N-type diffusion layer to be the source and drain of OS transistor
5a and 5b are formed by ion implantation and annealing. Subsequently, the interlayer film 6 such as a SiO ₂ film is formed to a thickness of 50 to 500 nm by using the LPCVD method.
To adhere.

Next, a part of the interlayer film 6 on the gate electrode 4a or the diffusion layer 5a is opened by photoetching to form a high-resistance polysilicon 8a.
Is grown to a thickness of 50 to 200 nm by LPCVD and patterned. Since the n-type impurity having a high concentration of 10 ¹⁹ to 10 ²⁰ cm ⁻³ is added to the diffusion layer and the gate electrode, the diffusion layer 5a
Alternatively, the impurity is also diffused into the high-resistance polysilicon 8a connected to the gate electrode 4a, and the low-resistance polysilicon 8b is formed. An interlayer film 9 such as a SiO ₂ film is deposited thereon by LPCVD to a thickness of 10 to 500 nm, a connection hole 10 is opened, and a second high-resistance polysilicon 17a is formed to a thickness of 50 to 200 nm by LPCVD.
Grow and pattern it. High resistance polysilicon
Impurities such as phosphorus are implanted at a high concentration by ion implantation using the photoresist as a mask at the end of 17a to form low-resistance polysilicon 17b.

In order to prevent the diffusion of phosphorus from the PSG film covering the whole later to the high-resistance polysilicon 17a and lowering of the resistance value, the thickness is 50 to
A 500 nm SiO ₂ film is deposited, and finally an interlayer film 12 consisting of a PSG film having a thickness of 100 to 100 nm containing 4 mol% of phosphorus and the SiO ₂ film.
Cover with. Then, a contact hole 18 is opened by photoetching on the diffusion layer 5b through the interlayer films 12, 9, 6 and the gate oxide film, an aluminum electrode 19 containing silicon is deposited, and patterning is performed by photoetching. The structure is completed.

According to the above-described structure and manufacturing method, the high-resistance polysilicon 8a of the first layer and the high-resistance polysilicon 17a of the second layer are connected through the connection hole 10, so that the effective length of the high-resistance polysilicon is increased, and It has become possible to reduce the area. This type of semiconductor device is disclosed in Japanese Unexamined Patent Publication No. 61-28316.
1, JP-A-63-142669 and the like.

[Problems to be Solved by the Invention] According to the above prior art, the length of the low-resistance polysilicon 17b (L _{3 in} FIG. 4) and the misalignment of the mask between the low-resistance polysilicon 17b and the connection hole. The length of the second layer high-resistance polysilicon 17a is limited by the interval (L ₄ ) in consideration of the above. For this reason, if the area occupied by the memory cells is reduced as the degree of integration increases, there is a problem that the layout becomes difficult and the length of the high-resistance polysilicon 17a cannot be sufficiently long.

[Differences of the Invention from the Prior Art] In contrast to the above-described prior art, the present invention penetrates the bit line and the transfer line through the low resistance polysilicon which is the power supply wiring formed at the end of the second high resistance polysilicon. A difference is that a connection hole with the diffusion layer of the MOS transistor is opened, and an insulating film is formed on the inner side wall to ensure insulation between the low-resistance polysilicon and the bit line.

[Means for Solving the Problems] The gist of the first invention of the present application is that a pair of high resistance elements connected in parallel to a first power supply wiring and a pair of the high resistance elements and the second power supply are connected. And a transfer field-effect transistor provided between the pair of bit lines and the drain of the drive field-effect transistor, and formed on the semiconductor substrate. The impurity region of the driving field-effect transistor, the impurity region of the transfer field-effect transistor formed on the semiconductor substrate, and the gate of the driving field-effect transistor provided on the semiconductor substrate. A first interlayer insulating film covering a gate of the field effect transistor for use, a first polysilicon film formed on the first interlayer insulating film and having a high resistance portion and a low resistance portion, and the first polysilicon film. A second interlayer insulating film covering the recon film, a second polysilicon film formed on the second interlayer insulating film and having a high resistance portion and a low resistance portion, and a third insulation film covering the second polysilicon film In a static semiconductor memory device having a film and a bit line on the third insulating film, the low-resistance portion of the second polysilicon layer is formed of the first polysilicon layer.
The high resistance part of the first polysilicon layer is connected to the high resistance part of the second polysilicon layer to form the high resistance element, and forms a high resistance element. A connection hole connecting the impurity layer of the effect transistor penetrates the third insulating film, the low-resistance portion of the second polysilicon film, the second interlayer insulating film, and the first interlayer insulating film. This means that the inner wall is covered with an insulator to allow the bit line to pass therethrough.

The gist of the second invention of the present application is that a gate electrode, a first interlayer insulating film, a high resistance part and a low resistance part are formed on a semiconductor substrate on which an impurity region of a driving field effect transistor and an impurity region of a transfer field effect transistor are formed. , A second polysilicon film including a high resistance part and a low resistance part.
Laminating a multilayer structure having a polysilicon film and a third insulating layer; drilling a connection hole through the low-resistance portion of the second polysilicon film in the multilayer structure; The step of depositing an insulator including inside, the step of exposing the impurity region of the transfer field effect transistor by providing a hole in the insulator by anisotropic etching, and the step of depositing a conductor to the exposed impurity region. That is, a step of forming a bit line to be connected is provided.

Examples Examples of the present invention will be described below.

First Embodiment FIG. 1 is a sectional view showing a first embodiment of the present invention.
2 (A) to 2 (D) are cross-sectional views showing manufacturing steps of the first embodiment of the present invention. Hereinafter, description will be given along the manufacturing process.

The process from the formation of the element isolation oxide film 2 on the semiconductor substrate 1 to the deposition of the interlayer film 9 and the opening of the connection port 10 is the same as the conventional description. Then, the second layer high-resistance polysilicon 11a
Is deposited with a thickness of 50 to 200 nm by LPCVD and patterned by photo-etching.
11a covers the diffusion layer 5b. Thereafter, using the resist as a mask, a high-concentration n-type impurity is implanted into the end of the high-resistance polysilicon 11a by ion implantation to form a low-resistance polysilicon 11b. An interlayer film similar to that of the prior art is deposited thereon (FIG. 2 (A)).

Next, a connection hole 13 is opened through the interlayer films 12, 9, 6 and the gate oxide film 3 and the low-resistance polysilicon 11b (FIG. 2B). Then, thickness of 200 to the SiO ₂ film 14 by the LPCVD method
When the SiO ₂ film 14 is grown by 400 nm (FIG. 2C) and the SiO ₂ film 14 is etched by a known anisotropic plasma etching, the SiO ₂ 14 remains 150 to 351 nm thick inside the connection hole 13 due to anisotropy. Side walls are formed (FIG. 2 (D)). Further, when an aluminum electrode 15 containing silicon is deposited and patterned by photoetching, the structure shown in FIG. 1 is completed.

With the structure thus formed, the insulation between the low-resistance polysilicon 11b and the aluminum electrode 15 is performed by the SiO ₂ film 14 when it becomes the side wall in the connection hole 13.

Second Embodiment This embodiment is characterized in that an interlayer film between a first-layer high-resistance polysilicon and a second-layer high-resistance polysilicon is planarized.

3 (A) to 3 (C) are cross-sectional views showing manufacturing steps of a second embodiment of the present invention. Hereinafter, description will be made sequentially along the manufacturing process.

First layer high-resistivity polysilicon in the same manner as conventional technology
After forming up to 8a and the low-resistance polysilicon 8b, a step 10 is performed to prevent phosphorus from diffusing from the PSG film into the high-resistance polysilicon 8a.
And the SiO ₂ film of ~ 100 nm, is deposited an interlayer film 16a composed of a 4 mol% of PSG film with a thickness of 200 to 500 nm (FIG. 3 (A)). Then 1
A known reflow is performed at a temperature of about 000 ° C. to achieve flattening (FIG. 3B). On top of that, in order to prevent impurities from diffusing into the high resistance polysilicon 11a, a 10 to 100 nm thick Si
The O ₂ film 16b is deposited by the LPCVD method, and the connection hole 10, the high-resistance polysilicon 11a, the low-resistance polysilicon 11b, and the interlayer film 12 are formed in the same manner as in the first embodiment (FIG. 3C). . Thereafter, the connection hole 13 is opened, the SiO ₂ film 14 is formed, and the aluminum electrode 15 is formed in the same manner as in the first embodiment.

[Effects of the Invention] As described above, the present invention penetrates through low-resistance polysilicon which is connected to high-resistance polysilicon and serves as a power supply wiring,
By making a connection hole between the bit line and the diffusion layer of the transfer MOS transistor and forming an insulating film on the inner side wall, ensuring insulation between the low-resistance polysilicon and the bit line,
There is an effect that a high-resistance polysilicon having a longer effective length than that of the conventional technique and thus having a higher resistance value can be obtained.

For example, in FIG. ₁ , the distance from the end of the connection hole 10 to the end of the connection hole 13 is L ₁ , the distance from the end of the low-resistance polysilicon to the end of the connection hole 13 is L _2, and in FIG. The distance from the connection hole 18 to L ₁ is the same as before, the length of the low-resistance polysilicon 17b is L ₃ , and the connection hole with the low-resistance polysilicon 17b end is L ₃ .
When 18 the distance to the end and L _4, in the conventional art, the effective length of the high-resistance polysilicon 17a is L ₁ -L ₃ -L _4. In contrast the effective length of the high-resistance polysilicon 11a according to the present invention is L ₁ -L _2. L ₂ and L ₄ be because it is enough to come a demand for such a mask alignment error or etching can be at the same level, which according to the present invention the effective length of the high-resistance polysilicon by at least L ₃ long Becomes possible.

[Brief description of the drawings]

FIG. 1 is a sectional view showing the structure of a first embodiment of the present invention, and FIG.
3A to 3D are cross-sectional views illustrating a manufacturing process according to a first embodiment of the present invention, and FIGS. 3A to 3C are cross-sectional views illustrating a manufacturing process according to a second embodiment of the present invention. FIG. 4 is a sectional view showing a conventional technique, and FIG. 5 is a circuit diagram of an SRAM memory cell. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Isolation oxide film, 3 ... Gate oxide film, 4a, 4b ... Gate electrode, 5a, 5b ... Diffusion layer, 6, 9, 12, 16 ... Interlayer film, 7 , 10,13,18 ...... connection hole, 8a, 11a, 17a ...... high resistance polysilicon, 8b, 11b, 17b ...... low resistance polysilicon, 14, 16b ...... SiO ₂ film, 15, 19 ...... aluminum Electrodes, 20a, 20b: MOS transistors for driving, 21a, 21b: MOS transistors for transfer, 22: Word line, 23a, 23b: Load resistance, 24a, 24b: Node, 25: Power supply, 26a, 26b: Bit line, 27a, 27b: Bit connection.

Claims (2)

(57) [Claims] 1. A pair of high resistance elements connected in parallel to a first power supply wiring, and a pair of driving field effect transistors respectively connected between the pair of high resistance elements and a second power supply. A transfer field effect transistor provided between the pair of bit lines and the drain of the drive field effect transistor, and an impurity region of the drive field effect transistor formed on a semiconductor substrate; An impurity region of the transfer field-effect transistor formed on the semiconductor substrate, a first interlayer insulation covering the gate of the drive field-effect transistor provided on the semiconductor substrate, and the gate of the transfer field-effect transistor A first polysilicon film formed on the first interlayer insulating film and having a high resistance portion and a low resistance portion; a second interlayer insulating film covering the first polysilicon film; A second polysilicon film formed on the insulating film and having a high resistance portion and a low resistance portion, a third insulating film covering the second polysilicon film, and a bit line on the third insulating film; In the semiconductor memory device, the low resistance portion of the second polysilicon layer forms a part of the first power supply wiring, and the high resistance portion of the first polysilicon layer is a high resistance portion of the second polysilicon layer. Forming the high resistance element, the connection hole connecting the bit line and the impurity layer of the transfer field effect transistor is formed by the third insulating film, the low resistance portion of the second polysilicon film, A static semiconductor memory element, wherein a bit line is allowed to pass through the second interlayer insulating film, penetrating the first interlayer insulating film, covering an inner wall of the connection hole with an insulator. A gate electrode, a first interlayer insulating film, a high resistance portion and a low resistance portion on a semiconductor substrate on which the impurity region of the driving field effect transistor and the impurity region of the transfer field effect transistor are formed; Laminating a multilayer structure having a first polysilicon film, a second interlayer insulating film, a second polysilicon film including a high resistance portion and a low resistance portion, and a third insulating layer; A step of piercing the multilayer structure so as to penetrate the low-resistance portion of the silicon film; a step of depositing an insulator including the inside of the connection hole; A method for manufacturing a static semiconductor memory device, comprising: a step of exposing an impurity region of a field effect transistor; and a step of forming a bit line connected to the exposed impurity region by depositing a conductor.