JPH0472730A - Wiring formation process - Google Patents
Wiring formation processInfo
- Publication number
- JPH0472730A JPH0472730A JP18633690A JP18633690A JPH0472730A JP H0472730 A JPH0472730 A JP H0472730A JP 18633690 A JP18633690 A JP 18633690A JP 18633690 A JP18633690 A JP 18633690A JP H0472730 A JPH0472730 A JP H0472730A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- aluminum
- time
- vapor deposition
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 20
- 230000015572 biosynthetic process Effects 0.000 title abstract description 7
- 239000010409 thin film Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 8
- 238000007740 vapor deposition Methods 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 239000010408 film Substances 0.000 abstract description 15
- 229910052782 aluminium Inorganic materials 0.000 abstract description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 9
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000010408 sweeping Methods 0.000 abstract 2
- 238000005019 vapor deposition process Methods 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 230000004913 activation Effects 0.000 description 3
- TUTOKIOKAWTABR-UHFFFAOYSA-N dimethylalumane Chemical compound C[AlH]C TUTOKIOKAWTABR-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000927 vapour-phase epitaxy Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 239000004147 Sorbitan trioleate Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- MCULRUJILOGHCJ-UHFFFAOYSA-N triisobutylaluminium Chemical compound CC(C)C[Al](CC(C)C)CC(C)C MCULRUJILOGHCJ-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、集積回路等を構成する配線の形成方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of forming wiring constituting an integrated circuit or the like.
従来、配線の形成方法としては、フォトリソグラフィを
使う方法、レーザ気相成長法を用いた配線を直接描画す
る方法(第37回応用物理学問係連合講演会講演予稿j
E 496頁 29a−ZE8)などがある。Conventionally, methods for forming wiring include methods using photolithography and direct drawing of wiring using laser vapor phase epitaxy (37th Applied Physics Association Lecture Preliminary).
E 496 pages 29a-ZE8).
上述した従来のフォトリングラフィを使う方法は、フォ
トマスクの作製に加え、成膜、レジスト塗布、露光、現
像、エツチング、レジスト除去の6エ程が必要で、時間
と費用がかがるという欠点がある。また、レーザ気相成
長法を用いて配線を直接描画する方法では、所望の膜厚
を有する配線を形成するために描画速度が制限され、ス
ループットが小さいという欠点がある。The conventional method using photolithography described above requires six steps: film formation, resist coating, exposure, development, etching, and resist removal, in addition to photomask production, which is time-consuming and costly. There is. Furthermore, the method of directly drawing wiring using laser vapor deposition has the disadvantage that the drawing speed is limited in order to form wiring having a desired thickness, and the throughput is low.
本発明の配線の形成方法は、選択気相成長法を用いた配
線用薄膜の堆積に関して不活性な基板の配線領域にエネ
ルギ一線を照射して前記基板の表面を前記堆積に関し、
その後、気相成長法によって、エネルギ一線を照射した
領域に配線を選択的に形成することを特徴とする方法で
ある。The wiring forming method of the present invention involves irradiating a line of energy to a wiring region of an inactive substrate for depositing a thin film for wiring using selective vapor deposition to coat the surface of the substrate.
This method is characterized in that wiring is then selectively formed in the region irradiated with a single line of energy by vapor phase growth.
例えば、ジメチルアルミニウムハイドライドを用いて選
択気相化学成長法でアルミニウム膜を形成すると、シリ
コン上にはアルミニウム膜が堆積し、シリコン酸化膜上
にはアルミニウム膜が堆積せず、選択性が得られる(第
50回応用物理学会学術講演会講演予稿集 631頁
29p−D−1)。このジメチルアルミニウムハイドラ
イドを用いた場合、エネルギ一線をシリコ・ン酸化膜に
照射するとシリコン酸化膜表面の原子が除去され、上記
の選択的な堆積に関し不活性なシリコン酸化膜表面にも
シリコンのダングリングボンドが生成することを新たに
見いだした。このとき、エネルギ一線が照射された領域
は膜堆積に関して活性化された状態になり、気相化学成
長法で、エネルギ一線が照射された領域に選択的にアル
ミニウム膜を形成することができる。For example, when an aluminum film is formed using dimethylaluminum hydride by selective vapor phase chemical growth, the aluminum film is deposited on silicon but not on the silicon oxide film, providing selectivity ( Proceedings of the 50th Japan Society of Applied Physics Academic Conference 631 pages
29p-D-1). When this dimethylaluminum hydride is used, when a silicon oxide film is irradiated with a single energy beam, atoms on the surface of the silicon oxide film are removed, and silicon dangling occurs even on the surface of the inert silicon oxide film due to the selective deposition described above. It was newly discovered that bond is generated. At this time, the area irradiated with the single energy line becomes activated for film deposition, and an aluminum film can be selectively formed in the area irradiated with the single energy line by vapor phase chemical growth.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例における主要工程によって形
成された基板の断面図である。本実施例はシリコン集積
回路における配線の形成に適用した場合を例示する。FIG. 1 is a sectional view of a substrate formed by main steps in an embodiment of the present invention. This embodiment exemplifies a case where the present invention is applied to the formation of wiring in a silicon integrated circuit.
標準的な集積回路製作方法を用いて第1図(a)に示し
た配線を形成する前の構造を形成する(基板に形成した
素子領域は図示省略)。図において、1はシリコン基板
、2はシリコン酸化膜である。次に第1図(b)に示す
ように、配線を形成しようとする領域に、エネルギーI
14を照射しながら掃引し、シリコン酸化膜2の表面の
原子を蒸散させ、活性化層3を形成する。エネルギ一線
としてはここでは、波長193 nm、パルス幅20n
s、パルレス当りのエネルギー密度2MW/pulse
−一のArFエキシマレーザを用いる。次に第1図(c
)に示すように、気相成長法によってアルミニウムを堆
積すると、活性化層3の上にアルミニウム配線5が選択
的に形成する0本実施例では、ジメチルアルミニウムハ
イドライドの熱分解を用いた気相化学成長法により、基
板温度的250℃、キャリア水素流量60SCCM、真
空室圧力2Torrでアルミニウム配線5を選択的に形
成する。配線形成に要する時間は、エネルギ一線4を掃
引する時間と配線用薄膜を形成する時間の和である。エ
ネルギ一線4を掃引する時間はレーザ気相成長法を用い
て厚く配線を直接描画しながら形成する方法に比べ十分
短く、配線用薄膜の選択堆積速度は約500OA/mi
nと速いので、レーザ気相成長法を用いた配線を直接描
画する方法に比べ、配線形成に要する時間を短くできる
。また、本発明の配線の形成方法によると、工程がパタ
ーニング、成膜の2工程に短縮できる。Using a standard integrated circuit manufacturing method, the structure shown in FIG. 1(a) before wiring is formed (the element region formed on the substrate is not shown). In the figure, 1 is a silicon substrate and 2 is a silicon oxide film. Next, as shown in FIG. 1(b), apply energy I to the area where wiring is to be formed.
14 is swept while irradiating the silicon oxide film 2, atoms on the surface of the silicon oxide film 2 are evaporated, and an activation layer 3 is formed. Here, the energy line is 193 nm in wavelength and 20 nm in pulse width.
s, energy density per pulseless 2MW/pulse
- Use one ArF excimer laser. Next, Figure 1 (c
), when aluminum is deposited by the vapor phase growth method, the aluminum wiring 5 is selectively formed on the activation layer 3. By a growth method, the aluminum wiring 5 is selectively formed at a substrate temperature of 250° C., a carrier hydrogen flow rate of 60 SCCM, and a vacuum chamber pressure of 2 Torr. The time required to form the wiring is the sum of the time to sweep the energy line 4 and the time to form the wiring thin film. The time to sweep the energy line 4 is sufficiently shorter than the method of directly drawing thick wiring using laser vapor phase epitaxy, and the selective deposition rate of the wiring thin film is approximately 500 OA/mi.
Since the method is as fast as n, the time required for wiring formation can be shortened compared to a method of directly drawing wiring using laser vapor phase epitaxy. Further, according to the wiring forming method of the present invention, the process can be shortened to two steps: patterning and film formation.
なお、元来この配線用薄膜の選択堆積に関して活性なシ
リコン基板1上にエネルギ一線4を照射した場合にも、
シリコン基板1上が配線用薄膜の堆積に関して活性であ
ることは変わらず、選択性が維持されることはいうまで
もない、また、エネルギ一線を照射した領域以外に存在
する基板上のシリコン、アモルファスシリコン、ポリシ
リコン、金属等の、元来配線用薄膜の堆積に関して活性
な領域にも同時に堆積し、このことを利用してデバイス
製造プロセスに利点をもたらしうることはいうまでもな
い。Note that even when a single energy line 4 is irradiated onto the silicon substrate 1, which is originally active for selective deposition of this wiring thin film,
It goes without saying that the silicon substrate 1 remains active in the deposition of thin films for wiring, and that selectivity is maintained. It goes without saying that it can also be simultaneously deposited on areas that are naturally active for the deposition of interconnect thin films, such as silicon, polysilicon, metals, etc., and that this can be used to provide advantages in device manufacturing processes.
なお、本実施例では配線用原料ガスとしてジメチルアル
ミニウムハイドライドを用いたが、トリイソブチルアル
ミニウム等でもよい。また、配線材料としてアルミニウ
ムを用いたがWF6等を使って形成できるタングステン
等でもよい、さらに、照射するエネルギ一線は、照射領
域を活性化させることができる強度を有し、かつ所望の
配線幅以下に照射領域を絞ることができる範囲で、光、
原子、分子、ラジカル及びイオン等から選べばよい、ま
た、基板はシリコン集積回路以外の化合物集積回路等で
もよい。In this example, dimethylaluminum hydride was used as the raw material gas for wiring, but triisobutylaluminum or the like may also be used. In addition, although aluminum is used as the wiring material, tungsten or the like which can be formed using WF6 etc. may also be used.Furthermore, the irradiated energy line has an intensity that can activate the irradiation area and is less than or equal to the desired wiring width. Light, within the range where the irradiation area can be narrowed down to
The substrate may be selected from atoms, molecules, radicals, ions, etc., and the substrate may be a compound integrated circuit or the like other than a silicon integrated circuit.
本実施例では、配線を直接描画する方法について述べた
がマスクを用いたプロジェクションによる配線の形成方
法でも本発明を実施できることはいうまでもない。In this embodiment, a method of directly drawing wiring has been described, but it goes without saying that the present invention can also be practiced by a method of forming wiring by projection using a mask.
以上説明したように本発明は、作業数や工程を減少させ
、大きいスループットで配線を形成できるので、集積回
路等に用いられる配線の製造工程と費用を低減できる効
果がある。As described above, the present invention can reduce the number of operations and processes and form wiring with a high throughput, so it has the effect of reducing the manufacturing process and cost of wiring used in integrated circuits and the like.
第1図(a)〜(c)は本発明の一実施例の主要工程を
示す断面図である。
1・・・シリコン基板、2・・・シリコン酸化膜、3・
・・活性化層、4・・・エネルギ一線、5・・・アルミ
ニウム配線。
(α)FIGS. 1(a) to 1(c) are sectional views showing the main steps of an embodiment of the present invention. 1... Silicon substrate, 2... Silicon oxide film, 3.
...Activation layer, 4... Energy line, 5... Aluminum wiring. (α)
Claims (1)
な基板の配線領域にエネルギ一線を照射して前記基板の
表面を前記堆積に関し活性化し、その後、気相成長法に
よって、前記基板に配線用薄膜を堆積することを特徴と
する配線の形成方法。The surface of the substrate is activated for the deposition by irradiating a line of energy onto the wiring area of a substrate which is inactive for the deposition of a thin film for wiring using a vapor deposition method, and then the wiring is deposited on the substrate by a vapor deposition method. 1. A method for forming wiring, characterized by depositing a thin film for use in wiring.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18633690A JPH0472730A (en) | 1990-07-13 | 1990-07-13 | Wiring formation process |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18633690A JPH0472730A (en) | 1990-07-13 | 1990-07-13 | Wiring formation process |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0472730A true JPH0472730A (en) | 1992-03-06 |
Family
ID=16186568
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18633690A Pending JPH0472730A (en) | 1990-07-13 | 1990-07-13 | Wiring formation process |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0472730A (en) |
-
1990
- 1990-07-13 JP JP18633690A patent/JPH0472730A/en active Pending
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