JPH0456413A - Phase difference signal generator - Google Patents

Abstract

PURPOSE:To eliminate a phase error by providing a phase comparator comparing the phases of two input signals and a switching means changing over the two signals at every prescribed period and inputting the inverted signal at its 1st input terminal only to the generator. CONSTITUTION:A reference signal 5 is inputted to the terminal A of a switching circuit 4 and the output of a VCO 3 is inputted to a terminal B, and the output of the VCO 3 is synchronized with the reference signal at the phase difference of 90 deg.+theta. When SWs 1-3 are switched to input the reference signal to the terminal B and to input the inverted output of the VCO 3, the reference signal at the terminal B of the phase comparator 1 is synchronized with the signal of the VCO 3 at the terminal A at the phase difference of 90 deg.+theta. That is, the output of the VCO 3 is synchronized with the reference signal at a phase difference of 90 deg.-theta. A phase error other than a substantial input phase error is reduced and a phase difference signal with high accuracy is obtained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a phase difference signal generator that compares the phases of two input signals and generates a signal having a phase difference with respect to a reference signal. .

[Conventional technology]

Conventionally, in a color encoder circuit for television signals, for example, in the case of the NTSC system, the B-Y signal is output as O.

Since the R-Y signal is modulated at 90°, the 0°90
A carrier signal (3.58 MHz) with a phase of 3.5° is required.

Conventionally, carrier signals with phases of 0° and 90° are digitally converted into high-frequency clock signals by 1/1, as shown in Figure 4.
It is formed from a signal counted down to N. Figure 4 (
4(a) is a block diagram showing an example of forming a carrier signal with a phase of 90°, and FIG. 4(b) is a timing chart showing the operation of the circuit of FIG. 4(a).

In FIG. 4(a), 5 is a counter that counts down the clock CK to 1-/N. Here, N is selected so that the frequency of the counter output is (3.58 MHzX 2 ). Reference numerals 6 and 7 are D-flip-flops (FF) which are triggered by the positive output (a) and negative output (b) of the counter 5, respectively. A carrier signal of O', 90° phase is obtained from these DFFs 6.7.

The timing of each signal is as shown in FIG. 4(b).

Another method for forming carrier signals with 0° and 90° phases is a phase-locked oscillator. FIG. 5 shows a block diagram of the phase-locked oscillator. In Figure 5, 1 is the phase of the reference signal (c) and the 3 outputs of the VCO (voltage controlled oscillator).
. 2 is a low-pass filter (LPF) that smoothes the phase error output of the phase comparator 1. VOC3 changes the output frequency according to the phase error voltage (ne) smoothed by LPF 2. VOC3 output ■. To make the phase of 90° with respect to the reference signal, the phase comparator 1
It is sufficient to design the device to output a phase error O with a phase difference of °.

FIG. 6 shows a timing chart of an example where the phase error is O at a 90° phase. Output ■ for the phase of the reference signal (c). The state of 9 phase error (:) is when the phase is 90°, and if the output of the phase comparator 1 is smoothed by the LPF 2, the phase error voltage (E) becomes an intermediate level.

At this time, the phase error voltage (ne) is at a level of (,t)-1, and the VCO 3 is oscillating at the same frequency as the reference signal.

The output of VCO3 is ■. When the phase advances with respect to the reference signal (C) as shown in ', the output of phase comparator 1 becomes as shown in (:)', and the level of the phase error voltage (E) rises as shown in (*)-2. , the oscillation frequency of the VCO 3 is increased, and the phase of the output of the VCO 3 is controlled to be 90° with respect to the reference signal (c). The output of VCO3 is ■. '', the above operation is reversed and the phase error voltage (N) decreases to -3, the oscillation frequency of VCO3 becomes low (and the reference signal (C) decreases).
The output of the VCO 3 is controlled to have a phase difference of 90°.

[Problem to be solved by the invention]

However, in a color signal encoder, even if the phase difference of the input carrier changes by ±1° to 2″ from 90°, a hue shift occurs, so the conventional example described above has the following problem.

In the countdown method, (1) Since the carrier frequency is 3.58 MHz (NTSC method), the clock must be made to have a high frequency in order to create a stable and accurate phase difference of <90°.

(2) Two carrier signal inputs to the color encoder are required.

In a phase-locked oscillator, (3) Ideally, it locks with a phase difference of 90°, but due to variations in the elements that make up the circuit, a phase error other than the input signal phase error occurs, causing an error in the synchronized phase. It will happen.

An object of the present invention is to provide a phase difference signal generator that solves the above problems.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a first input terminal and a second input terminal.
a phase comparator that compares the phase between two input signals input to the input terminal of the input terminal; and a phase comparator that compares the phase between two input signals input to the input terminal of The apparatus is characterized in that the apparatus further includes a switch means for inverting and inputting only one of the two input signals to the first input terminal.

[For production]

According to the present invention, the above configuration makes it possible to eliminate the phase error caused by variations in the elements of the circuit other than the phase error of the input signal itself.

〔Example〕

FIG. 1 is a block diagram that best represents the features of the present invention. 1 is a phase comparator (PD) that detects the phase difference between the signals input to the A terminal and B terminal, and 2 is a low-pass filter (LPF) that smoothes the phase error voltage output from phase comparator 1.
, 3 is a voltage controlled oscillator (VCO) that changes the oscillation frequency according to the phase error voltage smoothed by the LPF, and 4 is a voltage controlled oscillator (VCO) that changes the oscillation frequency according to the phase error voltage smoothed by the LPF. A switch circuit for switching,
two switches SWI, SW2. It has SW3 and an inverter 4a (the operation will be described later).

FIG. 2 shows a timing chart showing the operation of the present invention. In Figure 2, in (1) and (2), the reference signal is input to the A terminal, the output of VCO3 is input to the B terminal (SW1 to 3 are as shown in Figure 1), and the circuit elements This shows that the output of the VCO 3 is synchronized with the reference signal at a phase of 90°+θ due to variations or other reasons. From this state, switch each SW1 to SW3 of the switch circuit 4 and
When the reference signal is input to the terminal and the inverted signal of VCO3 is input to the A terminal, the phase comparator 1 will set the B terminal to 90°+ with respect to the A terminal.
Since the synchronization is performed at θ, the reference signal is synchronized at 90°+θ with respect to the inverted signal of the output of the VCO 3. If this is shown in terms of the phase relationship of the VCO and the reference signal,
The CO output is synchronized at 90°-θ with respect to the reference signal ((3), (4), (5) in Fig. 2).

In other words, the above-mentioned switch operation changes the synchronous phase force to 90±θ every time the switch is switched.

FIG. 3 shows the phase of the output of the VCO 3 with respect to the reference signal when the input signal to the phase comparator 1 is switched by the switching signal swp. In FIG. 3, when the input signals to the A terminal 3 and B terminal are switched in the above-described operation by the signal swp in (i),
PDI -LPF2-VCO3→PD in Figure 1
Figure 3 (
As shown in ii), the phase of the output of the VCO 3 alternately changes between 90°+θ and 90°−θ with respect to the phase of the reference signal.

Here, by setting the switching signal SwP to a constant period and increasing the time constant of the feedback loop, the synchronization phase of the output of the VCO 3 with respect to the reference signal is set to 90° +
It can be stabilized at the average value of θ and 90°−θ, that is, 90″′.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to reduce phase errors other than the original phase error between input signals caused by variations in circuit elements, etc., and obtain a highly accurate phase difference signal.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a timing chart showing the operation of the embodiment, Fig. 3 is a signal waveform diagram showing the operating state of the embodiment, and Fig. 4 (a). ) is a block diagram showing a conventional example, Fig. 4(b)
5 is a block diagram showing another conventional example, and FIG. 6 is a timing chart showing the operation of the circuit shown in FIG. 5. 5...Counter, 6...D type flip-flop, 7...D type flip-flop. 1... Phase comparator (PD), 2... Low pass filter (LPF), 3... Voltage controlled oscillator (VCO), 4... Switch (SW), '-L-'- Fig. 4

Claims (1)

[Claims] 1) 2 input to the first input terminal and the second input terminal
a phase comparator that compares phases between two input signals; a phase comparator that switches the two input signals to the first input terminal and the second input terminal at regular intervals; and switch means for inverting and inputting only one of the two input signals.