JP2000036965A - Reference signal generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the inexpensive reference signal generating circuit capable of saving an installation space that stably generates plural reference signals from plural kinds of burst signals. SOLUTION: The generating circuit is provided with 1st and 2nd voltage controlled oscillators 11, 15 whose oscillated frequency is changed in response to a signal given to a control terminal, a 1st frequency divider 14 that applies 1/j frequency division to an output of the 1st oscillator 11, a 2nd frequency divider 16 that applies 1/k frequency division to an output of the 2nd oscillator 15, a 1st phase comparator 17a that compares phases of output signals of the 1st and 2nd frequency dividers 14, 16, a 1st low pass filter 17b that smoothes an output of the 1st phase comparator 17a and feeds back the smoothed signal to a control terminal of the 2nd oscillator 15, a 2nd phase comparator 19a that compares a phase of an output signal of the 2nd oscillator 15 with a phase of a burst signal, and a 2nd low pass filter 19b that smoothes an output of the 2nd phase comparator 19a and feeds back the smoothed signal to a control terminal of the 1st voltage controlled oscillator 11, and a desired reference frequency signal is obtained from an output of the 2nd voltage controlled oscillator 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference signal generating circuit for obtaining a reference signal synchronized with an input burst signal, and more particularly to a plurality of reference signals having different frequencies corresponding to a plurality of television systems, that is, color demodulation. And a circuit capable of generating a reference subcarrier for use.

[0002]

2. Description of the Related Art As a plurality of television systems, NTS is used.
C, PAL and SECAM are well known,
In particular, the NTSC system and the PAL system are widely used in the world. Further, there are a PAL-N system and a PAL-M system which are separate from the PAL system. Four systems, NTSC, PA
The frequency of the reference subcarrier used for LN, PAL-M, and PAL is 3.579545 MH, respectively.
z, 3.582056 MHz, 3.575611 MH
z, 4.433619 MHz.

As a conventional reference carrier generating circuit, an APC using a PLL (phase control loop) as shown in FIG.
(Automatic phase control) type circuits are widely used.

In FIG. 8, a voltage controlled oscillator (VCX)
O) 1 outputs an oscillation output signal of substantially determined stable frequency f _{re f} by externally attached crystal oscillator 2 of the resonance frequency (e.g. 3.58 MHz). In the following description, the oscillation output signal of the frequency _fref is simply referred to as the oscillation output signal f.
Sometimes referred to as _ref . Similarly, when there is no need to discriminate the relationship between other signal names and their frequencies, any expression is appropriately used.

The burst gate 3 has a chroma signal input Cin
From the burst signal f _SC . Oscillation output signal f _ref
And the burst signal f _SC are input to the phase comparator 4a of the APC circuit 4, and the phase comparison output signal Δf _{SC of} both signals is output from the phase comparator 4a. The phase comparison output signal Δf _SC is smoothed by the low-pass filter (LPF) 4b, and then fed back to the control terminal of the voltage controlled oscillator 1.

The voltage controlled oscillator 1 is controlled by the signal voltage fed back. As a result, the oscillation output signal f _ref of the voltage controlled oscillator 1 is controlled to have the same frequency and the same phase as the burst signal f _SC . Thus, a continuous oscillation signal f _ref having the same stability as the burst signal f _SC is obtained as the reference sub-carrier signal f _CW .

The APC reference carrier generation circuit as described above does not use a coil or a capacitor, and therefore has excellent mechanical stability and stability against temperature changes and is suitable for integration into an integrated circuit. The oscillation output signal from the reference carrier generation circuit using quartz has a very small free-run frequency variation, and the frequency variable range by the voltage control terminal is about ± 500 Hz. Therefore, when the chroma signal is input, a continuous oscillation signal having the same frequency and the same phase as the burst signal is obtained instantaneously.

[0008]

However, since the frequency variable range is narrow as described above, a plurality of crystal oscillators corresponding to each frequency are required to generate a plurality of reference carriers of different frequencies. Become.

On the other hand, when a plurality of reference carriers having different frequencies are generated using a voltage controlled oscillator (for example, an RC oscillator) having a wide variable range, an oscillation signal having the same frequency and the same phase as the burst signal is obtained from the free-run frequency. Is obtained, that is, the time until the APC is locked becomes longer. Also, a phenomenon called side lock may occur in which locking is performed at a frequency that is separated by a horizontal frequency near the target oscillation frequency.

In order to avoid this phenomenon, it is necessary to suppress the variation of the oscillation frequency and narrow the frequency variable range, but it is difficult to make it compatible with the generation of a plurality of reference carriers having different frequencies. Further, it is difficult to form an RC oscillator into an integrated circuit. This is because, when an integrated circuit is formed, variations in the resistance R and the capacitor C increase.

In order to generate a plurality of reference carrier waves having different frequencies corresponding to a plurality of television systems as described above, a plurality of types of external crystal oscillators are prepared according to the respective frequencies and are used by switching. The technology is described, for example, in Japanese Patent Publication No. Sho 63-28521.

Further, if the pass band of the low-pass filter 4b is narrowed in the APC circuit using the PLL, there is a problem that the time until synchronization becomes longer and the stability is deteriorated. Japanese Patent Application Laid-Open No. 63-82084 discloses a conventional example in which the accuracy of the oscillation frequency is increased while the stability of the low-pass filter is widened to increase the stability. In this conventional example, a crystal oscillator is provided in each of the two voltage-controlled oscillation circuits to form a double-loop PLL, thereby improving the stability of the oscillation frequency.

However, such a conventional technique has a problem that a circuit is complicated, a circuit space is increased, and a cost is increased. In particular, it has been strongly desired to solve these points especially in equipment that is strictly required for cost reduction, miniaturization, and the like.

In view of the above-mentioned conventional problems, the present invention selectively saves a plurality of reference signals from a plurality of burst signals having different frequencies with a relatively simple circuit configuration while saving space and reducing costs. It is another object of the present invention to provide a reference signal generating circuit capable of generating signals stably.

[0015]

To solve this problem, a reference signal generating circuit according to a first configuration of the present invention has a control terminal, and an oscillation frequency of an output signal according to a signal applied to the control terminal. Are changed using first and second voltage controlled oscillators. Further, in addition to the above components, a first frequency divider for dividing the output signal of the first voltage controlled oscillator by j and a second frequency divider for dividing the output signal of the second voltage controlled oscillator by k A frequency divider, a first phase comparator for comparing phases of output signals of the first and second frequency dividers, and control of a second voltage-controlled oscillator by smoothing output signals of the first phase comparator 1st input to the terminal to form a feedback control path
A low-pass filter, a second phase comparator for comparing the phase of the output signal of the second voltage-controlled oscillator with the burst signal, and a first voltage for smoothing the output signal of the second phase comparator. A second low-pass filter that inputs a control terminal of the control oscillator to form a feedback control path. Here, the continuous reference frequency signal having the desired frequency is obtained from the output signal of the second voltage controlled oscillator.

Preferably, the feedback control from the second phase comparator to the first voltage controlled oscillator is enabled only during a period in which the burst signal is valid, and the first phase is controlled only in a period other than the period in which the burst signal is valid. Means for enabling feedback control from the comparator to the second voltage controlled oscillator is further provided. This stabilizes the control by the two feedback loops.

Further, the feedback control from the first phase comparator to the second voltage controlled oscillator is made effective only for a predetermined period, and a duty ratio which is a ratio of a length of the predetermined period to a period other than the predetermined period is variable. Is preferable. Until the PLL is locked, the predetermined period is sufficiently long (duty ratio is large) to widen the frequency variable range of the voltage-controlled oscillator, so that the desired frequency can be obtained quickly and after the desired frequency has been reached. Frequency fluctuation can be suppressed by shortening the predetermined period.

It is preferable that the apparatus further includes a burst gate circuit for extracting a burst signal from the chroma signal. A control signal applied to the burst gate circuit;
The same control signal can be used as the control signal for validating the feedback control from the second phase comparator to the first voltage controlled oscillator only during a period in which the burst signal is valid.

A frequency multiplier for multiplying the frequency of the output signal of the first voltage controlled oscillator by α, and a third frequency divider for multiplying the frequency of the output signal of the second voltage controlled oscillator by 1 / α; The output signal of the first voltage controlled oscillator is passed through the multiplier to the first
, And the output signal of the second voltage controlled oscillator is preferably input to the second phase comparator via the multiplier and output as the reference signal. By using the multiplier, an inexpensive and general-purpose relatively low-frequency crystal oscillator can be used.

As a specific design numerical example, the value of α is set to 4, and the center oscillation frequency of the first voltage controlled oscillator is set to about 4.4.
When a burst signal of 3.575611 MHz (PAL-M system) is input, the values of j and k, which are frequency division numbers of the first and second frequency dividers, are set to 186 and 150.
, And when a 3.579545 MHz (NTSC system) burst signal is input, the values of j and k are set to 218.
And 176, and 3.582056 MHz (PAL
J and k when a burst signal of (−N method) is input.
Is preferably set to 177 and 143. Further, when a 4.433619 MHz burst signal is input, if the output signal of the first voltage controlled oscillator is directly input to the second phase comparator, it operates as a conventional APC circuit.

In the case where a multiplier for increasing the frequency of the output signal of the first voltage controlled oscillator by α is not used, the center oscillation frequency of the first voltage controlled oscillator is set to about 17.7 MHz.
When a 756611 MHz burst signal is input, the values of j and k, which are the frequency division numbers of the first and second frequency dividers, are set to 1
86 and 150. When a 3.579545 MHz burst signal is input, the values of j and k are set to 218 and 176. When a 3.582056 MHz burst signal is input, the values of j and k are set. 177 and 14
It is preferable to set both j and k to 200 when a burst signal of 4.433619 MHz is input.

A reference signal generating circuit according to a second configuration of the present invention includes a control terminal, and includes first and second voltage controlled oscillators in which the oscillation frequency of an output signal changes according to a signal applied to the control terminal. It is configured using. In addition to the above components, a phase comparator for comparing the phase of the output signal of the second voltage controlled oscillator with the burst signal, and the second voltage controlled oscillator for smoothing the output signal of the phase comparator , A first counter for measuring a first time corresponding to m times the output signal period of the first voltage-controlled oscillator, and an output signal of the second voltage-controlled oscillator A second counter for counting a second time corresponding to n times the cycle, and a second counter for counting a third time longer than the second time, which is p times the output signal cycle of the second voltage controlled oscillator. Counter 3 and the frequency of the second voltage-controlled oscillator is decreased if both the second and third times are shorter than the first time, and the second if the second and third times are both longer than the first time. The frequency of the voltage controlled oscillator of the second and third
And control means for applying a voltage for maintaining the frequency of the second voltage-controlled oscillator to the control terminal of the second voltage-controlled oscillator when the first time is present during the time.
The reference signal is obtained from an output signal of the second voltage controlled oscillator. In this configuration, as in the first configuration, a crystal oscillator (first voltage controlled oscillator) having excellent stability but having a narrow frequency variable range and a second voltage controlled oscillator having a relatively wide variable range are used in combination. ing. In this way, digital control using a counter or the like is further combined to correspond to burst signals of a plurality of frequencies.

Preferably, the first counter outputs the first signal when the output signal of the first voltage controlled oscillator is input and counts m cycles, and the second counter outputs the second signal.
When the output signal of the voltage-controlled oscillator is input and the number of pulses is counted, a second signal is output. The third counter receives the output signal of the second voltage-controlled oscillator and outputs p greater than n. When the number of pulses has been counted, a third signal is output, the second and third counters are reset by a signal slightly delayed from the first signal, and the control means controls the second and the third signals by the first signal. The first that latches the third signal
And a second latch, and a decoder for superimposing a signal obtained by decoding the output signals of the first and second latches on the input signal of the low-pass filter.

Also in this configuration, a burst gate circuit for extracting a burst signal from the chroma signal input is further provided, and the feedback control from the phase comparator to the second voltage controlled oscillator is effectively performed only during a period when the burst signal is valid. It is preferable to provide a means for performing this.

In order to narrow the oscillation frequency range of the reference signal output, it is preferable to further include a frequency divider for multiplying the frequency of the output signal of the second voltage controlled oscillator by 1 / α.
In this case, the output signal of the second voltage controlled oscillator is input to the phase comparator via the frequency divider and is output as the reference signal output.

That is, the frequency f _CW of the reference signal output is f
_CW = f _A / α (where f _A is the frequency of the output signal of the second voltage controlled oscillator), and constants, m, and f _A and f _REF are obtained.
The expression that the values of n and p should satisfy is n / f _A <m / f _ref <p / f _A. Here, by transforming this equation, (1 / α) (n / m) f _ref <f _CW <(1 / α) (p /
m) f _ref . In this equation, the amount of change in frequency when the n and p is changed by 1 is a _{f re} f / (αm). Therefore, when α is increased, the amount of change in frequency can be reduced.

As a specific example of design numerical values in the second configuration, the center oscillation frequency of the first voltage controlled oscillator is set to about 4.
Assuming that the frequency is 43 MHz and the value of α is 4, 3.575611M
Hz burst signal is input, the second and third
The values of n and p, which are the count numbers of
And 6603, and when a 3.579545 MHz burst signal is input, the values of m and p are set to 6617.
And 6610, and it is preferable to set the values of m and p to 6622 and 6616 when a 3.582056 MHz burst signal is input. Further 4.433
When a 619 MHz burst signal is input, the output signal of the first voltage controlled oscillator may be directly input to the phase comparator.

[0028]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram of a reference carrier generation circuit according to a first embodiment of the present invention. In FIG. 1, a voltage controlled oscillator (VCXO) 11 outputs an oscillation output signal f _ref having a stable frequency substantially determined by the resonance frequency of an externally mounted crystal oscillator 12.
As an example, a 4.433619 MHz crystal oscillator 12
Is used.

The oscillation output signal f _ref is converted into a signal having a frequency four times higher by the multiplier 13, and then the first frequency divider (CD 1) 1
At 4, the frequency is j-divided. Therefore, the frequency of the output signal of the first frequency divider 14 is 4f _ref / j.

The reference carrier generation circuit of the present embodiment has a first
A second voltage controlled oscillator (CVCO) 15 is provided separately from the voltage controlled oscillator (VCXO) 11. This oscillator 15 does not use a crystal oscillator, and has a voltage control type RC having a frequency variable range wider than that of the first voltage control oscillator 11.
An oscillator, for example, a multivibrator circuit. The output f _{A of the} oscillator 15 is supplied to the second frequency divider (C
D2) The frequency is divided by k at 16. Therefore, the frequency of the output signal of the second frequency divider 16 is f _A / k.

The output signal 4f _ref / j of the first frequency divider 14 and the output signal f _A / k of the second frequency divider 16 are input to a first phase comparator 17a constituting a first APC circuit 17. And
An output signal obtained by comparing the phases of the two signals is output from the phase comparator 17a. This output signal is supplied to first and second
, And is fed back to the control terminal of the second voltage controlled oscillator 15 after being smoothed by the first low-pass filter (LPF) 17b.

The second voltage controlled oscillator 15 is controlled by the signal voltage fed back. As a result, the oscillation output signal f _A of the second voltage controlled oscillator 15 becomes
Two signals 4f input to the first phase comparator 17a
_ref / j and f _A / k are controlled so as to have the same frequency and the same phase. That is, with respect to frequency,

[0034]

## EQU1 ## The relationship of 4f _ref / j = f _A / k holds, and if j = k is set,

[0035]

## EQU2 ## From 4f _ref = f _A , it can be seen that a signal f _A having a frequency four times as high as f _ref is obtained as an oscillation output signal of the second voltage controlled oscillator 15. Then, by adjusting the values of j and k, an oscillation output signal of a desired frequency can be obtained from the second voltage controlled oscillator 15. This will be described in detail later.

In practice, as shown in FIG. 1, the output signal f _A of the second voltage controlled oscillator 15 is
After being divided into a frequency of / 4, the reference signal f _CW (= f _A /
4) is output. Also, this signal f _A / 4 is
Is input to the second phase comparator 19a constituting the APC circuit 19 of FIG.

On the other hand, the burst signal f _SC is taken out from the chroma signal input Cin by the burst gate circuit 20.
The signal is input to the second phase comparator 19a. Phase comparator 19
“a” compares the phases of the two input signals f _A / 4 and f _SC and outputs a phase comparison output signal Δf _SC . This phase comparison output signal Δf _SC is supplied to a third switch SW3 described later.
The signal is smoothed by a second low-pass filter (LPF) 19b, and then fed back to the control terminal of the first voltage-controlled oscillator 11.

If there is a phase shift between the burst signal f _SC and the signal f _A / 4, the phase comparator 1
9a outputs an output signal Δf _SC , which is further smoothed by a low-pass filter 19b and fed back as a control voltage to the control terminal of the first voltage controlled oscillator 11, so that the oscillation output signal f _ref is corrected first. . As a result, the first
APC circuit 17 of the second voltage controlled oscillator 15
Oscillation output f _A is corrected. In this way, the signal f _A / 4 adjusted to have the same frequency and the same phase as the burst signal f _SC by the double feedback circuit including the first and second APC circuits 17 and 19 is used as the reference sub-circuit. Obtained as carrier signal f _CW .

FIG. 2 shows a specific example of the APC circuit. First
Of the APC circuit 19 of FIG. Second AP
The C circuit 17 can be configured by a similar circuit. Although a specific circuit of the switch SW3 is omitted, it can be easily realized by inserting a switching circuit using a transistor or the like between the phase comparator 19a and the low-pass filter 19b.

The phase comparator 19a is composed of a double balanced connection differential amplifier circuit, and includes a burst signal f _SC and a signal f _A.
A signal corresponding to the product of / 4 is output. When this signal is smoothed by the low-pass filter 19b, a positive or negative voltage signal corresponding to the phase difference between the burst signal f _SC and the signal f _A / 4 is obtained. When the phase difference is zero, the voltage signal becomes zero.

Next, the operation of the reference carrier generation circuit of the present embodiment will be described in more detail with reference to FIG. 3 showing the waveforms of the respective signals in FIGS.

FIG. 3 shows a schematic waveform of each signal when the time axis is taken from left to right. Each waveform will be described in order from the top. The top waveform Cin is an example of a chroma signal input. The waveform f _SC is a burst signal extracted by the burst gate circuit 20 from the chroma signal Cin. A waveform f _ref indicates an output signal of the first voltage controlled oscillator 11. The frequency of the signal f _ref is quadrupled by the frequency multiplier 13, and the frequency of the signal 4f _ref / j divided by the frequency divider 14 to 1 / j is drawn below. Although the output signal f _ref is a sine wave, the multiplier 1
Waveform shaping is performed by passing through the frequency divider 3 and the frequency divider 14 to form a rectangular wave. Below that, the second voltage controlled oscillator 15
The waveform of the signal f _A / k obtained by dividing the output signal f _A of FIG. FIG. 3 shows a state in which the signal f _A / k is advanced by about 60 degrees from the signal 4f _ref / j.

These two signals f _A / k and 4f _ref / j
Are obtained by the phase comparator 17a, that is, a comparison output is drawn below. This comparison output is a positive pulse having the width of the phase difference.

The lower waveform is a burst gate pulse BG
P. This signal is supplied to the burst gate 20 and the switch SW3 of the second APC circuit 19 as a control signal. The inverted signal (/ BGP) is used for controlling the first switch SW1 of the first APC circuit 17. As a result, the feedback loop including the second APC circuit 19 is made valid only during the period when the burst gate pulse BGP is at the H level, that is, during the period when the burst signal is valid.
The feedback loop including the first APC circuit 17 is valid only during the period when the burst gate pulse BGP is at the L level, that is, during a period other than the period during which the burst signal is valid. Therefore, as shown in FIG. 3, the output signal of SW1 is the logical product of the comparison output thereover and the inverted signal of BGP.

The WINDOW signal is drawn below the SW1 output signal. This signal is used in the first APC circuit 17 to control a second switch connected in series with the first switch SW1. Thereby, the first APC
The feedback loop including the circuit 17 is valid only during the period when the WINDOW signal is at the H level. Therefore, as shown in FIG. 3, the output signal of SW2 is the logical product of the output signal of SW1 and the WINDOW signal. And WIND
By making the H level period (that is, duty ratio) of the OW signal variable, the loop gain is made variable. As an example, by setting the duty ratio to 1/2 and setting the loop gain to a relatively high value until the PLL is locked, the frequency variable range of the second voltage controlled oscillator 15 can be widened, and the desired frequency can be quickly set. On the other hand, after reaching the desired frequency, the duty ratio is reduced to 1/4 and the loop gain is set to a relatively small value, whereby the frequency fluctuation can be suppressed.

The WINDOW signal is synchronized with 4f _ref / j and has a different phase and pulse width, and can be created in the process of producing the output signal 4f _ref / j of the frequency divider 14. That is, if the position from which the output of the frequency divider 14 is extracted is appropriately changed, a WINDOW signal can be obtained.

Next, a specific example will be described in which the reference carrier generation circuit according to the first embodiment of the present invention is used to handle a plurality of burst signals f _SC having different frequencies. As described above, the reference carrier generation circuit of the present embodiment can set the frequency division numbers j and k of the first and second frequency dividers 14 and 16 to a plurality of burst signal frequencies f _SC by appropriately setting them. Can respond.

The PLL loop including the first APC circuit 17 works so as to satisfy the relationship of 4f _ref / j = f _A / k shown in the equation (Equation 1). On the other hand, the reference carrier output signal f _CW is f
Equals _A / 4, because this is being controlled to be equal to the burst signal f _SC, the following equation from equations (Equation 1) and f _A / 4 = f _SC (Equation 3) is obtained.

[0049]

F _ref = (j / k) f _SC Based on this equation, the change of the output frequency f _ref of the first voltage-controlled oscillation circuit 11 for a plurality of specific burst signal frequencies f _SC . The values of j and k may be determined so as to be as small as possible within the output frequency variable range (about ± 500 Hz) of the first voltage control transmission circuit. As an example, four television systems, namely PAL-M, NTSC, P
3.575611 MH corresponding to AL-N and PAL
z, 3.579545 MHz, 3.582056MH
Table 1 shows an example in which burst signals of four kinds of frequencies of z and 4.433619 MHz are used.

[0050]

[Table 1] f _SC (MHz) jk f _ref (MHz) f _ref −4.433619 (Hz) 3.575611 186 150 4.433758 139 3.579545 218 176 4.433755 136 3.582056 177 143 4.433734 115 4.433619 200 200 4.433619 0 By appropriately setting the values of k and k, a plurality of types of reference carrier output signals fCW corresponding to burst signals of a plurality of frequencies can be obtained. However, when a 4.433619 MHz burst signal is input, the output signal f _{ref of} the first voltage controlled oscillator 11 is output.
May be directly input to the second phase comparator 19a. In this case, the second voltage controlled oscillator 15 and the first APC circuit 17 do not operate.

Here, in the circuit of FIG. 1, it is not necessary to limit the multiple of the multiplier 13 to 4, and similarly, the third frequency divider 18
Need not be limited to 1/4. Generally, if the multiple of the multiplier 13 is α and the frequency of the frequency divider 18 is β, the output frequency of the frequency multiplier 13 is α · f _{ref and} the output frequency of the frequency divider 18 is β · the f _a. Therefore, the above-mentioned relational expression (Equation 1) is replaced by the following expression (Equation 4).

[0052]

Α · f _ref / j = f _A / k Since β · f _A = f _SC , this equation and equation (4)
Gives the following equation (Equation 5).

[0053]

F _ref = (1 / αβ) (j / k) f _SC Equation (Equation 5) When α is equal to 1 / β (both are 4 in the circuit of FIG. 1), the above equation ( Equation 3) is obtained.

Here, the oscillation frequency f _A of the second voltage controlled oscillator 15 is given by f _A = (α / j) f _ref based on equation (4).
Is represented by k. Therefore, the second voltage controlled oscillator 1
5, the oscillation frequency f of the first voltage controlled oscillator 11
_In relation to _ref , one having an oscillation frequency variable range that can include the oscillation frequency determined by the combination of j, k, and α is used. In addition, it is desirable that the variable range is selected so as to satisfy the requirements even under the worst conditions, in consideration of temperature fluctuation, circuit element fluctuation, and power supply fluctuation.

The reason why the multiplier 13 and the third frequency divider 18 are used is that the general-purpose and inexpensive crystal oscillator 12 having a relatively low frequency is used.
However, when a crystal oscillator having a resonance frequency α times the burst signal frequency is used, the multiplier 13 is unnecessary.

(Embodiment 2) FIG. 4 is a block diagram of a reference carrier generation circuit according to a second embodiment of the present invention. In FIG. 4, a first voltage controlled oscillator (VCXO) 31
Outputs an oscillation output signal having a stable frequency _fref substantially determined by the resonance frequency of the externally attached crystal oscillator 32. As an example, a crystal oscillator 12 of 4.433619 MHz is used. Oscillation output signal f of voltage controlled oscillator 31
_ref is input to the first counter 33. The counter 33 counts the number of cycles of the oscillation output signal _fref and outputs a first signal. That is, m from the start of counting
When the first time corresponding to / f _ref has elapsed, the counter output is inverted from L level to H level.

A first voltage controlled oscillator (VCXO)
Apart from 31, a second voltage controlled oscillator (CVCO) 34
Is provided. The oscillator 34 is a voltage-controlled RC oscillator that does not use a crystal oscillator and has a wide frequency variable range, and is composed of, for example, a multivibrator circuit. The output f _{A of the} oscillator 34 is supplied to the second and third counters 3.
5 and 36 are input. The second counter 35 counts the number of cycles of the second oscillation output signal f _A by n and outputs a second signal. That is, when the second time corresponding to n / f _A elapses from the start of counting, the counter output is inverted from L level to H level. The third counter 36 counts p periods of the second oscillation output signal f _A and outputs a third pulse signal. That is, when the third time corresponding to p / f _A has elapsed from the start of counting, the counter output is inverted from L level to H level. Here, p is set to a value larger than n.

The second and third counters 35 and 36 are reset by a signal obtained by slightly delaying the first signal output from the first counter 33. Therefore,
If the second time n / f _A and the third time p / f _A are longer than the first time m / f _ref, neither the second nor the third signal is output (the counter output is not inverted). _A first time m / f between a second time n / f _A and a third time p / f _A
If there is a _ref , the second pulse signal is output but the third pulse signal is not output. If the second time n / f _A and the third time p / f _A are shorter than the first time m / f _ref , both the second and third signals are output.

The second pulse output from the second counter 35 is latched by the first latch 37, and the third pulse output from the third counter 36 is output by the second latch 38.
Latched. The first signal output from the first counter 33 is input to the first and second latches 37 and 38 as a latch timing signal. As a result, the second and third counters 35, 35 are generated by a signal obtained by slightly delaying the first signal by, for example, the inversion time of two gates.
Before resetting the counter 36, the counter output signal is output to the first and second latches 37 and 38 and held.

Accordingly, the first and second latches 37, 37
38, a second voltage controlled oscillator 34
Feedback control of the voltage applied to the control terminal of
The second voltage controlled oscillator 34 is set so that the first time m / f _ref is _inserted between the second time n / f _A and the third time p / f _A.
It is possible to control the output signal f _A. The decoder 39 and the current / voltage converter (V / I) 4 perform this function.
0. Details of these operations will be described later.

The output signal f _{A of} the second voltage controlled oscillator 34
Is frequency-divided by the frequency divider 41 into a quarter frequency, and is output as a reference signal f _CW (= f _A / 4). The signal f _A / 4 is used as a signal for a phase comparator 42 constituting the APC circuit 42.
is input to a.

On the other hand, a burst signal f _SC is extracted from the chroma input signal Cin by the burst gate 43 and is input to the phase comparator 42a. The phase comparator 42a compares the phases of the two input signals f _A / 4 and f _SC ,
The phase comparison output signal Δf _SC is output. This signal Δf
_SC is connected to a low-pass filter (LP) through a switch SW.
F) After being smoothed by 42b, the second voltage-controlled oscillator 3
4 is fed back to the control terminal. Therefore, the second voltage controlled oscillator 34 is PLL-controlled so that the phase of the signal f _A / 4 equal to the reference subcarrier output signal f _CW is equal to the phase of the burst signal f _SC .

The above-mentioned decoder 39 and voltage / current converter 40 are included in the feedback loop, and therefore, the second time n / f _A measured by the second counter and the third counter are used. The first time between the third time p / f _A
The APC circuit 42 is also used as a part of a feedback loop for controlling the second voltage-controlled oscillator 34 so that the first time m / f _ref counted by the counter is input. That is, as shown in FIG. 4, the output signal of the decoder 39 is input to the voltage / current converter 40, and the output signal is A
It is superimposed on the input signal of the low-pass filter of the PC circuit 42.

FIG. 5 shows the first and second voltage controlled oscillators 3.
1, 34, the oscillation output signals f _ref , f _A , the output signals of the first, second and third counters 33, 35, 36, the output signals of the first and second latches 37, 38, and the decoder 39
3 shows waveform examples of outputs A and B of FIG. In this figure, the first time m / f is between the second time n / f _A and the third time p / f _A.
The case where a _ref is included is shown.

As can be seen from FIG. 5, the second time n / f
_{When A} elapses, the second counter output is inverted from L level to H level. When the first time m / f _ref has elapsed, the output of the first counter becomes H level, and at this timing, the output signal of the second counter is latched in the first latch. The second counter is reset slightly later, and the first counter itself is reset. Third
The counter counts up and the output is inverted from the L level to the H level when the third time p / f _A has elapsed as indicated by the broken line in FIG. Since the third counter is reset at the timing when the second counter and the first counter are reset, the output of the third counter is not inverted and remains at the L level. Therefore, the output signal of the second latch remains at the L level.

However, for example, the frequency f _A becomes higher than the desired frequency, and the third time p / f _A becomes the first time m / f
If the time elapses before _ref , as described above, the outputs of both the second and third counters are inverted, and both the first and second latch outputs become H level. Conversely, when the frequency f _A becomes lower than the desired frequency and the second time n / f _A elapses later than the first time m / f _ref , the outputs of both the second and third counters are changed. While the L level remains, both the first and second latch outputs go to the L level.

The decoder 39 outputs a voltage / current converter (V / I) based on the output signals of the first latch and the second latch.
40, two decoder outputs A and B as shown in Table 2 are given.

[0068]

[Table 2] First latch output HHL Second latch output HLL Decoder output AHHL Decoder output BLHH The voltage / current converter 40 is composed of, for example, a circuit as shown in FIG. When the decoder outputs A and B are input, current outputs as shown in Table 3 corresponding to the combinations are obtained.

[0069]

Table 3 Decoder output A HH L Decoder output B L H H Current output Inflow Zero outflow In Table 3, the inflow current output is a current output in the direction of decreasing the frequency f _A , and the outflow current output increases the frequency f _A. Direction current output.

In the example of FIG. 5, the output of the first latch is at the H level, the output of the second latch is at the L level, and both the decoder outputs A and B are at the H level. In this case, the frequency f _A is within an appropriate range, and the output of the voltage / current converter 40 becomes zero. When both the first and second latch outputs are at the H level, the frequency f _A becomes higher than the upper limit frequency,
Since the decoder output A becomes H level and the decoder output B becomes L level, the output of the voltage / current converter 40 becomes the frequency f _A.
In the direction of decreasing the inflow current. Conversely, when the first and second latch outputs are both at L level, the frequency f _A is lower than the lower limit frequency, the decoder output A is at L level, and the decoder output B is at H level. 4
The output of 0 is the direction of the current output to increase the frequency f _A.

Accordingly, by appropriately setting the count number m of the first counter 33, the count number n of the second counter 35, and the count number p of the third counter 36, the frequency f _A is controlled within a desired range. be able to. For example m, n, the value of p by setting as shown in Table 4, with respect to three different burst frequency f _SC (MHz), and substantially centered on the respective frequencies f _SC, the frequency f
It is possible to set a preferable control range f _{OSC1 to} f _OSC2 (MHz) of _A / 4. f _OSC1 is the first voltage controlled oscillator 31
Is determined using the values of m and p, with the output frequency f _ref of 4.433619 MHz as the value. f _OSC2 is similarly obtained using the values of m and n.

[0072]

Table 4 in the _{f SC m n p f OSC1 f} OSC2 3.575611 2048 6610 6603 3.573631 3.577420 3.579545 2048 6617 6610 3.577420 3.581208 3.582056 2048 6622 6616 3.580667 3.583914 Thus, the output signal f _A of the second voltage controlled oscillator 34 1 After the frequency f _A / 4 divided into / 4 is controlled within the range of f _{OSC1 to} f _OSC2 , the frequency and the phase of the frequency f _A / 4 are adjusted to the frequency and the phase of the burst signal signal f _SC by the APC circuit. , _Is output as a reference subcarrier signal f _CW .

In this embodiment also, 4.44331
When a 9 MHz burst signal (PAL system) is input, the output signal f _ref of the first voltage controlled oscillator 31 is set to A
It can be directly input to the phase comparator 42a of the PC circuit 42. Actually, as shown in FIG. 7, three changeover switches SW2 to SW4 and two bypass lines 51 and 52 are added to the circuit of FIG. 4, and when a 4.433619 MHz burst signal is input, the switches are switched. SW2 to SW4 can be switched to the side opposite to the state of FIG.

As a result, the output signal f _ref of the first voltage controlled oscillator 31 is directly input to the phase comparator 42a through the bypass line 51 and the switch AW2, and the output of the low-pass filter 42b is connected to the SW 3 and the bypass line 52. , And is fed back to the control terminal of the first voltage controlled oscillator 31. At this time, the reference voltage source connected to the control terminal of the voltage controlled oscillator 31 is disconnected by SW4.

In the above description of the embodiment, the values of j and k of the frequency divider or the values of m, n and p of the counter are:
Switching can be performed using a normal method. For example,
A circuit for supplying an output corresponding to each combination of values is incorporated, and a switch is automatically or manually switched according to a required frequency. For automatic switching,
The switch is operated by a signal indicating the frequency of the color signal in the input television signal. A signal indicating such a frequency can be created using, for example, the output of a color killer circuit that detects the presence of a color signal corresponding to each color system. That is, the frequency of the color signal can be specified by the combination of the outputs from the color killer circuits corresponding to the respective color systems.

[0076]

According to the present invention, a plurality of reference signals can be selectively and stably generated from a plurality of burst signals having different frequencies with a relatively simple circuit configuration while saving space and reducing costs. And a reference signal generation circuit capable of performing the above.

[Brief description of the drawings]

FIG. 1 is a block diagram of a reference carrier generation circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of an APC circuit in the reference carrier generation circuit of FIG.

FIG. 3 is a diagram showing waveforms of respective signals in the reference carrier generation circuit of FIG. 1;

FIG. 4 is a block diagram of a reference carrier generation circuit according to a second embodiment of the present invention.

FIG. 5 is a diagram showing waveforms of respective signals in the reference carrier generation circuit of FIG. 4;

6 is a circuit diagram showing a specific example of a voltage / current converter in the reference carrier generation circuit of FIG.

FIG. 7 is a block diagram showing a modified example of the reference carrier generation circuit of FIG. 4;

FIG. 8 is a block diagram showing a configuration of a conventional reference carrier generation circuit.

[Explanation of symbols]

 11, 31 First voltage controlled oscillator 12, 32 Crystal oscillator 13 Multiplier 14, 16, 18, 41 Divider 15, 34 Second voltage controlled oscillator 17, 19, 42 APC circuit 17a, 19a, 42a Phase Comparator 17b, 19b, 42b Low-pass filter 20, 43 Burst gate 33, 35, 36 Counter 37, 38 Latch 39 Decoder 40 Voltage / current converter

Claims (15)

[Claims] 1. A reference signal generating circuit for obtaining a reference signal synchronized with an input burst signal, comprising: a control terminal, wherein a first oscillation frequency of an output signal changes according to a signal applied to the control terminal. And a second voltage-controlled oscillator; and a first voltage-divided output signal of the first voltage-controlled oscillator divided by j.
And a second divider for dividing the output signal of the second voltage controlled oscillator by k
A first phase comparator for comparing phases of output signals of the first and second frequency dividers; and a signal obtained by smoothing an output signal of the first phase comparator. A first low-pass filter that is input to a control terminal of the second voltage-controlled oscillator to form a feedback control path; and a second that compares a phase between the output signal of the second voltage-controlled oscillator and the burst signal. A phase comparator; and a second low-pass filter that inputs a signal obtained by smoothing an output signal of the second phase comparator to a control terminal of the first voltage controlled oscillator to form a feedback control path. A reference signal generation circuit that obtains the reference signal from an output signal of the second voltage controlled oscillator. 2. An oscillation frequency of the second voltage controlled oscillator is wider than a value obtained by multiplying an oscillation frequency of the first voltage controlled oscillator by k / j which is a ratio of the k value and the j value. 2. The reference signal generation circuit according to claim 1, wherein the reference signal generation circuit oscillates. 3. The feedback control from the second phase comparator to the first voltage controlled oscillator is made effective only during a period in which the burst signal is effective, and the second phase comparator outputs the second voltage controlled oscillator from the second phase comparator. 2. The reference signal generating circuit according to claim 1, further comprising means for validating feedback control to the voltage controlled oscillator only during a period other than a period during which the burst signal is valid. 4. A duty ratio which is a ratio of a length of the predetermined period to a period other than the predetermined period, wherein feedback control from the first phase comparator to the second voltage controlled oscillator is enabled only for a predetermined period. 2. The reference signal generating circuit according to claim 1, wherein 5. The reference frequency signal generating circuit according to claim 1, further comprising a burst gate circuit for extracting said burst signal from a chroma signal. 6. A multiplier for increasing the frequency of an output signal of the first voltage controlled oscillator by α, a third frequency divider for increasing the frequency of an output signal of the second voltage controlled oscillator by 1 / α. The output signal of the first voltage controlled oscillator is input to the first frequency divider via the frequency multiplier, and the output signal of the second voltage controlled oscillator is applied to the third frequency divider. 2. The reference signal generation circuit according to claim 1, wherein the reference signal is input to the second phase comparator via the input terminal and an output signal of the second voltage controlled oscillator is output as the reference signal. 7. An oscillation frequency of the second voltage controlled oscillator is obtained by multiplying a value obtained by multiplying the oscillation frequency of the first voltage controlled oscillator by α by k / j which is a ratio between the k value and the j value. 2. The reference signal generation circuit according to claim 1, wherein the reference signal generation circuit oscillates in a range wider than the value. 8. The value of α is 4, the center oscillation frequency of the first voltage controlled oscillator is about 4.43 MHz,
When a 3.575611 MHz burst signal is input, j and k are the division numbers of the first and second frequency dividers.
Are set to 186 and 150 and 3.579545M
When a burst signal of Hz is input, the values of j and k are set to 218 and 176, and 3.582056 MHz.
When a burst signal of z is input, the values of j and k are set to 177 and 143, and furthermore, 4.433619M
7. The reference signal generating circuit according to claim 6, wherein when a burst signal of Hz is input, an output signal of said first voltage controlled oscillator is directly input to said second phase comparator. 9. The center oscillation frequency of the first voltage controlled oscillator is set to about 17.7 MHz, and 3.575611 MHz.
When the burst signal is input, the values of j and k, which are the frequency division numbers of the first and second frequency dividers, are set to 186 and 150.
The values of j and k are set to 218 and 176 when a 3.579545 MHz burst signal is input, and the values of j and k are set to 177 when a 3.582056 MHz burst signal is input. 2. The reference signal generating circuit according to claim 1, wherein the values of j and k are both set to 200 when a burst signal of 4.433619 MHz is input. 10. A reference signal generating circuit for obtaining a continuous reference signal having the same frequency and the same phase as an input burst signal, comprising: a first voltage-controlled oscillator using a crystal oscillator; and a control terminal; A second device capable of changing an oscillation frequency of an output signal in accordance with a signal supplied to the control terminal;
A voltage-controlled oscillator, a phase comparator that performs a phase comparison between an output signal of the second voltage-controlled oscillator and the burst signal, and a smoothing of an output signal of the phase comparator. A low-pass filter input to the control terminal to form a feedback control path; a first counter for measuring a first time corresponding to m times the output signal period of the first voltage-controlled oscillator; A second counter for counting a second time corresponding to n times the output signal period of the second voltage controlled oscillator, and the second time corresponding to p times the output signal period of the second voltage controlled oscillator. A third counter that counts a longer third time; and if the second and third times are both shorter than the first time, lower the frequency of the second voltage controlled oscillator; Time 3 is more than the time 1 Increasing the frequency of the second voltage controlled oscillator if Kere, if there is the first time during the second and third time the second
Control means for applying a voltage that maintains the frequency of the voltage-controlled oscillator to the control terminal of the second voltage-controlled oscillator, wherein the reference signal is obtained from the output signal of the second voltage-controlled oscillator. Generator circuit. 11. The first counter outputs a first signal when the output signal of the first voltage controlled oscillator is input and counts m cycles, and the second counter outputs a second signal.
When the output signal of the voltage-controlled oscillator is input and the number of pulses is counted, a second signal is output. The third counter receives the output signal of the second voltage-controlled oscillator and outputs a second signal. When p pulses are counted, a third signal is output, the second and third counters are reset by a signal slightly delayed from the first signal, and the control means outputs the first signal. First and second latches for latching the second and third signals, and a signal obtained by decoding output signals of the first and second latches superimposed on an input signal of the low-pass filter. 11. The reference signal generating circuit according to claim 10, further comprising: 12. The reference signal generating circuit according to claim 10, further comprising means for validating feedback control from said phase comparator to said second voltage controlled oscillator only during a period in which said burst signal is valid. 13. The reference frequency signal generating circuit according to claim 10, further comprising a burst gate circuit for extracting said burst signal from a chroma signal input. 14. A frequency divider for multiplying the frequency of an output signal of the second voltage controlled oscillator by 1 / α, wherein the output signal of the second voltage controlled oscillator passes through the frequency divider and is subjected to the phase comparison. 11. The reference signal generation circuit according to claim 10, wherein the reference signal generation circuit inputs the reference signal and outputs the reference signal output. 15. A center oscillation frequency of the first voltage controlled oscillator is about 4.43 MHz, and the value of α is 4.
When the value of m is 2048 and a 3.575611 MHz burst signal is input, the values of n and p, which are the count numbers of the second and third counters, are set to 6610 and 6603, and the value of 3.579545 MHz is set. When a burst signal is input, the values of m and p are set to 6617 and 6610, and when a 3.582056 MHz burst signal is input, the values of m and p are set to 6622.
11. The reference signal generating circuit according to claim 10, wherein an output signal of said first voltage controlled oscillator is directly input to said phase comparator when a burst signal of 4.433619 MHz is input.