JPH09107286A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL which outputs a clock signal or the like stably locked to an input reference signal regardless of the variance of the input reference signal. SOLUTION: The PLL circuit consists of a phase comparator 1, a VCO 3, a clock generator 4, and a counter s to obtain an output signal S3. The clock generator 4 has the frequency division rate set by the value of a parameter PX. An output signal S4 of an LPF 2 and a certain voltage S5 are compared with each other by a comparator 6, and a phase delay signal S6 is outputted when the signal S4 is higher than the voltage S5. The frequency in occurrence is calculated in accordance with this signal S6 by a phase deviation calculation part 8c of an MPU 8 provided with a clock function 8b; and if this frequency exceeds a certain value, the deviation from the frequency range where the clock is stably outputted by the parameter PX is decided, and the parameter in the center of parameters for lock and output of the current frequency in the phase delay direction is selected from parameters in a parameter table 8e by a parameter selection part 8d and is set to the clock generator 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit which is used for digital video signal processing such as television video display on a PDP and which is stably locked even if an input reference signal changes.

[0002]

2. Description of the Related Art In a conventional PLL circuit including a clock generator whose output frequency changes by writing a parameter in a loop, the following parameter, which tends to correct the frequency shift, is written in the clock generator. In this case, since the same parameter operates in the vicinity of the end of the frequency range that can be locked and output, if the cycle of the input reference signal fluctuates, for example, when switching the input video signal, the lock often comes out and becomes unstable. Become.

[0003]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and a PL for outputting a clock signal or the like that is stably locked to a reference signal even if the input reference signal fluctuates.
To provide L.

[0004]

[Means for Solving the Problems] Means for detecting a phase deviation of a predetermined constant value or more between an input reference signal and a feedback signal, a means for calculating the occurrence frequency of the same phase deviation, and a parameter writing A clock generator inserted in the loop of the PLL circuit in which the frequency ratio changes, control means for calculating a parameter by the phase shift and writing it in the clock generator, and a PL for each parameter value.
When the L circuit is provided with a storage unit for storing the output frequency range of the clock generator when locked, and when the frequency of occurrence of the phase shift is equal to or greater than a predetermined constant value, the current parameter value is locked within a frequency range that can be output. From among the parameters that can output, the central parameter value in the direction to correct the phase shift is selected and written to the clock generator.

If there are an odd number of parameters that can output frequencies within the frequency range in which the current parameter value is locked and can be output, the central parameter value among the parameters excluding the current parameter is selected. Write to the clock generator.

When there is an even number of parameters that can output frequencies within the frequency range in which the current parameter value can be locked and output, the central parameter value of the parameters including the current parameter is selected. Write to clock generator.

The phase shift detecting means is provided with a comparator circuit which outputs a logic 1 when the output of the low-pass filter for integrating the outputs of the phase comparators of the reference signal and the feedback signal is higher than a predetermined constant voltage. The output signal is a phase delay signal or a phase advance signal.

The phase shift detecting means is provided with a comparator circuit which outputs a logic 1 when the output of the low-pass filter for integrating the outputs of the phase comparators of the reference signal and the feedback signal is lower than a predetermined constant voltage. The output signal is a phase lead signal or a phase delay signal.

Calculation of the occurrence frequency of the phase shift is performed by the MPU having a clock function, and the clock generator is also controlled by the MPU.

[0010]

Operation: A means for detecting a phase shift between the input reference signal and the feedback signal of the PLL, which is equal to or greater than a predetermined constant value, a means for calculating the occurrence frequency of the same phase shift, and a frequency division ratio changing by writing parameters. A clock generator inserted in the loop of the PLL circuit, a control means for calculating a parameter by the phase shift and writing the parameter in the clock generator, and an output frequency range of the clock generator when the PLL circuit is locked for each parameter value. When the frequency of occurrence of the phase shift is equal to or more than a predetermined constant value, a storage means is provided, and the phase is selected from among the parameters capable of outputting a frequency within a frequency range in which the current parameter value can be locked and output. Select the central parameter value in the direction to correct the deviation and write it to the clock generator. , Can set parameters with a frequency and outputting the locked substantially at the center in the clock generator to lock in a stable manner.

When there are an odd number of parameters that can output frequencies within the frequency range in which the current parameter values can be locked and output, the central parameter value among the parameters excluding the current parameter is selected. Then, the median value can be easily selected by writing in the clock generator.

When there is an even number of parameters that can output frequencies within the frequency range in which the current parameter value can be locked and output, the central parameter value among the parameters including the current parameter is selected. By writing to the clock generator, the central parameter can be selected even if each parameter has an even number.

The phase shift detecting means is provided with a comparator circuit which outputs a logic 1 when the output of the low-pass filter for integrating the outputs of the phase comparators of the reference signal and the feedback signal is higher than a predetermined constant voltage. By using the output signal as the phase delay signal or the phase advance signal, the phase delay or the phase advance can be detected with certainty.

The phase shift detecting means is provided with a comparator circuit which outputs a logic 1 when the output of the low pass filter for integrating the outputs of the phase comparators of the reference signal and the feedback signal is lower than a predetermined constant voltage. By setting the output signal to the phase advance signal or the phase delay signal, the phase advance or the phase delay can be detected with certainty.

The frequency of occurrence of phase shift is calculated by an MPU having a clock function, and the clock generator is also controlled by the MPU, so that the number of components can be reduced.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A PLL circuit according to the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a PLL according to the present invention.
3 is a block diagram of one embodiment of a circuit. FIG. The phase of the reference signal S1 such as the horizontal synchronizing signal and the feedback signal S2 of the PLL are compared by the phase comparator 1, and the duty pulse corresponding to the phase difference output from the phase comparator 1 is integrated by the LPF (low pass filter) 2. Then, the VCO (voltage control oscillator) 3 is controlled as a DC level signal. The output of the VCO 3 is divided by the clock generator 4 and the counter 5 to obtain the feedback signal S2. In this way, the output signal S3 of the PLL circuit such as the clock signal of the video signal locked to the input reference signal S1 can be obtained. Here, the clock generator 4 has a function of arbitrarily setting the frequency division ratio according to the value of the parameter PX written from the outside.

FIG. 2 shows the parameters set in the clock generator and the frequency range in which the PLL circuit locks and outputs. The PLL output signal S3 is selected by selecting an appropriate parameter, for example P5, from the respective parameter values P1, P2, ... Of the parameter PX set in the clock generator 4.
When the frequency of is locked at F0 and operating stably,
When the input reference signal S1 shifts to a high frequency due to switching of the input signal source or the like, the frequency of the PLL output signal S3 becomes, for example, F2.
Then, the lock is released and a phase shift occurs, resulting in instability.

To detect this phase shift, the comparator 6 compares the output signal S4 of the LPF 2 with a predetermined constant voltage S5,
When the output signal S4 of the LPF2 is higher than the constant voltage S5, the phase delay is normally performed and the phase delay signal S6 is output. Phase shift calculating unit 8c of MPU 8 having clock function 8b
Then, the occurrence frequency is calculated by counting the number of occurrences of the phase delay signal S6 within a certain time, and when the occurrence frequency is more than a predetermined certain frequency, the MPU 8 uses the above-mentioned parameter P.
If the frequency range for stable output is out of 5, the parameter selection unit 8d selects a new parameter PX from the parameters stored in the parameter table 8e and sets it in the clock generator 4. The parameter to be selected is the central parameter among the parameters P6, P7, P8 and P9 that lock and output the frequency F2 in the phase delay direction D2. If there are an even number of these, the current parameter S5 is set. The included central parameter P7 is selected.

The detection of the phase shift further includes LPF.
The output signal S4 of 2 and a predetermined constant voltage S7
In comparison, when the output signal S4 of the LPF2 is lower than the constant voltage S7, the phase is normally advanced, and the phase advance signal S8 is output. The occurrence frequency of the phase delay signal S8 is calculated by counting the number of occurrences of the phase delay signal S8 within a certain period of time in the phase shift calculator 8C of the MPU 8 having the clock function 8b. Is outside the frequency range F1 for stable output with the parameter P5, the parameter selection unit 8d displays the parameter table 8
new parameter PX from the parameters stored in e
To set the clock generator 4. The parameter to be selected is the frequency F1 in the phase delay direction D1.
Is a central parameter among the parameters P2, P3, and P4 to be locked and output. However, when there are an odd number of these, the central parameter P3 among them is selected.

[0020]

As described above, in the PLL circuit including the clock generator whose frequency division ratio can be changed by the parameter to be set in the loop, the occurrence frequency of the phase shift is calculated, and the occurrence frequency is equal to or more than a certain value. In this case, the current frequency among the parameters in the direction to correct the phase shift can be locked and output by selecting and setting the parameter located in the center of each parameter, which stabilizes even if the input reference frequency changes. It is possible to obtain an output signal that is locked and output.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a PLL circuit according to the present invention.

FIG. 2 is a diagram showing a parameter set in a clock generator and a frequency range locked and output by a PLL circuit.

[Explanation of symbols]

 1 Phase Comparator 2 LPF (Low Pass Filter) 3 VCO (Voltage Controlled Oscillator) 4 Clock Generator 5 Counter 6 Comparator 7 Comparator 8 MPU 8b Clock 8c Phase Deviation Calculator 8d Parameter Selector 8e Parameter Table S1 Input Reference Signal S2 Feedback signal S3 PLL output signal S4 LPF output S5 constant voltage S6 phase delay signal S7 constant voltage S8 phase lead signal PX parameter signal P1 to P9 parameters F0, F1, F2 PLL output frequency D1 phase lead direction D2 phase delay direction

Claims (6)

[Claims] 1. A means for detecting a phase shift between an input reference signal and a feedback signal that is equal to or greater than a predetermined fixed value, a means for calculating the occurrence frequency of the same phase shift, and a frequency division ratio changed by writing parameters. A clock generator inserted in the loop of the PLL circuit, a control means for calculating a parameter by the phase shift and writing the parameter in the clock generator, and an output frequency range of the clock generator when the PLL circuit is locked for each parameter value. When the frequency of occurrence of the phase shift is equal to or more than a predetermined constant value, a storage means is provided, and the phase is selected from among the parameters capable of outputting a frequency within a frequency range in which the current parameter value can be locked and output. Select the parameter in the center of the direction to correct the deviation and write it to the clock generator And the PLL circuit. 2. When there is an odd number of each parameter capable of outputting a frequency within a frequency range in which the current parameter value is locked and can be output, a central parameter value among the respective parameters excluding the current parameter 3. The PLL circuit according to claim 1, wherein the PLL circuit is selected and written in the clock generator. 3. When there is an even number of each parameter capable of outputting a frequency within a frequency range in which the current parameter value can be locked and output, the central parameter value among the respective parameters including the current parameter is set. 2. A method for selecting and writing to a clock generator.
The PLL circuit as described in the above. 4. The phase shift detecting means is provided with a comparator circuit which outputs a logic 1 when the output of a low-pass filter for integrating the outputs of the phase comparators of the reference signal and the feedback signal is higher than a predetermined constant voltage. The PLL circuit according to claim 1, wherein the output signal of the circuit is a phase delay signal or a phase advance signal. 5. The phase shift detecting means is provided with a comparator circuit which outputs a logic 1 when the output of a low pass filter for integrating the outputs of the phase comparators of the reference signal and the feedback signal is lower than a predetermined constant voltage. The PLL circuit according to claim 1, 2 or 3, wherein the output signal of the circuit is a phase lead signal or a phase delay signal. 6. An MPU having a clock function is used to calculate the frequency of occurrence of phase shift, and the MPU is also used.
The control of the clock generator is also carried out by means of claim 1, claim 2, claim 3, claim 4 or claim 5.
The PLL circuit as described in the above.