JPH09130237A - PLL circuit and transfer data signal processing device - Google Patents

Abstract

(57) 【Abstract】 PROBLEM TO BE SOLVED: A PLL circuit capable of high-speed pull-in for a skew pull-in response and a pull-in response from a free-running oscillation state, and A / D conversion processing and character addition processing of video signals using the same A transfer data signal processing device for performing the above is provided. An output signal of a variable oscillator that oscillates at a frequency N times that of a reference signal is divided by a frequency divider into a frequency L times (L <N) that of the reference signal. The first phase comparator 115 compares the phases of the reference signal and the divided signal 121 with the reference signal as timing, and controls the variable oscillator 101 so that the phase of the divided signal 121 matches the phase of the reference signal. At the same time, the frequency detector 109 controls the variable oscillator 101 so that the frequency of the divided signal 121 becomes a predetermined frequency. Further, when the second phase comparator 112 detects that the divided signal 121 is locked in a phase opposite to the normal phase, the signal selection switching circuit 107 inverts the phase of the divided signal 121. The divided signal 122 is output to the first phase comparator 115.
I made it input to.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal forming technique, and further, a PLL for generating a clock signal for reproducing data included in a data signal mutually transferred between another control circuit and a processing device. A technology particularly effective when applied to a (phase locked loop) circuit, for example, synchronizing with a horizontal synchronizing signal of a video signal necessary for A / D (analog / digital) conversion processing of a video signal which is a kind of transfer data signal The present invention relates to a technique useful when applied to a clock generating PLL circuit or a clock generating PLL circuit synchronized with a horizontal synchronizing signal used for character display position control in a character signal addition process to a video signal.

[0002]

2. Description of the Related Art When a computer performs image processing or the like, a video signal is taken into the computer, and when the taken video signal is an analog signal, the video signal is converted into a digital signal for signal processing inside the computer. (A / D conversion) may be performed.

When a video signal is A / D converted, the conversion clock is usually N times the horizontal synchronizing frequency of the video signal to be converted (N is an integer, for example, NTSC (Natio).
nalTelevision Systems Commuttee (clock) method or PAL (Phase Alteration by Lin)
There is a method that uses the clock of e). In those schemes, the value of N is 780, 858, 864 or 944. ) Frequency clock is used. The conversion clock having such a frequency is generated by the PLL circuit in synchronization with the horizontal synchronizing signal of the video signal.

FIG. 11 shows a block configuration of a conventional PLL circuit. This PLL circuit has an input terminal 10
A reference signal is input from the outside via 5, and a variable oscillator 101 capable of oscillating at a frequency N times the frequency fr of the input reference signal and an output signal of the variable oscillator 101 are divided by 1 / N. A frequency divider 102 that generates a frequency-divided signal having the same frequency fr ′ as the reference signal, and a phase comparator 103 that compares the frequency of the frequency-divided signal obtained by the frequency divider 102 with the phase of the reference signal. , A filter 10 for generating a variable oscillator control signal Vc by removing a high frequency component of the phase error signal output from the phase comparator 103 as a result of the comparison.
4 forms a loop, and the output of the filter 104 is used as the variable oscillator control signal Vc to control the oscillation frequency of the variable oscillator 101 to output the frequency N · fr to the output terminal 106.
The clock signal of is output.

Further, a PLL circuit for generating a clock synchronized with a horizontal synchronizing signal used for character display position control when adding a character signal to a video signal has the same configuration as the above circuit.

[0006]

However, it has been clarified by the present inventors that the above-described technology has the following problems.

That is, in general, a video signal has a skew (a discontinuity of the horizontal synchronizing signal at the joint of the video signal) which is caused by the structural accuracy of the reproducing apparatus like a reproduction signal of a home video tape recorder (VTR). Due to the skew, the cycle of the synchronization signal becomes discontinuous every time the field (vertical period) is switched. In FIG. 12, a state in which the cycle of the synchronization signal becomes discontinuous due to the skew is shown in FIG. 11 with the reproduced video signal (A) and the synchronous signal (B) separated from the reproduced video signal (A). It is shown as a timing diagram with the divided signal (C) output from the variable oscillator 101 of the PLL circuit. In FIG. 12, Th represents one horizontal period (Th = 1 / fH) of the synchronization signal (B), and ΔTs represents a time shift due to skew. When synchronizing with the horizontal synchronizing signal (B) of the reproduced video signal (A) having such a skew, in the conventional PLL circuit, the reference horizontal synchronizing signal (B) and the frequency-divided signal (C) to be compared. Since the phase comparison with is performed at a frequency ratio of 1: 1,
3, the maximum time shift ΔTs due to the skew is a half cycle Th / 2 of the horizontal synchronization signal (B) (the horizontal synchronization signal (B) and the divided signal (C) are 180 degrees out of phase with each other. State). In that case, the variable oscillator 101 is set to 1
Since the pulling-in is performed from the state where the phase is 80 degrees apart, it is necessary to change the oscillation frequency of the variable oscillator 101 from the steady oscillation frequency by at least N / 2 clocks, and the pulling-in requires a long time. During the pull-in time, the clock output from the variable oscillator 101 becomes unstable, and a stable conversion signal cannot be obtained during A / D conversion, for example.

Further, in the case where the state in which the reference signal is not input is changed to the input state, the variable oscillator 101 is generally used.
Starts the pull-in operation from the state of operating at a free-running frequency deviating from a predetermined oscillation frequency. As the phase error detection circuit in the PLL circuit, when using a sampling / holding type detection circuit that performs a phase error detection operation only during a period of a predetermined width of the reference signal and a holding operation during the remaining period, As shown in FIG. 14, in the process of pulling in from the free-running oscillation state, the flicker phenomenon of approaching or leaving the predetermined oscillation frequency is repeated. This flicker phenomenon further increases the pull-in time.

The present invention has been made in view of the above circumstances, and a skew is introduced in a PLL circuit that generates a clock signal used for transfer data signal processing such as A / D conversion processing of a video signal and character addition processing. PLL capable of high-speed pulling in response or pull-in response from free-running oscillation state
Its main purpose is to provide a circuit.

Another object of the present invention is to provide a transfer data signal processing device using a PLL circuit capable of high-speed pull-in in response to a skew pull-in response or a pull-in response from a free-running oscillation state. .

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, according to the present invention, the output signal of the variable oscillator that oscillates at a frequency N times as high as the reference signal is divided by the frequency divider to a frequency L times (L <N) as high as the reference signal, and the first signal is generated. The phase comparator compares the phases of the reference signal and the frequency-divided signal with the reference signal as timing, and the phase of the frequency-divided signal matches the phase of the reference signal, and the frequency detector outputs the frequency of the output signal of the variable oscillator. Alternatively, the oscillating frequency of the variable oscillator is controlled so that the frequency of the divided signal becomes a predetermined frequency, and the second phase comparator locks the divided signal in a phase opposite to the normal phase of the divided signal. When detected, the phase of the divided signal inputted to the first phase comparator is inverted by the signal selection switching circuit.

[0014]

1 is a block diagram of a PLL circuit according to a first embodiment of the present invention.

This PLL circuit has a reference signal input terminal 10
Reference signal (frequency is fr
And ) And a variable oscillator 101 capable of oscillating at a frequency N times (N · fr) and an output signal of the variable oscillator 101 (frequency is fo; fo = N · fr) is 1 / M (however,
M is a frequency division of 2 ≦ M <N) and is a frequency division near L times (where L is an integer of 2 ≦ L <N) of the reference signal, and a pair of frequency divisions that are 180 degrees out of phase with each other. Traffic light 12
1 / M frequency divider 111 that outputs 1, 122, and a first signal selection switching circuit that selects one of frequency-divided signals 121 and 122 output from frequency divider 111 and outputs it as comparison signal 125. 107 and its signal selection switching circuit 107
A first phase comparator 115 for performing a phase comparison between the comparison signal 125 output from the reference signal and the reference signal and outputting a phase error signal 130 corresponding to the phase difference between the two signals; and the divided signal 121 (or, A frequency detector 109 which counts the frequency-divided signal 122) every predetermined period and outputs a frequency error signal 131 corresponding to the deviation of the frequency-divided signal 121 from the normal frequency; the phase error signal 130 and the frequency error signal. And the switch 110 as a circuit function for stopping the operation of supplying the phase error signal 130 from the first phase comparator 115 to the adder 108.
And a filter 104 that generates a variable oscillator control signal Vc according to the signal output from the adder 108 and outputs the variable oscillator control signal Vc to the variable oscillator 101, forming a loop. The output of the filter 104 is input to the variable oscillator 101 as the variable oscillator control signal Vc, so that the oscillation frequency of the variable oscillator 101 is controlled and the signal of the frequency fo is output from the output terminal 106. There is.

As shown in FIG. 2, the 1 / M frequency divider 111 outputs the pair of frequency-divided signals 121 and 122 (for convenience, the first frequency-divided signal 121 and the third frequency-divided signal 122). .) Together with the respective divided edges 121, 122 at the high level in the range of ± α (α <90 °) around the respective falling edges (for the sake of convenience, the second divided signal). The signal 123 and the fourth frequency-divided signal 124 are output.

The PLL circuit of this embodiment includes
A second signal selection switching circuit 113 which receives the second frequency-divided signal 123 and the fourth frequency-divided signal 124, selects one of the frequency-divided signals 123 and 124, and outputs the selected signal as a comparison signal 126; The comparison signal 126 supplied from the signal selection switching circuit 113 is phase-compared with the reference signal, and when a predetermined comparison result is obtained, the first signal selection switching circuit 107 and the second signal selection switching circuit 113. Further, a second phase comparator 112 is provided which changes and outputs the phase selection signal 133 to prevent the phase selection signal 133 from being locked in a phase state opposite to the normal synchronization state. Second phase comparator 112
Based on the phase selection signal 133 supplied from the first signal selection switching circuit 107 and the second signal selection switching circuit 1
The comparison signal 125 and the comparison signal 126 in 13 are switched at the same time. When the first divided signal 121 is selected as the comparison signal 125, the second divided signal 123 is selected as the comparison signal 126, and the comparison signal 125 is selected.
When the third divided signal 122 is selected as, the fourth divided signal 124 is selected as the comparison signal 126. The first divided signal 121 is generated by the second divided signal 123.
This is because the falling edge of the third divided signal 122 is detected by the fourth divided signal 124.

The first phase comparator 115 outputs the comparison signal 12
Within a time period shorter than one cycle of 5, the phase comparison between the reference edge of the reference signal and the rising edge of the comparison signal 125 having a frequency L times that of the reference signal is performed. In FIG. 3, the comparison signal 125
Is 10 times the frequency fr of the reference signal, that is, an example of a normal synchronization state when L is 10 is the reference signal, the comparison signal 125, and the phase error current waveform 130 (when the phase error signal is represented as an error current. Waveform) is shown as a timing diagram. In the example of FIG. 3, the division ratio M
Is 78 and N is 780.

In FIG. 4, while the phase comparison operation is being performed by the first phase comparator 115 in the normal synchronization state, the skew occurs with a time width of ΔTs with respect to the reference signal of the period THo ( In the illustrated example, for example, 5 of the comparison signal 125
The timing diagram in the case of (occurring between the sixth cycle and the sixth cycle) is shown. When such a skew occurs, the first phase comparator 115 performs the phase comparison operation with the sixth cycle of the comparison signal 125 equivalently as a new first cycle. That is, the first phase comparator 115
Operates to output a phase error signal by considering the original skew having a time shift of ΔTs as the skew of the shift ΔTs1 within ± 0.5 cycles of the comparison signal 125 and outputting a phase error signal. Here, the comparison signal 125 is a signal having a frequency L times (10 times) that of the reference signal. Therefore, as compared with the conventional PLL circuit that performs the pull-in by comparing the phase with the frequency-divided signal having the same frequency as the reference signal, the pull-in after the skew occurrence becomes faster. In particular, the high-speed pull-in with respect to the skew generated in about a half cycle of the reference signal becomes remarkable.

The frequency detector 109 uses the number of clocks of the first frequency-divided signal 121 (or the third frequency-divided signal 122) having the frequency of L · fr input within a predetermined cycle of the reference signal. Is counted and the count value is compared with the regular clock number, so that the reference signal and the comparison signal 125 are, for example, 1: (L−) with respect to the regular frequency ratio (1: L).
It operates to prevent erroneous synchronization at frequency ratios such as 1) and 1: (L + 1). Specifically, the frequency detector 109 uses the clock of the first frequency-divided signal 121 (or the third frequency-divided signal 122) input during K (where K is a positive integer) cycle period of the reference signal. The number is counted, and the frequency error signal 131 is generated and output according to the difference between the counted value and the regular clock number L · K. By inputting the frequency error signal 131 to the variable oscillator 101 via the adder 108 and the filter 104, the oscillation frequency of the variable oscillator 101 is controlled so that the count value of the frequency detector 109 becomes L · K ± 1. To be done. For example, K = 1
When 0 and L = 10, the oscillation frequency of the variable oscillator 101 is controlled with an accuracy of 100 ± 1, that is, ± 1%.

When the periodicity of the reference signal becomes discontinuous due to skew or the like, the frequency detector 10
9 detects that the periodicity becomes discontinuous and initializes the counting state of the K period of the reference signal during frequency detection,
It is configured to start the recounting from the reference signal input next.

Further, when the frequency detector 109 determines that the variable oscillator 101 is not operating at the frequency within the predetermined range based on the counting result, it generates the phase comparison operation permission signal 132 and the switch 110. Output to. The switch 110 stops the supply of the phase error signal 130 from the first phase comparator 115 to the adder 108 when the phase comparison operation permission signal 132 is input.

The second phase comparator 112 detects that the falling edge of the comparison signal 125 input to the first phase comparator 115 and the reference edge of the reference signal match, and this PLL circuit Operates to prevent the lock from being locked in a phase state opposite to the normal synchronization state. That is, for example, as shown in FIG. 5, when the phase of the reference signal deviates by π with respect to the cycle of the comparison signal 125 due to skew or the like, the output state of the phase error current becomes an output state opposite to the normal synchronization state. In this case, the charge / discharge charge amount by one sampling is ± 0. In such a case, the conventional general PLL circuit holds in that state unless some disturbance occurs, resulting in an unstable state in which it is unclear when to shift to the normal synchronization state. However, P according to the present invention
In the LL circuit, the second phase comparator 112 continuously detects the state where the phase of the comparison signal 125 is π ± α with respect to the reference signal at least twice, and detects the anti-phase proximity detection pulses PA1 and PA2. Is generated, the pulse PA1, P
Upon receiving A2, the state of the phase selection signal 133 is changed.
Thereby, the first signal selection switching circuit 107 and the second signal selection switching circuit 107
Comparison signals 125, 12 by the signal selection switching circuit 113 of
The switching operation of No. 6 occurs, and at the time of the third sampling at least after the occurrence of the skew, the normal synchronization state is quickly changed. It is to be noted that α is appropriately a value obtained by dividing an integer of 360 ° such as 30 ° or 45 °.

In addition, generally, in the PLL circuit, when pulling in from the state where the frequency is shifted, the forward error signal output state in the flicker operation (see FIG. 14) as the sampling operation (the state at the upper right of FIG. 14). To a reverse error signal output state (downward rightward state in FIG. 14) through a phase region of π ± α. In the PLL circuit according to the present invention, π ±
A second phase comparator 112 for detecting sampling of the α phase region and a first for inverting the comparison signal 125.
Since the output of the backward error signal is reduced by the signal selection switching circuit 107, the equivalent high-speed frequency control is performed and the pull-in time is shortened, as shown in FIG.

In the NTSC system and the PAL system, the N values 780, 858, 864, 944 with respect to the reference signal of the oscillation frequency in the variable oscillator (this value is described in the section of the prior art). , L can be set as 10, 11, 9, and 10, respectively, so that the configuration of the frequency dividing circuit can be simplified and the mode changing circuit for changing the frequency dividing number can be easily designed. Further, since the frequency division number can be set smaller than in the conventional case, the delay time of the comparison signal can be reduced, the shift time in the lock phase can be reduced, and the delay circuit elements for time adjustment can be reduced. .

FIG. 7 shows a PLL according to the second embodiment of the present invention.
A block diagram of the circuit is shown.

In this PLL circuit, the output signal of the variable oscillator 101 is directly input to the frequency detector 109 to count the frequency (fo) of the output signal of the variable oscillator 101. As a result, P of the first embodiment
The effect that the frequency detection accuracy of the frequency detector 109 is improved as compared with the LL circuit is obtained. The other configuration is the same as that of the first embodiment, and therefore the description thereof is omitted.

Instead of directly inputting the output signal of the variable oscillator 101 to the frequency detector 109, the frequency divider 11 is used.
It is also possible to output a signal in the middle of frequency division by 1 from the frequency divider 111 and input it to the frequency detector 109 so that the frequency of the signal in the middle of frequency division is counted by the frequency detector 109. good.

FIG. 8 shows a PLL according to the third embodiment of the present invention.
A block diagram of the circuit is shown.

This PLL circuit, as a frequency detector,
A frequency detector 114 having a counter in which a count value is initialized every cycle of the reference signal is used. And
The frequency detector 114 is provided with the first signal selection switching circuit 1
The comparison signal 125 output from 07 and the phase selection signal 133 output from the second phase comparator 112 are input.

The frequency detector 114 counts the frequency (L · fr) of the input comparison signal 125 and divides the comparison signal 125 by 1 / L to generate a control signal 135 and a phase comparison operation permission signal 134. To do. Frequency detector 11
The control signal 135 generated in 4 is supplied to the second signal selection switching circuit 113, and the second signal selection switching circuit 113 is supplied.
To the second phase comparator 112 from the comparison signal 12
7 supply timing is controlled. Further, the phase comparison operation permission signal 134 is supplied to the switch 110 and the switch 1
Control the opening and closing of 10.

In FIG. 9, the comparison signal 125 is the reference signal 5
An example of the reference signal, the comparison signals 125 and 127, the phase comparison operation permission signal 134, and the control signal 135 when the frequency is doubled (L = 5) is shown as a timing diagram. As shown in FIG. 9, when the reference signal is omitted, the frequency detector 114 causes the counter to perform a cyclic operation to generate and output the phase comparison operation permission signal 134 and the control signal 135.

In the frequency detector 114, the interval between two consecutive sampling pulses of the input reference signal is 4.5.
When it is continuously detected a plurality of times within a clock or more than 5.5 clocks, it is determined that the frequency of the output signal of the variable oscillator 101 is low or high, and the frequency error signal is determined according to the level of the frequency. 131 is the adder 10
8 and the output of the phase comparison operation permission signal 134 is stopped.

The phase comparison operation permission signal 134 is the comparison signal 125 after the counter of the frequency detector 114 is initialized.
Is output with a width of 5 ± 0.5 clocks with respect to the count value of. The phase comparison operation permission signal 134 is transmitted to the switch 110.
Is input to the switch 110, the switch 110 is closed, and the phase error signal 130 output from the first phase comparator 115 is added to the adder 1
It is supplied to the variable oscillator 101 via 08 and the filter 104. When the output of the phase comparison operation permission signal 134 to the switch 110 is stopped, the switch 110
Opens and the supply of the phase error signal 130 to the variable oscillator 101 is stopped. In the example shown in FIG. 9, the phase error signal 130 is not supplied to the adder 108 because the output of the phase comparison operation permission signal 134 is stopped for the pulse of the reference signal having the skew of ΔTs.

The control signal 135 is output with a width of 5 ± 1 clock with respect to the count value of the comparison signal 125. Therefore,
The comparison signal 127 from the second signal selection switching circuit 113 is synchronized with the falling edges of the clocks having the count values of 5 and 1.
Is output. The second phase comparator 112 compares the phases of the input comparison signal 127 and the reference signal, and the comparison signal 127 and the reference signal are in phase, that is, the phase of the comparison signal 125 with respect to the reference signal. When it is detected at least twice consecutively that the value is π ± α, the phase selection signal 133 is changed. Thereby, the first
Similar to the embodiment, the comparison signal 125 by the first signal selection switching circuit 107 and the second signal selection switching circuit 113,
The switching operation of 127 occurs, and the normal synchronization state is quickly changed.

Regarding the other constitution, the above first
The description is omitted because it is the same as the embodiment.

According to the third embodiment, it is possible to obtain the effect that the number of elements such as transistors forming the frequency detector 114 is smaller than that of the PLL circuit of the first embodiment.

FIG. 10 shows an example of a transfer data signal processing device using the PLL circuit according to the present invention.

This transfer data signal processing device is a device (A / D conversion device) 200 for converting an analog signal into a digital signal when an analog video signal is taken into a computer or the like. The A / D converter 200 includes a sync separation circuit 220 that separates a horizontal sync signal from a video signal input from the data input terminal 210, and a sync separation circuit 2.
A horizontal synchronizing signal separated by 20 is input as a reference signal, and a PLL circuit 230 that generates a clock signal having a frequency N times that of the horizontal synchronizing signal, and its PLL circuit 23.
A clock signal having a frequency N times as high as that generated at 0 and the video signal are input, and an A / D converter 240 for operating the input clock signal as a conversion clock to perform digital conversion of the video signal is provided. It has a configuration and is formed on one semiconductor chip by, for example, a known semiconductor integrated circuit technology.

The data digitally converted by the A / D converter 240 is the external image digital signal processing circuit 30.
0, etc.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, the value of the frequency division ratio L in the frequency divider 111 is not limited to 10 and 5, and can be set to any integer such as 9, 11 or 20 as long as it is allowed.

Further, the phase comparator 115 may be of an exclusive logic type sampling system in which the error signal is zero in the normal synchronization state.

Further, the PLL according to the present invention is applied to a character display position control system when a character signal is added to a video signal.
A circuit may be used to generate a clock synchronized with the horizontal synchronizing signal in the character display position control.

In the above description, the case where the invention made by the present inventor is mainly applied to the video signal processing technology which is the field of application which is the background of the invention has been described, but the present invention is not limited thereto. It can be used to generate clocks used in various signal transfer data digital signal processing systems.

[0046]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, by performing phase comparison between the comparison signal having a frequency L times the reference signal and the reference signal, the pull-in time can be shortened to at least 1 / L or less even if a skew occurs. Further, when the phase of the comparison signal is inverted when the comparison signal is locked in the opposite phase with respect to the normal phase, the pull-in time from the anti-phase state is shortened. Further, since the reverse error signal output at the time of pulling in is suppressed, the pulling in time is further shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a PLL circuit according to the present invention.

FIG. 2 is a waveform diagram showing a divided signal output from the divider of the PLL circuit according to the present invention.

FIG. 3 is a timing diagram showing a normal synchronization state of the PLL circuit of the first embodiment.

FIG. 4 is a timing chart showing an example of a response to the skew of the PLL circuit of the first embodiment.

FIG. 5 is a timing chart showing an example of a response to the skew of the PLL circuit of the first embodiment.

FIG. 6 is a characteristic diagram showing an example of improvement of a pull-in process flicker phenomenon in a sampling method by a PLL circuit according to the present invention.

FIG. 7 is a block diagram showing a second embodiment of a PLL circuit according to the present invention.

FIG. 8 is a block diagram showing a third embodiment of a PLL circuit according to the present invention.

FIG. 9 is a timing diagram showing a normal synchronization state of the PLL circuit of the third embodiment.

FIG. 10 is a block diagram showing an example of an embodiment of a transfer data signal processing device using a PLL circuit according to the present invention.

FIG. 11 is a block diagram of a conventional PLL circuit.

FIG. 12 is a timing diagram illustrating skew of a video signal.

FIG. 13 is a timing diagram showing a state where the phase is shifted to the maximum due to skew.

FIG. 14 is a characteristic diagram showing a pull-in process flicker phenomenon in a sampling method using a conventional PLL circuit.

[Explanation of symbols]

101 variable oscillator 104 filter fr frequency of reference signal fo frequency of output signal of variable oscillator Vc variable oscillator control signal 102 1 / N frequency divider 103 phase comparator 105 input terminal 106 output terminal 107 first signal selection switching circuit 108 addition Switch 109 Frequency detector 110 Switch (circuit function for stopping the operation of supplying the phase error signal from the phase comparator to the adder) 111 1 / M frequency divider 112 Second phase comparator 113 Second signal selection switching Circuit 114 Frequency detector 115 First phase comparator 121 First divided signal 122 Third divided signal 123 Second divided signal 124 Fourth divided signal 125 Comparison signal 130 Phase error signal 131 Frequency error Signal 133 Phase selection signal 200 A / D converter (transfer data signal processor) 220 Synchronous separation circuit Path 230 PLL circuit 240 A / D converter 300 image digital signal processing circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor ▲ Flag ▼ Makoto 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Inventor Kenya Yamauchi Iruma-gun, Saitama Prefecture Asahidai 15 Moroyama-cho Osamu Hitachi Ritsubei Semiconductor Co., Ltd. (72) Inventor Takashi Kami, Asahidai 15 Osamu Moroyama-cho, Iruma-gun, Saitama Prefecture Eastern Japan Semiconductor Co., Ltd.

Claims (6)

[Claims] 1. A variable oscillator capable of oscillating at a frequency N times that of an input reference signal and having its oscillation frequency controlled according to a control signal, and an output signal of the variable oscillator divided by 1 / M (M is M ≧ 2) and L times the reference signal (L is an integer of L ≧ 2)
And a frequency divider that outputs a frequency-divided signal having a frequency in the vicinity of, and phase comparison between the reference signal and the frequency-divided signal is performed.
A phase comparator which outputs a phase error signal corresponding to the phase difference between the reference signal and the frequency-divided signal, which is performed within a time period smaller than the cycle; and an output signal of the variable oscillator or a signal obtained by frequency-dividing the output signal. A frequency detector that counts any of them for each predetermined period and outputs a frequency error signal corresponding to the deviation of the output signal of the variable oscillator or the divided signal of the output signal from the normal frequency; and the frequency detector, An adder that adds the output frequency error signal and the phase error signal output from the phase comparator, and from the phase comparator to the adder when a specific frequency count result is obtained by the frequency detector. A circuit function of stopping the operation of supplying the phase error signal, and generating a variable oscillator control signal for controlling the oscillation frequency of the variable oscillator according to the signal output from the adder,
And a filter for supplying the variable oscillator control signal to the variable oscillator. 2. The frequency divider outputs a second frequency-divided signal composed of a pulse signal having a predetermined phase width of less than ± 90 degrees around a phase opposite to the normal phase of the frequency-divided signal. Receiving the second frequency-divided signal, sampling the pulse signal of the second frequency-divided signal at the sampling cycle of the reference signal, and sampling the pulse signal continuously at least twice. A second phase comparator that generates or changes a phase selection signal and outputs the phase selection signal is provided separately from the first phase comparator, and receives a phase selection signal output from the second phase comparator. The phase of the first frequency-divided signal input to the first phase comparator is inverted, and the phase of the second frequency-divided signal input to the second phase comparator is inverted. Phase corresponding to the phase of the first divided signal PLL circuit according to claim 1, characterized in that a signal selection switching circuit for. 3. The frequency detector outputs the frequency error signal and detects the continuity of the cycle of the input reference signal, and the periodicity of the reference signal becomes discontinuously. 3. When it is detected, the counting state during frequency detection for a predetermined period is initialized, and recounting is started from a reference signal continuously input in time. The described PLL circuit. 4. The frequency detector counts the first frequency-divided signal output from the signal selection switching circuit to 1 /
It has a cyclic counting circuit that is divided by L and is initialized by the reference signal only when the counting state when the reference signal is input is in a predetermined state, and is input continuously in time. 3. The frequency error signal is output when each initialization state of the counting circuit by the plurality of reference signals is the same state at least twice consecutively. PLL circuit. 5. The frequency divider, together with the first frequency-divided signal and the second frequency-divided signal, a third frequency-divided signal obtained by inverting the phase of the first frequency-divided signal, The fourth frequency-divided signal, which is a pulse signal having a predetermined phase width of less than ± 90 degrees centered on a phase opposite to the normal phase of the third frequency-divided signal, is output. 3. The PLL circuit according to 3 or 4. 6. A device for inputting an analog video signal on which a horizontal sync signal is superimposed, a sync separation circuit for separating the horizontal sync signal from the video signal, and a mixture of analog and digital signals for the video signal. 7. An analog / digital signal processing circuit for performing signal processing according to claim 1 and a PLL circuit according to claim 1, wherein the PLL circuit is a horizontal synchronization signal separated by the synchronization separation circuit. Is used as a reference signal, a signal having a frequency N times that of the reference signal is generated and output to the analog / digital signal processing circuit, and the analog / digital signal processing circuit outputs the reference signal input from the PLL circuit. A transfer data signal processing device, characterized in that the analog / digital mixed signal processing operation is performed by using a signal having a frequency of N times as a clock. .