JP3353372B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit for a liquid crystal display device which can cope with a plurality of kinds of synchronous signal inputs having different scan line scan rates of image signals (hereinafter abbreviated as "multi-scanning system"). The present invention relates to a mounted liquid crystal display device.

[0002]

2. Description of the Related Art A conventional PLL circuit is a conventional PLL circuit.
The configuration used in 116436, that is, the configuration shown in the block diagram of FIG.

The frequency division is performed on a reference signal generated from a reference crystal oscillation circuit 101 by a programmable frequency divider 105 for setting a frequency division ratio in order to take out an oscillation output of a VCO 104 as a desired frequency which is phase-locked.
The frequency-divided output is input to the phase comparator 102 as a signal to be compared, and the phase is compared with the reference signal output of the reference crystal oscillation circuit 101. The result (phase difference) is converted to a voltage and
The voltage is fed back to the VCO 104 via the low-pass filter 103 as a control voltage of CO.

Thus, the oscillation output of the VCO 104 controlled by the feedback voltage repeatedly returns to the phase comparator 102 via the programmable frequency divider 105 again, and the oscillation output of the VCO 104 becomes the reference signal output of the reference crystal oscillator. And a phase lock loop for outputting a stable desired frequency is established.

This conventional system is suitable for use as an oscillator having a constant channel bandwidth in a predetermined frequency band, as represented by channel control of a radio transmitter and a receiver. .

[0006]

However, the above-mentioned PLL
In the circuit, in a multi-scanning type liquid crystal display device, the reference signal previously held by the reference crystal oscillation circuit must be a horizontal synchronization signal of the input image. There are a wide variety of signal formats ranging from to several hundred KHz, and it has been almost impossible to accommodate them all.

Further, in order for a liquid crystal display device having the same number of pixels to cope with a variety of input signals by a liquid crystal display device having the same number of pixels, even if an input reference frequency (horizontal synchronization cycle) is changed, the input signal changes. A PLL circuit that generates no read frequency is indispensable, but the prior art could not satisfy this.

The present invention is intended to solve such a problem. Even if an input image signal having a different horizontal synchronization frequency is input, the same oscillation frequency corresponding to the number of pixels of the liquid crystal display device is always output. It is an object of the present invention to realize a PLL circuit to be implemented and to realize a write / read separated dual-system PLL circuit that can be used in a multi-scanning type liquid crystal display device.

[0009]

According to the present invention, there is provided a liquid crystal display device comprising: a synchronization frequency detector for detecting a horizontal synchronization frequency of an input image signal; and a first voltage controlled oscillator (hereinafter referred to as a first VCO) for outputting a first signal. And a frequency setting device that outputs a signal indicating the frequency of the first signal; and a divider that outputs a signal indicating a value obtained by dividing the output of the frequency setting device by the detection output of the synchronous frequency detector. A first programmable frequency divider for dividing the first signal based on the output of the divider, and a first VCO based on the divided first signal and a horizontal synchronization pulse of the input image signal. A first phase comparator and a first low-pass filter for controlling a second voltage-controlled oscillator (hereinafter referred to as a second VC) for outputting a second signal.
O), a second programmable frequency divider for dividing the second signal based on a predetermined dividing ratio, and the second VC based on the divided second signal and the horizontal synchronization pulse.
A second phase comparator for controlling O and a second low-pass filter. Then, the timing of capturing the input image signal is controlled based on the second signal, and the display output timing of the liquid crystal display device is controlled based on the first signal.

[0010]

[0011]

(Embodiment 1) An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a PLL circuit according to the present invention, which is one embodiment of the present invention.

First, a horizontal synchronizing pulse fH of an input image signal serving as a lock reference signal of a PLL circuit is applied to a synchronizing frequency detector 1 and a phase comparator 2, and the synchronizing frequency detector 1
Converts the cycle of the horizontal synchronizing pulse fH into digital frequency and sends it to the divider 6.

The divider 6 has a PL which is a numerator of the operation.
FOUT is simultaneously inputted from a frequency setting device for setting the oscillation output frequency fOUT of L, and division of fOUT ÷ fH = N is performed, so that the dividing ratio N of the programmable frequency divider 5 is automatically calculated.

The result of this operation is output to the programmable frequency divider 5
The oscillation output from the VCO 4 is divided by 1 / N and input to the phase comparator 2 as a pulse a to be compared.

The phase comparator 2 given fH and the pulse to be compared a undergoes a phase difference → voltage conversion by a phase discriminating circuit and a charge pump which are components of the phase comparator, and
As a control voltage of CO4, V is applied through the low-pass filter 3.
Feedback is provided to CO4.

By repeating a series of feedback operations as described above, fOUT is phase-locked to fH and is output from the VCO 4 as a stable output.

In this description, the horizontal synchronizing pulse input as fH is approximately ten and several K in various current image signal sources.
Although it exists in the range of Hz to one hundred and several tens KHz, a series of configurations including the synchronous frequency detector 1, the divider 6, and the frequency setting device 7 sufficiently corresponds to the multi-scanning type display device which is the object of the present invention. It has the ability to automatically and instantaneously determine the frequency division ratio N of the programmable frequency divider.

Thus, even if fH changes over a wide range (input image source changes), a constant reference clock that matches the output capability of the display device, especially the number of pixels, which is a constraint in the case of a liquid crystal display device, is used. You can always get it.

(Embodiment 2) FIG. 2 is a block diagram showing a schematic configuration of a circuit of a liquid crystal display device according to an embodiment of the present invention.

First, the input image signal Vin is supplied to the sync separation circuit 1.
0 and input to the A / D converter 13. Next, as shown in the figure, the horizontal synchronizing signal fH and the vertical synchronizing signal fV separated by the synchronizing separation circuit 10 are applied to the PLL (A) 11 and the PLL (B) 18, and fV is a write control circuit / read control circuit. The signals are input to a liquid crystal display device control circuit (hereinafter abbreviated as an LCD control circuit).

At this time, the PLL (A) 11 has the configuration shown in FIG.
The output fOUTa of the VCO 203 is the write control circuit 1
2 and a programmable frequency divider 204 provided to set the frequency required by the A / D converter 13 and a closed loop of the PLL determined by the frequency division ratio input Nin.

The other process of obtaining fOUTa phase-locked to fH, including the low-pass filter 202, is basically the same as that described in the first embodiment. Is determined by the PLL (A) 11.

The one PLL (B) 18 is a PLL circuit according to the first embodiment described in detail in the first embodiment. Therefore, detailed description of the operation is omitted,
The effect is that the image input signal V
Even if the horizontal synchronizing signal fH of in changes, the reading control of the frame memory 14 and the L
A constant control clock is supplied to the read control circuit 19 and the LCD control circuit 17 to enable CD control.

The frame memory 14 includes a write control circuit 12, a read control circuit 19, and an A / D converter 1.
3 for temporarily storing and generating image-processed video data input via the D / A converter 15 as a display signal of the LCD 16 in accordance with the control signal and the video signal respectively input from the LCD 3.

With the configuration described above, two independent P
According to the present embodiment, the LL (A) and the PLL (B) can independently control various image capture timings for LCD control and readout timings for display control while synchronizing with an input image signal. It is.

[0027]

According to the PLL circuit of the present invention, even if an input image signal having a different horizontal synchronizing frequency is input, the same oscillation frequency corresponding to the number of pixels of the liquid crystal display device is always output.
It is extremely effective for realizing LL circuits and realizing a read / write separated type PLL circuit that can be used in a multi-scanning type liquid crystal display device, and is widely used in CRTs using LCDs with a limited number of display pixels. It can be said that this is an excellent means for realizing a multi-scanning type display device which is becoming increasingly popular.

Further, the present invention has an excellent effect of preventing the occurrence of disturbing clock noise due to the presence of an asynchronous clock, which is likely to occur in a read / write separation type image processing circuit, and is useful for improving the image quality of a liquid crystal display device using the same. is there.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a configuration of an embodiment according to claim 1 of the present invention.

FIG. 2 is a circuit block diagram showing a schematic configuration of an embodiment according to claim 2 of the present invention.

FIG. 3 is a circuit block diagram showing a configuration of an embodiment according to claim 2 of the present invention.

FIG. 4 is a circuit block diagram showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Synchronous frequency detector 2 Phase comparator 3 Low-pass filter 4 VCO 5 Programmable frequency divider 6 Divider 7 Frequency setting device 10 Synchronous separation circuit 11 PLL (A) 12 Write control circuit 13 A / D converter 14 Frame Memory 15 D / A converter 16 LCD 17 LCD control circuit 18 PLL (B) 19 Read control circuit 101 Reference crystal oscillation circuit

Claims (1)

(57) [Claims] A synchronous frequency detector for detecting a horizontal synchronous frequency of an input image signal; a first VCO for outputting a first signal; a frequency setting device for outputting a signal indicating a frequency of the first signal; A divider that outputs a signal indicating a value obtained by dividing an output of the setting device by a detection output of the synchronous frequency detector; and a first programmable frequency divider that divides the first signal based on the output of the divider. A first phase comparator and a first low-pass filter for controlling the first VCO based on the divided first signal and a horizontal synchronization pulse of the input image signal; and a second VCO for outputting a second signal. A second programmable frequency divider for dividing the second signal based on a predetermined dividing ratio; and a second phase for controlling the second VCO based on the divided second signal and the horizontal synchronization pulse. ratio Vessels and second
And a low-pass filter, wherein the timing of capturing the input image signal is controlled based on the second signal, and the display output timing of the liquid crystal display device is controlled based on the first signal. , Liquid crystal display device.