JPH0716161B2 - PLL circuit - Google Patents

Description

The present invention relates to a PLL circuit suitable for use in synchronizing a clock and a subcarrier in a color video camera system, for example.

[Conventional technology]

CCD as a PAL color video camera system
Some use a solid-state image sensor, but a PLL circuit is used to synchronize the clock for the CCD solid-state image sensor with the subcarrier of the color video signal.

FIG. 2 shows an example of this PLL circuit, in which (10) is a variable frequency oscillation circuit, which includes an inverter (11), a resistor (12), a crystal oscillator (13), capacitors (14) (15) and a varicap (1).
It consists of 6). Then, the oscillation frequency is controlled in accordance with the voltage applied to the varicap (16) with a frequency four times the clock frequency f _CK as the oscillation center frequency.

(20) is a phase comparison circuit that is also integrated into a one-chip IC together with a frequency dividing circuit. 1 / N frequency dividing circuit (21) and 1 / N frequency dividing circuit (22)
And a phase comparator (23). Then, the output signal of the variable frequency oscillator (10) is supplied to the 1 / M frequency dividing circuit (21) through the input terminal (20a).

Also, the 4f _SC signal from the crystal oscillator (30) whose oscillation frequency is four times the subcarrier frequency f _SC of the PAL color video signal is the input terminal (20b) of the phase comparison circuit (20).
Is supplied to the 1 / N frequency divider circuit (22) through. The output of the frequency dividing circuit (21) is the input terminal A of the comparator (23).
Then, the output of the frequency dividing circuit (22) is supplied to the other input terminal B, respectively. In this case, M and N are set so that 4f _CK / M = 4f _SC / N, both input signal frequencies of the comparator (23) are made equal, and both input signals from this comparator (23) An output corresponding to the phase error of the signal is obtained. Then, this phase error output is supplied to the Paris cap (16) of the variable frequency oscillation circuit (10) through the low pass filter (40), and its oscillation signal has a constant phase relationship with the output signal of the crystal oscillation circuit (30). Controlled to be.

In this conventional PLL circuit, the varicap (16) is used with its anode grounded. Therefore, when the potential of the output of the phase comparison circuit (20), that is, the output VL of the low pass filter (40) becomes high, the variable frequency oscillation circuit (10).
The oscillation frequency of becomes high. That is, the direction of change in the phase comparison output and the direction of change in the oscillation frequency of the variable frequency oscillator circuit (10) are the same.

The output signal of the variable frequency oscillation circuit (10) is supplied to the frequency dividing circuit (51), from which the clock C of the frequency f _CK is generated.
The K and the horizontal and vertical sync signals HD and VD are obtained.

Further, the output signal of the crystal oscillator (30) is supplied to the frequency dividing circuit (52), from which the subcarrier _SC of the frequency f _SC is obtained.

In this way, the clock CK and the subcarrier SC are synchronized.

[Problems to be solved by the invention]

By the way, in the PLL circuit configured as shown in FIG.
The clock C is synchronized with this subcarrier with reference to. However, in general, the output of the phase comparison circuit (20) is affected by signal leakage and has a variation similar to so-called jitter. Therefore, the output signal of the variable frequency oscillating circuit (10) is also affected by the fluctuation, and the fluctuation is included in the clock CK from the frequency dividing circuit (51). Since this clock CK is for reading the output from the CCD solid-state image sensor, there is a drawback that such fluctuations in the clock itself affect the CCD image output.

Therefore, it is conceivable to configure the PLL circuit so that the subcarrier is phase-synchronized with this clock with reference to the clock CK.

In this case, if the phase comparison circuit (20), which is a one-tick IC in FIG. 2, is used, two inputs are compared at the same frequency, so unlike the example in FIG. The output is output to the comparator (2
In 3), the output of the crystal oscillation circuit must be supplied to the comparator (23) via the 1 / M frequency dividing circuit (21). However, if you change the input like this,
Since the direction of change in the output from the phase comparison circuit (20) and the direction of change in the oscillation frequency of the variable frequency oscillation circuit are opposite, it cannot be used as it is, and the phase comparison circuit and variable frequency oscillation circuit A phase inversion circuit must be provided between them. Therefore, the number of parts increases, which is not preferable. If you use a phase comparison circuit with the frequency dividers (21) and (22) at the opposite insertion positions to the circuit (20) shown in Fig. 2, the number of parts will not increase, but that requires a new IC. However, there is a drawback that it becomes rather expensive.

The present invention is intended to provide a PLL circuit capable of eliminating the above drawbacks.

[Means for solving problems]

In the present invention, in which the subcarrier is locked by the PLL circuit on the basis of the clock, the phase comparator circuit (20) which is the one-chip IC of the example of FIG. 2 is used. Change the connection method of the varicap for changing the frequency. That is, in the variable frequency oscillating circuit, the varicap whose one end is conventionally grounded is connected to the power supply without being grounded, and the phase comparison output is applied as a difference from the power supply voltage.

[Action]

The voltage applied to the varicap is conventionally the comparison circuit (20).
However, since the difference between the power supply voltage and the comparison output is applied in the present invention, even if the phase comparison circuit that has been used as a one-chip IC, which is conventionally used, is used. The comparison output and the direction of change in the oscillation frequency of the variable frequency oscillation circuit match.

〔Example〕

FIG. 1 shows an embodiment of the present invention. In the figure, (60) is a variable frequency oscillation circuit, and its oscillation center frequency is set to 4f _SC . Like the circuit (10), the oscillator circuit (60) is composed of an inverter (61), a resistor (62), a crystal unit (63), capacitors (64) (65) and a varicap (66). The cathode side of the varicap (66) is connected to the power supply terminal (67), and the phase comparison circuit (20) passing through the low-pass filter (40) at the connection point between the anode of the varicap (66) and the capacitor (64). ) Output VL is supplied.

The oscillation output of this variable frequency oscillation circuit (60) is passed through the input terminal (20b) of the phase comparison circuit (20) and the 1 / N frequency divider circuit (22).
Through the other input terminal of the comparator (23) (reference input terminal)
Supplied to B.

Further, (70) is a crystal oscillation circuit with an oscillation frequency of 4f _CK , the output of which passes through the input terminal (20a) of the phase comparison circuit (20) and through the 1 / N frequency divider circuit (21) to the comparator (23). It is supplied to one input terminal (comparative input terminal) A.

Then, the output signal of the variable frequency oscillation circuit (60) is supplied to the frequency division circuit (81) to obtain the subcarrier _SC of frequency f _SC , and the output signal of the crystal oscillation circuit (70) is frequency-divided. The clock CK is supplied to the circuit (82) and the horizontal and vertical synchronizing pulses HD and VD are obtained from the clock CK.
That is, since the clock is obtained from a fixed crystal oscillation circuit, even if it is used for CCD reading, the conventional defects do not occur.

Since the output signal of the variable frequency oscillator circuit and the output signal of the crystal oscillator circuit are supplied to the phase comparison circuit (20) through the input terminal opposite to the conventional one, the output direction of this phase comparison circuit (20) is conventional. Although it is the reverse of that, one end of the varicap of the variable frequency oscillator circuit (60) is connected to the power supply, and the comparison output is supplied to this varicap as the difference between the power supply voltage and it. ) The direction of change in the oscillating frequency matches the direction of change in the comparison output, and as in the conventional case, in this case, the reference signal is used as the clock CK, and this clock CK and the subcarrier SC are synchronized. .

Thus, according to the embodiment described above, the 1 / M frequency divider (21)
Is connected to the comparison input terminal A and the 1 / N frequency divider (22) is connected to the reference input terminal B. The phase comparison circuit (20) has a comparator (23) and the output of this phase comparison circuit (20). The variable frequency oscillator circuit (60) is connected to the input side of the phase comparator circuit (20) as a comparison signal, and the output signal is connected to the low side filter (40) through a low frequency filter (40). The oscillation frequency of the oscillation circuit (60) is changed by changing the voltage between the terminals of the varicap (66), and the reference signal from the crystal oscillation circuit (70) is divided by 1 / N frequency divider (22). To the 1 / M frequency divider (21) (see Fig. 2) and the reference signal from the crystal oscillator (70) to 1 / M. Variable frequency oscillator (60) supplied to the frequency divider (21)
When the comparison signal from the varicap (66) is supplied to the 1 / N frequency divider (22) (see Fig. 1), the varicap (66) 's electrical characteristics are reversed so that the voltage-capacitance characteristics have opposite polarities. I am trying to change the target connection.

As a result, the PLL loop can be held in the negative feedback loop even if the reference signal and the signal that is in phase with the reference signal, that is, the comparison signal are alternately connected by using the same phase comparison circuit (20) as it is. Is obtained.

〔The invention's effect〕

According to the present invention, it is possible to use the phase comparison circuit which has been used as a one-chip IC and is used as it is, and the reference signal and the signal which is phase-synchronized with the reference signal are exchanged without using the phase inversion circuit. You can Therefore, there is no fear that the number of parts will increase or a new IC will be produced, resulting in higher cost.

[Brief description of drawings]

FIG. 1 is a system diagram of an example of a PLL circuit of the present invention, and FIG. 2 is a system diagram of an example of a conventional PLL circuit. (10) and (6
(0) is a variable frequency oscillation circuit, (20) is a phase comparison circuit integrated into a single-chip IC, (21) and (22) are frequency dividing circuits, (16)
And (66) are varicaps, and (30) and (70) are crystal oscillation circuits.

Claims (1)

[Claims] 1. A phase comparison circuit having a comparator in which a 1 / M frequency divider is connected to a comparison input terminal and a 1 / N frequency divider is connected to a reference input terminal, and a low-pass filter on the output side of this phase comparison circuit. In a PLL circuit including a variable frequency oscillation circuit connected through a filter, the output signal of which is fed back to the input side of the phase comparison circuit as a comparison signal, the variable frequency oscillation circuit has an oscillation frequency of a varicap. It is designed to change by changing the voltage between terminals.The reference signal is supplied to the 1 / N frequency divider and the comparison signal
The voltage-capacitance characteristic of the varicap is different between when supplying the / M frequency divider and when supplying the reference signal to the 1 / M frequency divider and the comparison signal to the 1 / N frequency divider. A PLL circuit characterized in that the electrical connection of the varicap is changed so as to have a reverse polarity.