JPH04305921A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04305921A JPH04305921A JP307291A JP307291A JPH04305921A JP H04305921 A JPH04305921 A JP H04305921A JP 307291 A JP307291 A JP 307291A JP 307291 A JP307291 A JP 307291A JP H04305921 A JPH04305921 A JP H04305921A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- charge
- oxide film
- amount
- gate oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 6
- 238000005468 ion implantation Methods 0.000 claims description 13
- 150000002500 ions Chemical class 0.000 abstract description 6
- 239000007943 implant Substances 0.000 abstract 1
- 230000006378 damage Effects 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特にイオン注入工程における半導体基板への帯電
量の測定方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for measuring the amount of charge on a semiconductor substrate during an ion implantation process.
【0002】0002
【従来の技術】従来、半導体装置の製造におけるイオン
注入工程での半導体基板への帯電量の測定は、図2に示
す様に、半導体基板1上に形成されたゲート酸化膜4と
アルミ電極5とからなる複数のパターンを用いて行われ
ていた。注入されるイオンビームの電荷6がゲート酸化
膜4に蓄積され帯電し、帯電量がある一定量を越えると
ゲート酸化膜4中で放電し、ゲート酸化膜4を破壊する
。このゲート酸化膜4の破壊をアルミ電極5に電圧を印
加する事により検出しゲート酸化膜4の破壊される割合
によって帯電量を測定していた。2. Description of the Related Art Conventionally, the amount of charge on a semiconductor substrate during the ion implantation process in the manufacture of semiconductor devices has been measured as shown in FIG. It was carried out using multiple patterns consisting of. The charge 6 of the implanted ion beam is accumulated and charged in the gate oxide film 4, and when the amount of charge exceeds a certain amount, a discharge occurs in the gate oxide film 4, destroying the gate oxide film 4. The breakdown of the gate oxide film 4 was detected by applying a voltage to the aluminum electrode 5, and the amount of charge was measured based on the rate of breakdown of the gate oxide film 4.
【0003】半導体基板上に電荷6が蓄積されるとその
クーロン力によりイオンビームが曲げられるため、不純
物の注入量を均一にできなくなる。こため帯電量測定用
の半導体基板を用いて帯電量を測定することにより、必
要に応じて帯電防止の対策、例えばエレクトロンシャワ
ーの使用等を用いることができる。すなわち、図3の破
線Bに示すように、規定のイオン注入条件におけるゲー
ト酸化膜の破壊が生じない程度(破壊率0%)に、エレ
クトロンシャワーの電流値を制御し、帯電の影響を除く
ことができる。When charges 6 are accumulated on the semiconductor substrate, the ion beam is bent by the Coulomb force, so that the amount of impurity implanted cannot be made uniform. Therefore, by measuring the amount of charge using a semiconductor substrate for measuring the amount of charge, it is possible to take measures to prevent charging, such as using an electron shower, as necessary. That is, as shown by the broken line B in FIG. 3, the current value of the electron shower is controlled to such an extent that the gate oxide film is not destroyed under the specified ion implantation conditions (destruction rate 0%), and the influence of charging is eliminated. Can be done.
【0004】0004
【発明が解決しようとする課題】この様に、半導体装置
製造におけるイオン注入工程での半導体基板への帯電量
の測定は、ゲート酸化膜に電荷が蓄積され、蓄積された
電荷が一定量を越えた時に放電によってゲート酸化膜が
破壊される事を利用して行なわれているため、ゲート酸
化膜の破壊まで到らない様な電荷の帯電量は、この従来
の方法では測定できない。特に半導体素子の微細化に伴
ってイオン注入量の均一化がより要求される近年におい
ては、微量の帯電量もイオン注入量を不均一にし、半導
体装置の特性にばらつきを与えるという問題点がある。[Problem to be Solved by the Invention] As described above, the measurement of the amount of charge on a semiconductor substrate during the ion implantation process in semiconductor device manufacturing is difficult because charge is accumulated in the gate oxide film and the accumulated charge exceeds a certain amount. Since this method takes advantage of the fact that the gate oxide film is destroyed by discharge when the gate oxide film is damaged, it is not possible to measure the amount of charge that does not lead to the destruction of the gate oxide film using this conventional method. Particularly in recent years, with the miniaturization of semiconductor devices, there has been a growing demand for uniformity in the amount of ion implantation, and even a small amount of charge can make the amount of ion implantation uneven, causing variations in the characteristics of semiconductor devices. .
【0005】[0005]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体基板へ不純物をイオン注入する工程と
、イオン注入後前記半導体基板に形成された多結晶シリ
コンからなる低抗体の抵抗値を測定することにより前記
イオン注入による半導体基板への帯電量を検出する工程
とを含んで構成される。[Means for Solving the Problems] A method for manufacturing a semiconductor device of the present invention includes a step of ion-implanting impurities into a semiconductor substrate, and a low-resistance antibody made of polycrystalline silicon formed on the semiconductor substrate after the ion implantation. The method includes the step of detecting the amount of charge on the semiconductor substrate due to the ion implantation by measuring the amount of charge on the semiconductor substrate.
【0006】[0006]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。図1は本発明の一実施例を説明するための
半導体チップの断面図である。Embodiments Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a semiconductor chip for explaining one embodiment of the present invention.
【0007】図1に示すように、帯電量測定用の半導体
基板1上には、酸化膜2を介して多結晶シリコンからな
る複数個の低抗体3が設けられている。この半導体基板
1上に不純物のイオン注入を行うと、例えば図4の破線
A1に示すように、帯電により抵抗体3の抵抗値が上昇
する。その抵抗値は各抵抗体3の位置により異なる。As shown in FIG. 1, a plurality of low antibodies 3 made of polycrystalline silicon are provided on a semiconductor substrate 1 for measuring the amount of charge with an oxide film 2 interposed therebetween. When impurity ions are implanted onto this semiconductor substrate 1, the resistance value of the resistor 3 increases due to charging, as shown, for example, by broken line A1 in FIG. The resistance value differs depending on the position of each resistor 3.
【0008】半導体基板1に規定量の不純物をイオン注
入する場合、抵抗体3の抵抗値は図4の破線A1に示し
たように高くなるが、エレクトロンシャワーを働かせる
ことにより実線A2のように、抵抗値の上昇、すなわち
帯電量を抑制することができる。When a prescribed amount of impurity is ion-implanted into the semiconductor substrate 1, the resistance value of the resistor 3 becomes high as shown by the broken line A1 in FIG. It is possible to suppress the increase in resistance value, that is, the amount of electrification.
【0009】この抵抗値の変動率と帯電量との関係は、
図3における実線Aのようになり、従来ゲート酸化膜の
破壊率が0%を越えようとする領域での抵抗値の変動率
は約15%であることが分る。従って、従来の測定法で
ゲート酸化膜の破壊に到らないような電荷の帯電量も図
3に示したように、抵抗値の変動率により十分測定でき
る。このため、例えば抵抗値の変動率が10%以下にな
るようにエレクトロンシャワーの電流値を制御すること
により、帯電量に影響されることなく、半導体基板によ
り均一に不純物をイオン注入することができる。[0009] The relationship between the rate of change in resistance value and the amount of charge is as follows:
As shown by the solid line A in FIG. 3, it can be seen that the fluctuation rate of the resistance value in the region where the destruction rate of the conventional gate oxide film tends to exceed 0% is about 15%. Therefore, as shown in FIG. 3, the amount of charge that does not destroy the gate oxide film using conventional measurement methods can be sufficiently measured by the rate of change in resistance value. Therefore, for example, by controlling the current value of the electron shower so that the fluctuation rate of the resistance value is 10% or less, impurity ions can be uniformly implanted into the semiconductor substrate without being affected by the amount of charge. .
【0010】0010
【発明の効果】以上説明したように本発明は、イオン注
入工程でのイオン注入による帯電量の測定に、半導体基
板上に形成された多結晶シリコンからなる抵抗体の抵抗
値を測定する事により、比較的小さな帯電量も定量的に
測定できる。このため帯電量を制御することが容易にな
るため、半導体装置の特性のばらつきを小さくできると
いう効果がある。[Effects of the Invention] As explained above, the present invention measures the amount of charge caused by ion implantation in the ion implantation process by measuring the resistance value of a resistor made of polycrystalline silicon formed on a semiconductor substrate. , relatively small amounts of charge can be measured quantitatively. This makes it easy to control the amount of charge, which has the effect of reducing variations in the characteristics of semiconductor devices.
【図1】本発明の一実施例を説明するための半導体チッ
プの断面図である。FIG. 1 is a cross-sectional view of a semiconductor chip for explaining one embodiment of the present invention.
【図2】従来例を説明するための半導体チップの断面図
である。FIG. 2 is a cross-sectional view of a semiconductor chip for explaining a conventional example.
【図3】実施例および従来例を説明するための帯電量と
、抵抗値の変動率及びゲート酸化膜の破壊率との関係を
示す図である。FIG. 3 is a diagram showing the relationship between the amount of charge, the rate of change in resistance value, and the rate of destruction of the gate oxide film, for explaining the embodiment and the conventional example.
【図4】抵抗体の位置とイオン注入後の抵抗体の抵抗値
との関係を示す図である。FIG. 4 is a diagram showing the relationship between the position of a resistor and the resistance value of the resistor after ion implantation.
1 半導体基板 2 酸化膜 3 抵抗体 4 ゲート酸化膜 5 アルミ電極 6 電荷 1 Semiconductor substrate 2 Oxide film 3 Resistor 4 Gate oxide film 5 Aluminum electrode 6 Charge
Claims (1)
工程と、イオン注入後前記半導体基板に形成された多結
晶シリコンからなる低抗体の抵抗値を測定することによ
り前記イオン注入による半導体基板への帯電量を検出す
る工程とを含むことを特徴とする半導体装置の製造方法
。1. A step of ion-implanting impurities into a semiconductor substrate, and charging the semiconductor substrate due to the ion implantation by measuring the resistance value of a low antibody made of polycrystalline silicon formed on the semiconductor substrate after the ion implantation. A method for manufacturing a semiconductor device, comprising the step of detecting the amount.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP307291A JPH04305921A (en) | 1991-01-16 | 1991-01-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP307291A JPH04305921A (en) | 1991-01-16 | 1991-01-16 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04305921A true JPH04305921A (en) | 1992-10-28 |
Family
ID=11547138
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP307291A Pending JPH04305921A (en) | 1991-01-16 | 1991-01-16 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04305921A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5451529A (en) * | 1994-07-05 | 1995-09-19 | Taiwan Semiconductor Manufacturing Company | Method of making a real time ion implantation metal silicide monitor |
-
1991
- 1991-01-16 JP JP307291A patent/JPH04305921A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5451529A (en) * | 1994-07-05 | 1995-09-19 | Taiwan Semiconductor Manufacturing Company | Method of making a real time ion implantation metal silicide monitor |
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