JPS60116128A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60116128A JPS60116128A JP22493483A JP22493483A JPS60116128A JP S60116128 A JPS60116128 A JP S60116128A JP 22493483 A JP22493483 A JP 22493483A JP 22493483 A JP22493483 A JP 22493483A JP S60116128 A JPS60116128 A JP S60116128A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor substrate
- ion implantation
- oxide film
- impurity layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Landscapes
- Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、不純物を半導体基板内にイオン打込みによっ
てイオン注入する工程による、半導体装置の製造方法に
161コするものである。DETAILED DESCRIPTION OF THE INVENTION The present invention provides 161 improvements to a method of manufacturing a semiconductor device using a step of implanting impurities into a semiconductor substrate by ion implantation.
第1図に従来の半グ、一体装置の製造方法を示す。FIG. 1 shows a conventional method of manufacturing a half-gage, integrated device.
半導体基板内1に不純物層をイオン打込みによって形成
する場合、イオン注入をする箇所以外はマスク2(例と
して、フォトレジスト、54o2’、など)でおおい薄
い酸化膜3を通して(酸化膜3はない場合もある)、イ
オン注入を行う。この方法では、マスク2I酸化膜3.
フィールド酸化膜40表面付近や内部に電荷が帯電して
しまう。したがって酸化膜3が半導体基板1との電位差
による破簸や、フィールド酸化膜4内の電荷帯電による
、フィールド部の反転の原因になる。従来の製造方法は
、この様な欠点があった。When forming an impurity layer in the semiconductor substrate 1 by ion implantation, a thin oxide film 3 is passed through the mask 2 (for example, photoresist, 54o2', etc.) except for the ion implantation area (if there is no oxide film 3). ), perform ion implantation. In this method, the mask 2I oxide film 3.
Electric charges are generated near the surface of the field oxide film 40 and inside the field oxide film 40. Therefore, the oxide film 3 becomes a cause of elutriation due to the potential difference with the semiconductor substrate 1, and the inversion of the field portion due to the charging of the field oxide film 4. Conventional manufacturing methods have such drawbacks.
本発明はイオン打込み前に半導体基板1全表面に導電性
被膜を形成後、イオン打込みを行う事によって上記欠点
を除去した半導体装置の製造方法を目的としたものであ
る。The object of the present invention is to provide a method for manufacturing a semiconductor device in which the above drawbacks are eliminated by forming a conductive film on the entire surface of a semiconductor substrate 1 before ion implantation, and then performing ion implantation.
以下第2図Cαl−(Ql f参照して本発明の一実施
例を説明する。An embodiment of the present invention will be described below with reference to FIG.
第2図(ロ)は、イオン注入によって不純物層を作成す
る工程を行う前に、半導体基板1全表面に導電性被膜5
(例えばAi、ドープドPo1y 8iなど)を被着さ
せたものを示す。次に通常のイオン打込み工程を行う。FIG. 2(b) shows that a conductive film 5 is applied to the entire surface of the semiconductor substrate 1 before the step of creating an impurity layer by ion implantation.
(e.g. Ai, doped Po1y 8i, etc.). Next, a normal ion implantation process is performed.
一定箇所に不純物層を作成する場合は、第2図(6)に
示すように導伝性被膜5上にマスクとなるものを被着さ
せ、フォトリソ工程によシ、バターニングを行い、イオ
ン注入を行う。When creating an impurity layer at a certain location, as shown in FIG. 2 (6), a mask is deposited on the conductive film 5, followed by a photolithography process, patterning, and ion implantation. I do.
イオン打込み工程終了後、マスク2.導伝性被膜5を除
去すれば良い。After completing the ion implantation process, mask 2. The conductive film 5 may be removed.
上記実施例は先に導伝性被膜5全被着させた後イオン注
入を行う工程を説明した。次にその逆の工程を第2図(
c)に示す、まず先にマスク2となるものを被着させ、
フォトリソによシバターニングを行う。その後全表面に
導伝性被膜5.被着させた後、イオン打込みによシ、不
純物層を作成する事は可能である。また、上記実施例は
一部分に不純物層を形成することを示しているが、半導
体基板1全表面にイオン打込みする場合にでも、導伝性
被膜5を被着させた後、イオン注入を行う事によっても
、本発明の目的を達成することができることはいうまで
もない。In the above embodiment, the process of performing ion implantation after the conductive film 5 has been completely deposited has been described. Next, the reverse process is shown in Figure 2 (
As shown in c), first put on what will become the mask 2,
Perform shiba patterning using photolithography. After that, a conductive coating is applied to the entire surface5. After deposition, it is possible to create an impurity layer by ion implantation. Further, although the above embodiment shows that an impurity layer is formed in a portion, even when implanting ions into the entire surface of the semiconductor substrate 1, the ion implantation can be performed after the conductive film 5 is deposited. It goes without saying that the object of the present invention can also be achieved.
以上の様に本発明は、導伝性被膜5を被着後、イオン注
入工程を行う場合、イオン注入時に起る静電荷の帯電全
導伝性被膜5からディスチャージし帯電を防ぐ事によっ
て向い酸化膜の破壊、フィールド部での反転を防ぐとい
う、効果がある。また帯電防止のために、電子シャワー
という装置をイオン注入機に取付けてイオン打込みを行
っているが、本発明金層いる事によって仁の様な装置を
使用しないでイオン注入を行えるという効果もある。As described above, when performing the ion implantation process after depositing the conductive film 5, the present invention prevents oxidation by discharging the electrostatic charge that occurs during ion implantation from the conductive film 5 and preventing charging. This has the effect of preventing membrane destruction and reversal in the field area. In order to prevent static electricity, a device called an electronic shower is attached to the ion implanter for ion implantation, but the presence of the gold layer of the present invention also has the effect of allowing ion implantation to be performed without using a device like a metal ion implanter. .
第1図は従来のイオン打込みによる不純物層の形成の製
造方法を示した断面図、第2図@〜(c)は本発明の半
導体装置の製造方法の一笑施例の工程順を説明するため
の断面図である。
1・・半導体基板 2・・マスク
8・・薄い酸化膜 4・・フィールド酸化膜5・・導伝
性被膜
以 上
出願人 セイコー電子工業株式会社
代理人 弁理士 最 上 務FIG. 1 is a cross-sectional view showing a conventional manufacturing method for forming an impurity layer by ion implantation, and FIGS. FIG. 1. Semiconductor substrate 2. Mask 8. Thin oxide film 4. Field oxide film 5. Conductive film or more
Claims (1)
程において、イオン注入前に半導体基板1全面に導伝性
被膜を被着させておく事を特徴とする半導体装置の製造
方法。1. A method for manufacturing a semiconductor device, which comprises depositing a conductive film over the entire surface of a semiconductor substrate 1 before ion implantation in a step of implanting impurities into a semiconductor substrate using an ion implanter.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22493483A JPS60116128A (en) | 1983-11-29 | 1983-11-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22493483A JPS60116128A (en) | 1983-11-29 | 1983-11-29 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60116128A true JPS60116128A (en) | 1985-06-22 |
Family
ID=16821467
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22493483A Pending JPS60116128A (en) | 1983-11-29 | 1983-11-29 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60116128A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61295627A (en) * | 1985-06-24 | 1986-12-26 | Nec Kansai Ltd | Ion implantation method |
JPS63234520A (en) * | 1987-03-23 | 1988-09-29 | Nec Corp | Manufacture of semiconductor device |
US5075240A (en) * | 1989-04-19 | 1991-12-24 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device manufactured by using conductive ion implantation mask |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52127157A (en) * | 1976-04-19 | 1977-10-25 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor |
JPS5464460A (en) * | 1977-10-11 | 1979-05-24 | Supadea Guregorio | Ion implantation method |
JPS5775463A (en) * | 1980-10-28 | 1982-05-12 | Nec Corp | Manufacture of semiconductor device |
-
1983
- 1983-11-29 JP JP22493483A patent/JPS60116128A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52127157A (en) * | 1976-04-19 | 1977-10-25 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor |
JPS5464460A (en) * | 1977-10-11 | 1979-05-24 | Supadea Guregorio | Ion implantation method |
JPS5775463A (en) * | 1980-10-28 | 1982-05-12 | Nec Corp | Manufacture of semiconductor device |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61295627A (en) * | 1985-06-24 | 1986-12-26 | Nec Kansai Ltd | Ion implantation method |
JPS63234520A (en) * | 1987-03-23 | 1988-09-29 | Nec Corp | Manufacture of semiconductor device |
US5075240A (en) * | 1989-04-19 | 1991-12-24 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device manufactured by using conductive ion implantation mask |
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