JPH04196263A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuits, and particularly to large-scale semiconductor integrated circuits.

[Conventional technology]

FIG. 2 is a plan view showing a conventional semiconductor integrated circuit. In the figure, (1) is the chip, (2a) is the memory section (RA
M), (2b) is a memory section (RAM duder), (2c
) is the memory part (ROM), (2d) is the memory part (ROM
+81 is a peripheral pad, and (7) is a CPU section.

Next, the effect will be explained.

A conventional semiconductor integrated circuit is constructed as described above, with memory parts (2a) to (2a), peripheral parts F (81), and CPU part (8) being formed in a mixed manner on a chip (1). .

[Problem to be solved by the invention]

Conventional semiconductor integrated circuits are configured as described above, so as the memory capacity increases, the chip size also increases, and due to chip size limitations, there are problems such as the need to limit the memory capacity. .

The present invention has been made to solve the above-mentioned problems, and its object is to construct a memory circuit configured on one chip as a separate chip to obtain a large-scale conductor integrated circuit.

[Means to solve the problem]

In the semiconductor integrated circuit according to the present invention, a metal material for ohmic contact and a metal bonding material are placed on the pads connecting the parent chip and the memory function chip, and the chips are placed facing each other, and each signal or power supply pad is placed facing each other. It is metal-bonded.

[Effect]

The bonding method in this invention is to form a memory circuit and a memory circuit peripheral circuit separated from a chip, or a part of a memory circuit and a memory circuit peripheral circuit into a chip, and place it on a parent chip and pads on a memory function chip. Each signal or power supply pad is bonded to each other using a metal bonding material.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figures show a semiconductor integrated circuit according to an embodiment of the present invention. chip, (2) is a memory function chip, (8) is a peripheral pad provided on the parent chip (1), (4) is provided on the parent chip (1) and memory function chip (2), and they are connected to each other. Bonding pad for connection, (5) is bonding pad +
4) Stack it on top, make ohmic contact between the bonding pad +41 and the following metal bonding material (6),
1) Metal material for ohmic contact to maintain space between the surfaces of the memory function chip (2) and avoid contact; (6) f″i parent chip (1) and memory function chip (2);
) is a metal bonding material such as solder for bonding.

Next, the operation will be explained. In the semiconductor integrated circuit configured as described above, the chips are connected to each other on the parent chip (1) and the memory function chip (2), and the memory function chip (2) A bonding pad C4) is provided in order to supply signals or power from the parent chip, and a metal material (5) for ohmic contact and a metal bonding material (6) are placed on this pad, facing each other for each signal or power. Connect the power supply pads so that they are flush against each other. Note that the memory function chip also includes a decoder necessary for the memory.

In the above embodiment, the memory circuit is configured as a separate chip, but peripheral circuits such as a timer circuit may be configured as separate chips, and the same effect can be obtained.

[Effects of the Invention] As described above, according to the present invention, the memory circuit and the peripheral circuit for the memory circuit, or a part of the memory circuit and the peripheral circuit for the memory circuit are formed into separate chips, so that the chip does not depend on the memory capacity. The size can be realized and there is an effect that a large-scale semiconductor integrated circuit can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a semiconductor integrated circuit according to an embodiment of the present invention, in which FIG. 1 (a+ is a plan view, FIG. In the figure, (1) is the parent chip, (2) is the memory function chip, (8) is the peripheral pad, C4) is the bonding pad, (
5I is a metal material for ohmic contact, and (6) is a metal bonding material. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A parent chip consisting of a semiconductor integrated circuit main body, a memory function chip consisting of a memory circuit and memory peripheral circuits such as a decoder, and signal pads or power supply pads necessary for connecting each other to each of the parent chip and memory function chip are provided, A metal material capable of ohmic contact is laminated on each of the signal pads or power supply pads, a metal bonding material is placed on the metal material, and the parent chip and memory function chip are placed facing each other. A semiconductor integrated circuit characterized in that each signal or each power supply pad is metal-bonded so as to face each other.