JPH02278740A - Packaging of semiconductor device - Google Patents
Packaging of semiconductor deviceInfo
- Publication number
- JPH02278740A JPH02278740A JP9917789A JP9917789A JPH02278740A JP H02278740 A JPH02278740 A JP H02278740A JP 9917789 A JP9917789 A JP 9917789A JP 9917789 A JP9917789 A JP 9917789A JP H02278740 A JPH02278740 A JP H02278740A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- chip
- sealing
- frame
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 title claims description 4
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 238000007789 sealing Methods 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 238000003754 machining Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
Landscapes
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、半導体装置のパッケージング方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method of packaging a semiconductor device.
通常、ＩＣチップをリードフレームに取りつけるに際し
ては、ＩＣチップとリードフレーム間はワイヤーボンデ
ィングされるか、チップ上に形成された接続用突起電極
（バンプ）を介して接続される。Usually, when an IC chip is attached to a lead frame, the IC chip and the lead frame are connected by wire bonding or via connecting protruding electrodes (bumps) formed on the chip.
ワイヤーボンディングでＩＣチップを実装する場合、Ｉ
Ｃの！１０数（ピン数）が増した場合、例えば、ｌ０Ｉ
Ｉｌ！１角２００ビンのＩＣの場合、チップ上のボンデ
ィングパッドの間隔は２００ｍ以下となり、ワイヤリン
グ時のツール（キャピラリー）とワイヤーの接触する限
界値に迫り、これ以上は不可能である。When mounting an IC chip using wire bonding, I
C's! If the number 10 (number of pins) increases, for example, l0I
Il! In the case of an IC with 200 bins per side, the distance between the bonding pads on the chip is less than 200 m, which approaches the limit value for contact between the tool (capillary) and the wire during wiring, and is impossible to achieve any longer.
また、ボンディング時間においても、ワイヤーボンディ
ング方式では、１ワイヤー当たり約０．２秒必要とし、
２００ワイヤーの場合、４０秒のボンディング時間を要
する。Also, regarding the bonding time, the wire bonding method requires approximately 0.2 seconds per wire.
For 200 wires, the bonding time is 40 seconds.
これに対し、バンプを介して接続する方式は、−括して
接合するため、ボンディング時間が２秒程度となり、大
幅に短縮化が図れるが、チップ上にバンプを形成する為
（バンプを形成するには通常のＡ２電極上に拡散防止の
金属層の形成や接合の改善を図る接着層の形成が必要で
ある）、コストアップ、歩留まりの低下につながるとい
った問題があった。On the other hand, in the method of connecting via bumps, the bonding time is approximately 2 seconds because the bonding is performed all at once, which can significantly shorten the bonding time. However, since the bumps are formed on the chip ( (It is necessary to form a metal layer on the normal A2 electrode to prevent diffusion and to form an adhesive layer to improve bonding), which leads to increased costs and decreased yield.
本発明は上記問題点を解決するためになされたもので、
その目的とするところは、多ピン化への対応が図れると
共に、ボンディング時間の短縮化が図れ、しかもコスト
アップにつながらない半導体装置のパッケージング方法
を提供することにある。The present invention has been made to solve the above problems,
The purpose is to provide a packaging method for a semiconductor device that can cope with an increase in the number of pins, can shorten bonding time, and does not lead to an increase in cost.
上記課題を解決するため本発明は、予めＩＣのボンディ
ングパッドに相対する位置にバンブを形成したリードフ
レームに封止枠を形成し、しかる後、前記リードフレー
ムを支えていたダイバーを切断すると共に端子をフォー
ミングして封止枠付リードフレームを形成し、該封止枠
付リードフレームにＩＣチップを接合し、該ＩＣチップ
を樹脂封止してなることを特徴とする。In order to solve the above problems, the present invention forms a sealing frame on a lead frame in which a bump is formed in advance at a position opposite to a bonding pad of an IC, and then, the diver supporting the lead frame is cut off and the terminal A lead frame with a sealing frame is formed by forming a lead frame with a sealing frame, an IC chip is bonded to the lead frame with a sealing frame, and the IC chip is sealed with a resin.
（実施例）
以下、本発明を実施例に基づいて説明する。第１図（ａ
）〜（ｄ）は本発明の一実施例を示す工程図である。ま
ず、リードフレーム１の適所、すなわちＩＣのボンディ
ングバンドに相対する位置にバンブ２を形成する（同図
（ａ）参照）。バンブ２は、Ａｕ等のＩＣ１１ｉ材料（
Ａ２）と接合性の良い材料で形成する６次に、上記リー
ドフレーム１に封止枠３をモールド成形する（同図（ｂ
）参照）、シかる後、リードフレームｌを支えていたダ
イバーを切断し、端子をフォーミングする（同図（Ｃ）
参照）、このように構成された封止枠付リードフレーム
４にＩＣチップ５を接合し、ボッティング等の方法によ
りＩＣチップ５を樹脂封止し、ＩＣの保護を行なう（同
図（ｄ）参照）。(Examples) Hereinafter, the present invention will be described based on Examples. Figure 1 (a
) to (d) are process diagrams showing one embodiment of the present invention. First, a bump 2 is formed at a suitable location on the lead frame 1, that is, at a position facing the bonding band of the IC (see FIG. 2(a)). The bump 2 is made of IC11i material such as Au (
Next, the sealing frame 3 is molded onto the lead frame 1 (see figure (b)).
), then cut the diver supporting the lead frame l and form the terminal (see (C) in the same figure).
), the IC chip 5 is bonded to the lead frame 4 with a sealing frame configured as described above, and the IC chip 5 is sealed with resin by a method such as botting to protect the IC (see (d) in the same figure). reference).
これにより、従来例の如きワイヤーボンディングのパッ
ド間隔の制限は取り除かれ、リードフレームの加工限界
まで可能となる。また、ボンディング時間はパッド数に
関係なく一定（２秒程度）となり、工程の効率化が図れ
る。さらに、リードフレーム１にバンブ２を形成するた
め、バンブ２の材料を適切に選択すれば（上記実施例の
ようにＡｕを用いれば）、ウェハーの特別な加工は必要
とせず、ワイヤーボンディングされるのと同様の仕ｊｊ
ｌｃＡｌバッド）のままで良いので、コストダウンが図
れる。さらにまた、リードフレームｌには封止枠３が成
形されているので、後工程での封止が容易になる。As a result, the limitation on the pad spacing of wire bonding as in the conventional example is removed, and it becomes possible to process the lead frame up to its processing limit. Furthermore, the bonding time is constant (about 2 seconds) regardless of the number of pads, making the process more efficient. Furthermore, in order to form the bumps 2 on the lead frame 1, if the material of the bumps 2 is appropriately selected (if Au is used as in the above embodiment), wire bonding can be performed without requiring any special processing of the wafer. Similar work to
lcAl pad) can be used as is, reducing costs. Furthermore, since the sealing frame 3 is formed on the lead frame 1, sealing in a subsequent process becomes easy.
なお、上記実施例では封止枠３をモールドで形成したが
、プリント板を形成するように積層して形成してもよい
。In the above embodiment, the sealing frame 3 is formed by molding, but it may be formed by laminating them to form a printed board.
本発明は上記のように、ＩＣチップとリードフレームの
接合時間の短縮化が図れると共に、多ピン対応が可能と
なり、また、従来のワイヤーボンディング用のＩＣをそ
のまま用いて一括ボンディングできるので、汎用性があ
りコストダウンが図れる。As described above, the present invention can shorten the bonding time between an IC chip and a lead frame, can support a large number of pins, and can be used for batch bonding using conventional wire bonding ICs as is, making it highly versatile. This allows for cost reduction.
第１図（ａ）〜（ｄ）は本発明の一実施例を示す工程図
である。
１・・・リードフレーム
２・・・バンブ
３・・・封止枠
４・・・封止枠付リードフレーム
５・・・ＩＣチップFIGS. 1(a) to 1(d) are process diagrams showing one embodiment of the present invention. 1... Lead frame 2... Bump 3... Sealing frame 4... Lead frame with sealing frame 5... IC chip
Claims (1)
バンプを形成したリードフレームに封止枠を形成し、し
かる後、前記リードフレームを支えていたダイバーを切
断すると共に端子をフォーミングして封止枠付リードフ
レームを形成し、該封止枠付リードフレームにＩＣチッ
プを接合し、該ＩＣチップを樹脂封止してなる半導体装
置のパッケージング方法。(1) A sealing frame is formed on a lead frame with bumps formed in advance at positions facing the bonding pads of the IC, and then the diver supporting the lead frame is cut and terminals are formed to form the sealing frame. A packaging method for a semiconductor device, comprising forming a lead frame with a sealing frame, bonding an IC chip to the lead frame with a sealing frame, and sealing the IC chip with a resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9917789A JPH02278740A (en) | 1989-04-19 | 1989-04-19 | Packaging of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9917789A JPH02278740A (en) | 1989-04-19 | 1989-04-19 | Packaging of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02278740A true JPH02278740A (en) | 1990-11-15 |
Family
ID=14240370
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9917789A Pending JPH02278740A (en) | 1989-04-19 | 1989-04-19 | Packaging of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02278740A (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5318926A (en) * | 1993-02-01 | 1994-06-07 | Dlugokecki Joseph J | Method for packaging an integrated circuit using a reconstructed plastic package |
| US5406117A (en) * | 1993-12-09 | 1995-04-11 | Dlugokecki; Joseph J. | Radiation shielding for integrated circuit devices using reconstructed plastic packages |
| US5700697A (en) * | 1993-02-01 | 1997-12-23 | Silicon Packaging Technology | Method for packaging an integrated circuit using a reconstructed package |
| US6261508B1 (en) | 1994-04-01 | 2001-07-17 | Maxwell Electronic Components Group, Inc. | Method for making a shielding composition |
| US6262362B1 (en) | 1994-04-01 | 2001-07-17 | Maxwell Electronic Components Group, Inc. | Radiation shielding of three dimensional multi-chip modules |
| US6368899B1 (en) | 2000-03-08 | 2002-04-09 | Maxwell Electronic Components Group, Inc. | Electronic device packaging |
| US6455864B1 (en) | 1994-04-01 | 2002-09-24 | Maxwell Electronic Components Group, Inc. | Methods and compositions for ionizing radiation shielding |
| US6613978B2 (en) | 1993-06-18 | 2003-09-02 | Maxwell Technologies, Inc. | Radiation shielding of three dimensional multi-chip modules |
| US6720493B1 (en) | 1994-04-01 | 2004-04-13 | Space Electronics, Inc. | Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages |
| US6813828B2 (en) | 2002-01-07 | 2004-11-09 | Gel Pak L.L.C. | Method for deconstructing an integrated circuit package using lapping |
| US6884663B2 (en) | 2002-01-07 | 2005-04-26 | Delphon Industries, Llc | Method for reconstructing an integrated circuit package using lapping |
| US7382043B2 (en) | 2002-09-25 | 2008-06-03 | Maxwell Technologies, Inc. | Method and apparatus for shielding an integrated circuit from radiation |
| US7696610B2 (en) | 2003-07-16 | 2010-04-13 | Maxwell Technologies, Inc. | Apparatus for shielding integrated circuit devices |
-
1989
- 1989-04-19 JP JP9917789A patent/JPH02278740A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5318926A (en) * | 1993-02-01 | 1994-06-07 | Dlugokecki Joseph J | Method for packaging an integrated circuit using a reconstructed plastic package |
| US5700697A (en) * | 1993-02-01 | 1997-12-23 | Silicon Packaging Technology | Method for packaging an integrated circuit using a reconstructed package |
| US6858795B2 (en) | 1993-06-18 | 2005-02-22 | Maxwell Technologies, Inc. | Radiation shielding of three dimensional multi-chip modules |
| US6613978B2 (en) | 1993-06-18 | 2003-09-02 | Maxwell Technologies, Inc. | Radiation shielding of three dimensional multi-chip modules |
| US5406117A (en) * | 1993-12-09 | 1995-04-11 | Dlugokecki; Joseph J. | Radiation shielding for integrated circuit devices using reconstructed plastic packages |
| US6455864B1 (en) | 1994-04-01 | 2002-09-24 | Maxwell Electronic Components Group, Inc. | Methods and compositions for ionizing radiation shielding |
| US6262362B1 (en) | 1994-04-01 | 2001-07-17 | Maxwell Electronic Components Group, Inc. | Radiation shielding of three dimensional multi-chip modules |
| US6720493B1 (en) | 1994-04-01 | 2004-04-13 | Space Electronics, Inc. | Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages |
| US6261508B1 (en) | 1994-04-01 | 2001-07-17 | Maxwell Electronic Components Group, Inc. | Method for making a shielding composition |
| US6368899B1 (en) | 2000-03-08 | 2002-04-09 | Maxwell Electronic Components Group, Inc. | Electronic device packaging |
| US6963125B2 (en) | 2000-03-08 | 2005-11-08 | Sony Corporation | Electronic device packaging |
| US6813828B2 (en) | 2002-01-07 | 2004-11-09 | Gel Pak L.L.C. | Method for deconstructing an integrated circuit package using lapping |
| US6884663B2 (en) | 2002-01-07 | 2005-04-26 | Delphon Industries, Llc | Method for reconstructing an integrated circuit package using lapping |
| US7382043B2 (en) | 2002-09-25 | 2008-06-03 | Maxwell Technologies, Inc. | Method and apparatus for shielding an integrated circuit from radiation |
| US7696610B2 (en) | 2003-07-16 | 2010-04-13 | Maxwell Technologies, Inc. | Apparatus for shielding integrated circuit devices |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH08255862A (en) | Lead frame, resin sealed semiconductor device, manufacture thereof, and molding die | |
| WO1998052217A3 (en) | Method of forming a chip scale package, and a tool used in forming the chip scale package | |
| JPH02278740A (en) | Packaging of semiconductor device | |
| US4951120A (en) | Lead frame and semiconductor device using the same | |
| US7960213B2 (en) | Electronic package structure and method | |
| JPH088385A (en) | Resin sealed semiconductor device | |
| JP4485210B2 (en) | Semiconductor device, electronic device, method for manufacturing semiconductor device, and method for manufacturing electronic device | |
| JPH0357236A (en) | Manufacture of resin-sealed semiconductor device | |
| JPH04144269A (en) | Hybrid integrated circuit device | |
| JP2885786B1 (en) | Semiconductor device manufacturing method and semiconductor device | |
| JP4570797B2 (en) | Manufacturing method of semiconductor device | |
| JPH0451056B2 (en) | ||
| MY106858A (en) | Resin sealing type semiconductor device in which a very small semiconductor chip is sealed in package with resin. | |
| JPH08279575A (en) | Semiconductor package | |
| JPH01206660A (en) | Lead frame and semiconductor device utilizing same | |
| JPH0366150A (en) | Semiconductor integrated circuit device | |
| JPH0574774A (en) | Resin-sealed type semiconductor device | |
| JPH10214934A (en) | Semiconductor device and its manufacture | |
| JPS61284951A (en) | Semiconductor device | |
| JPS60182733A (en) | Hybrid integrated circuit for contactless switch | |
| JPH05291345A (en) | Semiconductor device | |
| JPS6060743A (en) | Lead frame | |
| JPH0547835A (en) | Semiconductor device mounting structure | |
| JPS63141329A (en) | Ic package | |
| JPH0493039A (en) | Resin-sealed semiconductor device |