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JPS61284951A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61284951A
JPS61284951A JP60126562A JP12656285A JPS61284951A JP S61284951 A JPS61284951 A JP S61284951A JP 60126562 A JP60126562 A JP 60126562A JP 12656285 A JP12656285 A JP 12656285A JP S61284951 A JPS61284951 A JP S61284951A
Authority
JP
Japan
Prior art keywords
chip
semiconductor chip
semiconductor
package
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60126562A
Other languages
Japanese (ja)
Inventor
Shinji Mitsui
三井　真司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP60126562A priority Critical patent/JPS61284951A/en
Publication of JPS61284951A publication Critical patent/JPS61284951A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0652—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve the mounting density by oppositely bonding the second semiconductor chip on the main surface of the first semiconductor chip, and integrally packaging them, thereby placing a plurality of semiconductor chips on a chip placing section of the package. CONSTITUTION:The first semiconductor chip 1 to become a lower layer is mounted on a chip placing unit of a package so that the back surface of the chip 1 is contacted, at least one second semiconductor chip 7 is bonded to be opposed at the front surface with the chip 1 of the lower layer to form an upper layer, and they are integrally packaged in the state that the chips becomes a 2-layer structure. For example, the chip 1 is bonded to a lead frame 2, and the chip 1 and the frame 2 are coupled by fine wirings 5 of Au. Thereafter, the chip 7 formed with bump electrodes 6 in the state heated to approx. 250 deg.C is bonded in a face-down with the chip 1 to form an upper layer. A sealing resin 8 such as epoxy is eventually formed to complete a packaging.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、複数の半導体チップを同一パッケージに収容
した半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device in which a plurality of semiconductor chips are housed in the same package.

従来の技術 近年、実装密度を向上させる手段として、半導体チップ
のパッケージには、第３図に示したようなりＩＬ型に変
わって、第４図に示したＳＯ型で代表されるミニパッケ
ージが用いらｎている。さらに、機能の異なるチップを
個別にパッケージングせず、同一パッケージに収容した
ハイブリッドＩＣを用いる場合もある。BACKGROUND OF THE INVENTION In recent years, as a means to improve packaging density, mini packages, such as the SO type shown in Figure 4, have been used for semiconductor chip packages instead of the IL type shown in Figure 3. I'm annoyed. Furthermore, a hybrid IC may be used in which chips with different functions are housed in the same package instead of being individually packaged.

発明が解決しようとする問題点 しかし、ミニパッケージを使用しても同一パッケージに
１個のチップを収容するだけでは、複数のチップをプリ
ント基板に実装する場合、ノクノケージの数だけ基板面
積を占有してしまう。一方、ハイブリッドＩＣの場合で
も、同一チップ載置部平面上に複数のチップを塔載する
ことになるのでチップ数の増加に比例してパッケージサ
イズは増大し、やはり、実装密度向上に制限を与えるこ
とになる。Problems to be Solved by the Invention However, even if a mini package is used, accommodating only one chip in the same package means that when multiple chips are mounted on a printed circuit board, the board area will be occupied by the number of cages. I end up. On the other hand, even in the case of a hybrid IC, since multiple chips are mounted on the same chip mounting surface, the package size increases in proportion to the increase in the number of chips, which also limits the improvement in packaging density. It turns out.

問題点を解決するための手段 本発明は、上述問題点を解決するため、パッケージのチ
ップ載置部に下層となる第１の半導体チップの裏面が接
触するようにマウントし、少なくとも１個の第２の半導
体チップ全下層の前記第２の半導体チップと相互に表面
が対向するように接合して上層を形成し、半導体チップ
が２層構造となった状態でこれらを一体的にパッケージ
ングする。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention mounts a first semiconductor chip as a lower layer so that the back surface thereof is in contact with a chip mounting portion of a package, and at least one first semiconductor chip. The second semiconductor chip is bonded to the second semiconductor chip in the entire lower layer so that the surfaces thereof face each other to form an upper layer, and the two semiconductor chips are integrally packaged in a two-layer structure.

作　　用 かかる構造にすることにより、従来チップサイズによっ
てその面積を決定さｎていたパッケージのチップ載置部
には１個の素子しか塔載できなかったのに対し、本発明
では、前記チップ載置部の同等面積に約２倍の数のチッ
プが搭載可能となる。By adopting such a structure, only one element could be mounted on the chip mounting section of a conventional package whose area was determined by the chip size, but in the present invention, the chip mounting section Approximately twice the number of chips can be mounted on the same area of the mounting section.

実施例 第１図は、本発明を用いた樹脂封止型半導体装置の実施
例の断面図である。下層の半導体チップ１はリードフレ
ーム２と結線するためのＡ２電極３と上層の半導体チッ
プを接合するためのＣｕ／Ｔｉ／Ａｎの３層構造からな
る電極４を有している。Embodiment FIG. 1 is a sectional view of an embodiment of a resin-sealed semiconductor device using the present invention. The lower layer semiconductor chip 1 has an A2 electrode 3 for connection to the lead frame 2 and an electrode 4 having a three-layer structure of Cu/Ti/An for bonding the upper layer semiconductor chip.

本実施例の装置の組立て工程では、従来の樹脂封止型半
導体装置の組立て方法が利用でき、４２７０イからなる
リードフレーム２’）Ｈ４００″Ｃ程度に加熱してＡ　
ｕ　−Ｓ　Ｌ共晶法にて下層の半導体チップ１を前記リ
ードフレーム２にボンディングし、引き続き、同半導体
チップ１とリードフレーム２をＡｕまたはＡ２などの細
線５にて結線する。このあと、２５０°Ｃ程度に加熱し
た状態ではんだバンプ電極６１ｒ：設けた半導体チップ
７をフェイスダウンで下層半導体チップ１と接合し上層
を形成する。In the assembly process of the device of this embodiment, a conventional method for assembling a resin-sealed semiconductor device can be used.
The lower semiconductor chip 1 is bonded to the lead frame 2 by the u-S L eutectic method, and then the semiconductor chip 1 and the lead frame 2 are connected with a thin wire 5 made of Au or A2. Thereafter, while heated to about 250° C., the semiconductor chip 7 provided with the solder bump electrodes 61r is joined face down to the lower semiconductor chip 1 to form an upper layer.

最後にエポキシやシリコーンなどの封止樹脂８を用いて
成形し、パッケージング全完了する。なお上記実施例で
は、本発明を樹脂封止型で実現したが、第２図に示した
ようにセラミックパッケージ９で代替しても実現可能で
ある。Finally, molding is performed using a sealing resin 8 such as epoxy or silicone to complete packaging. In the above embodiment, the present invention was realized by a resin-sealed type, but it can also be realized by replacing it with a ceramic package 9 as shown in FIG.

発明の詳細 な説明したとおり、本発明によｎば、従来、半導体チッ
プに対応した半導体チップ載置部に１個の素子しか塔載
できなかったのに対し、複数の半導体チップが搭載可能
となり、実装時の部品数の減少による実装密度の著しい
向上となり、半導体装置のコストダウンが可能となる。As described in detail, according to the present invention, whereas conventionally only one element could be mounted on a semiconductor chip mounting section corresponding to a semiconductor chip, it is now possible to mount a plurality of semiconductor chips. This results in a significant improvement in packaging density due to a reduction in the number of components during packaging, making it possible to reduce the cost of semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明を樹脂封止型半導体装置に応。 用した実施例の断面図、第２図はセラミックパッケージ
を用いた本発明の実施例のキャップ封止前の斜視図、第
３図は従来のＤＩＬ型プラスチックバ。 ノケージの外観図、第４図は従来のＳＯ型ラプラスチッ
クパッケージ外観図である。 １・・・・・・下層（第１）の半導体チップ、２・・・
・・・リードフレーム、３・・・・・・ＡＩＤ、電極、
４・・・・・・Ｃｕ／Ｔｉ／Ａ℃電極、５・・・・・・
ＡｆｉまたはＡｕ細線、６・・・・・・はんだバンブ電
極、７・・・・・・上層（第２）の半導体チップ、８・
・・・・・封止樹脂、９・・・・・・セラミックパッケ
ージ。 代理人の氏名　弁理士　中　尾　敏　男　ほか１名／−
−−下ノ＠　−Ｉ４２ミチー７７″２−一り一１’７Ｌ
−４ ３−Ａｌｔ項 ６−−ｌじｒバーンでｅ不シFIG. 1 shows the present invention applied to a resin-sealed semiconductor device. FIG. 2 is a perspective view of an embodiment of the present invention using a ceramic package before the cap is sealed, and FIG. 3 is a conventional DIL type plastic package. Fig. 4 is an external view of a conventional SO type plastic package. 1... Lower layer (first) semiconductor chip, 2...
...Lead frame, 3...AID, electrode,
4...Cu/Ti/A℃ electrode, 5...
Afi or Au thin wire, 6...Solder bump electrode, 7...Upper layer (second) semiconductor chip, 8.
... Sealing resin, 9 ... Ceramic package. Name of agent: Patent attorney Toshio Nakao and 1 other person/-
--Lower @ -I42 Michi 77″2-Ichiriichi 1’7L
-4 3-Alt term 6--ljir burn e non-shield

Claims (1)

【特許請求の範囲】[Claims] 第１の半導体チップの主表面上に前記半導体チップと異
なる第２の半導体チップを相互に表面が対向するように
接合し、これらを一体的にパッケージングしたことを特
徴とする半導体装置。A semiconductor device characterized in that a second semiconductor chip different from the semiconductor chip is bonded to the main surface of a first semiconductor chip so that the surfaces thereof face each other, and these are integrally packaged.
JP60126562A 1985-06-11 1985-06-11 Semiconductor device Pending JPS61284951A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60126562A JPS61284951A (en) 1985-06-11 1985-06-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60126562A JPS61284951A (en) 1985-06-11 1985-06-11 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61284951A true JPS61284951A (en) 1986-12-15

Family

ID=14938238

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60126562A Pending JPS61284951A (en) 1985-06-11 1985-06-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61284951A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5701031A (en) * 1990-04-26 1997-12-23 Hitachi, Ltd. Sealed stacked arrangement of semiconductor devices
US6054763A (en) * 1997-10-31 2000-04-25 Oki Electric Industry Co., Ltd. Semiconductor device
EP1093165A1 (en) * 1999-10-12 2001-04-18 Agilent Technologies Inc. Integrated circuit assembly

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58154254A (en) * 1982-03-10 1983-09-13 Hitachi Ltd semiconductor equipment
JPS59117251A (en) * 1982-12-24 1984-07-06 Hitachi Micro Comput Eng Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58154254A (en) * 1982-03-10 1983-09-13 Hitachi Ltd semiconductor equipment
JPS59117251A (en) * 1982-12-24 1984-07-06 Hitachi Micro Comput Eng Ltd Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5701031A (en) * 1990-04-26 1997-12-23 Hitachi, Ltd. Sealed stacked arrangement of semiconductor devices
USRE37539E1 (en) * 1990-04-26 2002-02-05 Hitachi, Ltd. Sealed stacked arrangement of semiconductor devices
US6054763A (en) * 1997-10-31 2000-04-25 Oki Electric Industry Co., Ltd. Semiconductor device
EP1093165A1 (en) * 1999-10-12 2001-04-18 Agilent Technologies Inc. Integrated circuit assembly

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