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JPS59175150A - Mounting structure of electronic component - Google Patents

Mounting structure of electronic component

Info

Publication number
JPS59175150A
JPS59175150A JP58051180A JP5118083A JPS59175150A JP S59175150 A JPS59175150 A JP S59175150A JP 58051180 A JP58051180 A JP 58051180A JP 5118083 A JP5118083 A JP 5118083A JP S59175150 A JPS59175150 A JP S59175150A
Authority
JP
Japan
Prior art keywords
electronic component
component
recess
lead terminal
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58051180A
Other languages
Japanese (ja)
Inventor
Shin Tada
多田　伸
Yoshio Okajima
良男 岡嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP58051180A priority Critical patent/JPS59175150A/en
Publication of JPS59175150A publication Critical patent/JPS59175150A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To omit a connecting wiring pattern and a bump by a method wherein a recess is formed in a printed wiring substrate, an electronic component is contained and fixed therein, and another one is face-down-bonded to the bonding lead terminal of said component. CONSTITUTION:The connecting wiring pattern 2' to connect one electronic component 4 to another circuit element 5, etc. is provided on the substrate 1. The recess 6 is to contain the electronic component 5. The depth of the recess 6 is prescribed so that the top of the contained component 5 and said pattern 2' are in approximately the same plane. Said component 5 contained in this recess 6 is fixed by means of adhesive with the bonding lead terminal upside, and the other electronic component formed by connecting one bump to said pattern 2' is directly bonded to the lead terminal via bump 3. Thereby, the bump of said component 4 is directly bonded to the lead terminal of said component 5.

Description

【発明の詳細な説明】 く技術分野〉 本発明は印刷配線基板に複数個の電子部品を取付で電気
的に接続する電子部品の取付構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an electronic component mounting structure for electrically connecting a plurality of electronic components to a printed wiring board by mounting.

〈従来技術〉 中央演算処理装置（ＣＰＵ）と記憶装置（ＲＯＭ又はＲ
ＡＭ）などのテップ状電子部品全電気的に漣続するには
、普通第１図（イ）、（ロ）に示す通り、基板１に接続
配線パターン２を形成し、このパターン上にバンプ３を
有するＣＰＵチップ４とＲＯＭ（又はＲＡＭ）チップ５
を直接ボンディングすることにより行なわれている。<Prior art> Central processing unit (CPU) and storage device (ROM or R
In order to fully electrically connect a tip-shaped electronic component such as AM), normally a connection wiring pattern 2 is formed on a substrate 1, and bumps 3 are placed on this pattern, as shown in Figures 1 (a) and (b). CPU chip 4 and ROM (or RAM) chip 5 with
This is done by directly bonding.

しかしながら、このような取付構造によれば、両チップ
間を接続する複雑な配線パターンが必要であり、又ＲＯ
Ｍ（又はＲＡＭ）チップ５に接続用のバンプを形成しな
ければならないので、どうしてもコスト高になるという
欠点があった〇〈目的〉 本発明はかかる従来の欠点に鑑みて成されたもので、接
続配線パターンやバンプを省略できる非常に安価な電子
部品の取付構造を提供せんとするものである。However, such a mounting structure requires a complicated wiring pattern to connect both chips, and also requires a complicated wiring pattern to connect the two chips.
M (or RAM) chip 5, so a bump for connecting must be formed, so there was a drawback that it would be expensive. The present invention aims to provide a very inexpensive mounting structure for electronic components that can omit connection wiring patterns and bumps.

〈実施例〉 以下図にもとづいて本発明の詳細な説明する。<Example> The present invention will be explained in detail below based on the drawings.

第２図（（）は本発明に係る取付構造の平面図、同図（
ロ）はその側面図である。図において、ｌは基板、２′
は一方の電子部品（ＣＰＵ）４ｉ他の回路素子などに接
続するだめの接続配線パターン、５は他方の電子部品（
ＲＯＭ又はＲＡＭ）、６け前記電子部品５を収納する四
部である。Figure 2 (() is a plan view of the mounting structure according to the present invention;
b) is its side view. In the figure, l is the substrate, 2'
5 is the connection wiring pattern for connecting one electronic component (CPU) 4i to other circuit elements, etc., and 5 is the other electronic component (
ROM or RAM), and four parts that house the six electronic components 5 mentioned above.

この凹部の深さは同図（ロ）に示す如く収納した電子部
品５の頂部と接続配線パターン２′が路面−となるよう
に規定されている。そして、この凹部６に収納された電
子部品５はボンディング用リード端子（図示せず）を上
にして接着剤により固着され、かつそのリード端子には
一方のバンプを前記接続配線パターン２′に接続してな
る今一つの電子部品（ＣＰＵ）４がバンプ３を介して直
接ボンディングされている。The depth of this recess is determined so that the top of the stored electronic component 5 and the connection wiring pattern 2' are flush with the road surface, as shown in FIG. The electronic component 5 housed in the recess 6 is fixed with adhesive with the bonding lead terminal (not shown) facing upward, and one bump is connected to the lead terminal to the connection wiring pattern 2'. Another electronic component (CPU) 4 is directly bonded via the bumps 3.

このようにすれば、電子部品（ＣＰＵ）４のバンプと今
一つの電子部品（ＲＯＭ又はＲＡＭ）５のボンディング
用リード端子全直接結合できるから、基板ｌに両室子部
品間を接続するだめの配線パターンが不要となり、又電
子部品５の方にバンプを形成せずに電気的結合を行なう
ことが出来る。In this way, the bumps of the electronic component (CPU) 4 and the bonding lead terminals of the other electronic component (ROM or RAM) 5 can all be directly connected, so that the wiring that connects the two child components on the board 1 can be connected directly. No pattern is required, and electrical coupling can be achieved without forming bumps on the electronic component 5.

なお、上記実施例において、電子部品５を今一つの電子
部品４以外のものと接続する必要がある樽、合には、そ
のものと接続された配線パターン７にワイヤー８を用い
て、所謂ワイヤーボンディング方式により結合すればよ
い（第３図参照）。In the above embodiment, if the electronic component 5 needs to be connected to something other than another electronic component 4, the wire 8 is used for the wiring pattern 7 connected to the electronic component 5, so that a so-called wire bonding method is used. (See Figure 3).

〈効果〉 以上の様に本発明によれば、印刷配線基板に四部を形成
し、この四部に電子部品を収納固着し、この収納固着さ
れた電子部品のボンディング用リード端子に今一つの電
子部品をフェイスダウンボンディングするものであるか
ら、接続配線パターンとバンプを省くことが出来る。よ
って、非常に安価な電子部品の取付構造を提供すること
ができる。<Effects> As described above, according to the present invention, four parts are formed on a printed wiring board, electronic components are housed and fixed to these four parts, and another electronic component is attached to the bonding lead terminal of the electronic component that is housed and fixed. Since face-down bonding is used, connection wiring patterns and bumps can be omitted. Therefore, a very inexpensive mounting structure for electronic components can be provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（イ）、（ロ）は従来の取付構造を説明する図、
第２図（イ）、（ロ）は本発明の取付構造を説明する図
、第３図は他の実施例である。 イは印刷配線基板、２′は配線パターン、３はバンプ、
４及び５は電子部品、６は四部。Figures 1 (a) and (b) are diagrams explaining the conventional mounting structure;
FIGS. 2(a) and 2(b) are diagrams for explaining the mounting structure of the present invention, and FIG. 3 is another embodiment. A is a printed wiring board, 2' is a wiring pattern, 3 is a bump,
4 and 5 are electronic parts, and 6 is the fourth part.

Claims (1)

【特許請求の範囲】 １　印刷配線基板に複数個の電子部品を取付で電気的に
接続するものに於て、 前記基板に凹部を形成し、この凹部に電子部品を収納固
着し、この収納固着された電子部品のボンディング用リ
ード端子に今一つの電子部品をフェイスダウンボンディ
ングして取付てなることを特徴とする電子部品の取付構
造。[Scope of Claims] 1. In a device in which a plurality of electronic components are electrically connected to a printed wiring board by mounting, a recess is formed in the board, the electronic component is housed and fixed in the recess, and the electronic component is housed and fixed. An electronic component mounting structure characterized in that another electronic component is mounted by face-down bonding to the bonding lead terminal of the electronic component.
JP58051180A 1983-03-24 1983-03-24 Mounting structure of electronic component Pending JPS59175150A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58051180A JPS59175150A (en) 1983-03-24 1983-03-24 Mounting structure of electronic component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58051180A JPS59175150A (en) 1983-03-24 1983-03-24 Mounting structure of electronic component

Publications (1)

Publication Number Publication Date
JPS59175150A true JPS59175150A (en) 1984-10-03

Family

ID=12879636

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58051180A Pending JPS59175150A (en) 1983-03-24 1983-03-24 Mounting structure of electronic component

Country Status (1)

Country Link
JP (1) JPS59175150A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09199824A (en) * 1995-11-16 1997-07-31 Matsushita Electric Ind Co Ltd Printed wiring board and its mounting body
EP0774888A3 (en) * 1995-11-16 1998-10-07 Matsushita Electric Industrial Co., Ltd Printing wiring board and assembly of the same
DE102007020475A1 (en) * 2007-04-27 2008-11-06 Häusermann GmbH Method for producing a printed circuit board with a cavity for the integration of components and printed circuit board and application
JP2010232659A (en) * 2009-03-25 2010-10-14 Lsi Corp Three-dimensional electronics package
JP2017092170A (en) * 2015-11-06 2017-05-25 株式会社村田製作所 Mounting structure of electronic component

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5175964A (en) * 1974-12-27 1976-06-30 Hitachi Ltd KONSEISHUSEKIKAIROSOCHI

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5175964A (en) * 1974-12-27 1976-06-30 Hitachi Ltd KONSEISHUSEKIKAIROSOCHI

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09199824A (en) * 1995-11-16 1997-07-31 Matsushita Electric Ind Co Ltd Printed wiring board and its mounting body
EP0774888A3 (en) * 1995-11-16 1998-10-07 Matsushita Electric Industrial Co., Ltd Printing wiring board and assembly of the same
US6324067B1 (en) 1995-11-16 2001-11-27 Matsushita Electric Industrial Co., Ltd. Printed wiring board and assembly of the same
DE102007020475A1 (en) * 2007-04-27 2008-11-06 Häusermann GmbH Method for producing a printed circuit board with a cavity for the integration of components and printed circuit board and application
JP2010232659A (en) * 2009-03-25 2010-10-14 Lsi Corp Three-dimensional electronics package
JP2017092170A (en) * 2015-11-06 2017-05-25 株式会社村田製作所 Mounting structure of electronic component

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