JPH0282564A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0282564A JPH0282564A JP63235513A JP23551388A JPH0282564A JP H0282564 A JPH0282564 A JP H0282564A JP 63235513 A JP63235513 A JP 63235513A JP 23551388 A JP23551388 A JP 23551388A JP H0282564 A JPH0282564 A JP H0282564A
- Authority
- JP
- Japan
- Prior art keywords
- pellet
- pad
- pads
- back side
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＩＣペレットのポンディング方法に関し、特に
ＩＣペレット間を３次元立体的にポンディングする方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for bonding IC pellets, and particularly to a method for three-dimensionally bonding IC pellets.
従来、ＩＣペレットはそのシリコン表面に回路を形成す
るか、更に表面上部に立体的に３次元構造で回路を形成
するようになっており、ポンディングはその表面におい
てのみ行なわれる。Conventionally, an IC pellet has a circuit formed on its silicon surface or a circuit formed in a three-dimensional structure on the upper surface of the pellet, and bonding is performed only on that surface.
上述した従来のＩＣペレットではシリコン表面のみで裏
面使用は考慮されていないので、ＩＣペレットをケース
にマウントする際は２次元的に並べ、ポンディングはシ
リコン表面に対してのみ行なわれ、シリコン裏面への使
用はできないという欠点がある。In the conventional IC pellets mentioned above, only the silicon surface is used, and the back side is not considered, so when mounting the IC pellets in a case, they are arranged two-dimensionally, and bonding is performed only on the silicon surface, and not on the silicon back side. The disadvantage is that it cannot be used.
本発明のＩＣペレットのポンディング方法は、表面に意
味のある回路が形成されたＩＣペレットの裏面に導電性
のパッドを有し、該パッドが表面の回路と電気的に接続
され、該ＩＣペレットの裏に配置された第２のＩＣベレ
、トの表面のパッドと第１のＩＣペレットの裏面のパッ
ドとをバンプにより電気的に接続する手段を有している
。In the method for bonding an IC pellet of the present invention, a conductive pad is provided on the back side of an IC pellet on which a meaningful circuit is formed, and the pad is electrically connected to the circuit on the front side. The second IC pellet disposed on the back side has means for electrically connecting the pads on the front surface of the second IC pellet and the pads on the back surface of the first IC pellet by means of bumps.
したがって、ＩＣペレットの裏面を有効利用し、表面の
回路の電位を裏面のパッドに出せるようにした為に、Ｉ
Ｃペレット間を立体構造で直接ポンディングしてゆける
。Therefore, by effectively utilizing the back side of the IC pellet and making it possible to output the potential of the circuit on the front side to the pad on the back side, the I
Direct bonding between C pellets is possible due to the three-dimensional structure.
本発明について図面を参照して説明する。 The present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例の概略図である。FIG. 1 is a schematic diagram of a first embodiment of the invention.
■は、第１のＩＣペレット表面を表わし、２は、第１．
第２のＩＣペレット表面のパッド。３は、第１のＩＣペ
レット裏面を表わす、４は、第２のＩＣペレット表面の
パッド２の上に置くバンプ。2 represents the surface of the first IC pellet; 2 represents the surface of the first IC pellet;
Pad on the surface of the second IC pellet. 3 represents the back surface of the first IC pellet, and 4 represents a bump placed on the pad 2 on the surface of the second IC pellet.
５は第２のＩＣペレットの表面を表わす。６は、第１の
ＩＣペレット裏面のパッド。７は、第１のＩＣペレット
の表面のパッド２と裏面のパッド６とを電気的につなぐ
導体。5 represents the surface of the second IC pellet. 6 is a pad on the back side of the first IC pellet. 7 is a conductor that electrically connects the pad 2 on the front surface of the first IC pellet and the pad 6 on the back surface.
第１図に於て、キーポイントは、第１のＩＣペレ、トの
裏面に形成されたパッドと、表面に形成されているパッ
ド２とを電気的に結ぶ導体７の形成についてである。７
の導体は、まず表裏のパッド間にレーザでＩＣペレット
を貫通する穴を開け、ハンダをその穴に溶融させ流し込
み形成することが考えられる。ハンダでなくとも金、銀
、銅が考えられる０次に第２のＩＣペレット上のパッド
の上にバンプ４を置いて第１のＩＣペレットを第２のＩ
Ｃペレットの上にかぶせるように置く。パッド６のレイ
アウト位置に対し、第２のＩＣペレット表面のパッド２
のレイアウト位置が考慮され、ペレット同志を合わせた
時にこれらのパッド間がバンプ４によって電気的につな
がれば、第１のＩＣと第２のＩＣとは電気的にバ、ド間
で結ばれ、ポンディングが行なわれたことになる。In FIG. 1, the key point is the formation of a conductor 7 that electrically connects the pad formed on the back surface of the first IC plate and the pad 2 formed on the front surface. 7
The conductor may be formed by first drilling a hole through the IC pellet between the front and back pads using a laser, and then melting and pouring solder into the hole. Gold, silver, or copper can be used instead of solder. Place the bump 4 on the pad on the second IC pellet and connect the first IC pellet to the second IC pellet.
Place it over the C pellet. With respect to the layout position of pad 6, pad 2 on the surface of the second IC pellet
If the layout positions of the pads are taken into consideration and these pads are electrically connected by the bumps 4 when the pellets are aligned, the first IC and the second IC will be electrically connected between the pads and the pump will be connected. This means that the ding has been carried out.
第２図は、本発明の第２の実施例の概略図である。FIG. 2 is a schematic diagram of a second embodiment of the invention.
第１の実施例との差異は７の２と６のパッド間をつなぐ
導体を、ペレットのシリコン内部に置くのでなく、図の
ように外部を廻すように配置する点にある。７の導体材
料はハンダ等が考えられる。The difference from the first embodiment is that the conductor connecting between pads 7 and 6 is not placed inside the silicon pellet, but is placed around the outside as shown in the figure. The conductor material 7 may be solder or the like.
他は全て第１の実施例と同様なので説明は省略する。Everything else is the same as in the first embodiment, so explanations will be omitted.
以上説明したように本発明は、表面に意味のある回路が
形成されたＩＣペレットの裏面に導電性のパッドを有し
、該パッドが表面の回路と電気的に接続され、該ＩＣペ
レットの裏に配置された第２のＩＣペレットの表面のパ
ッドと第１のＩＣペレットの裏面のパッドとをバンプに
より電気的に接続することにより、第１のＩＣと第２の
ＩＣを電気的にパッド間で結ぶことができる。このこと
により、異なる機能を有するＩＣペレットを何段にも積
み重ねて、立体構造のＩＣとすることができ、よりコン
パクトで空間あたりの実装密度を飛躍的に高める効果が
ある。As explained above, the present invention has a conductive pad on the back side of an IC pellet on which a meaningful circuit is formed, and the pad is electrically connected to the circuit on the front side. By electrically connecting the pads on the front surface of the second IC pellet disposed on the surface of the second IC pellet and the pads on the back surface of the first IC pellet with bumps, the first IC and the second IC are electrically connected between the pads. It can be tied with As a result, IC pellets having different functions can be stacked in multiple layers to form an IC with a three-dimensional structure, which is more compact and has the effect of dramatically increasing the packaging density per space.
面のパッド、７・・・・・・２と６のパッド間をつなぐ
導体。Surface pad, 7... Conductor connecting between pads 2 and 6.
Claims (1)
に導電性のパッドを有し、該パッドが表面の回路と電気
的に接続され、該ＩＣペレットの裏に配置された第２の
ＩＣペレットの表面のパッドと第１のＩＣペレットの裏
面のパッドとをバンプにより電気的に接続したことを特
徴とする半導体装置。A second IC pellet having a conductive pad on the back side of the IC pellet having a meaningful circuit formed on its surface, the pad being electrically connected to the circuit on the front side, and disposed on the back side of the IC pellet. A semiconductor device characterized in that a pad on the front surface of the first IC pellet is electrically connected to a pad on the back surface of the first IC pellet by a bump.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63235513A JPH0282564A (en) | 1988-09-19 | 1988-09-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63235513A JPH0282564A (en) | 1988-09-19 | 1988-09-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0282564A true JPH0282564A (en) | 1990-03-23 |
Family
ID=16987102
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63235513A Pending JPH0282564A (en) | 1988-09-19 | 1988-09-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0282564A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1233444A3 (en) * | 1992-04-08 | 2002-12-11 | LEEDY, Glenn J. | Membrane dielectric isolation ic fabrication |
| US7138295B2 (en) | 1997-04-04 | 2006-11-21 | Elm Technology Corporation | Method of information processing using three dimensional integrated circuits |
| US7176545B2 (en) | 1992-04-08 | 2007-02-13 | Elm Technology Corporation | Apparatus and methods for maskless pattern generation |
| US7193239B2 (en) | 1997-04-04 | 2007-03-20 | Elm Technology Corporation | Three dimensional structure integrated circuit |
| US7302982B2 (en) | 2001-04-11 | 2007-12-04 | Avery Dennison Corporation | Label applicator and system |
| US7402897B2 (en) | 2002-08-08 | 2008-07-22 | Elm Technology Corporation | Vertical system integration |
-
1988
- 1988-09-19 JP JP63235513A patent/JPH0282564A/en active Pending
Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7307020B2 (en) | 1992-04-08 | 2007-12-11 | Elm Technology Corporation | Membrane 3D IC fabrication |
| US7479694B2 (en) | 1992-04-08 | 2009-01-20 | Elm Technology Corporation | Membrane 3D IC fabrication |
| US6713327B2 (en) | 1992-04-08 | 2004-03-30 | Elm Technology Corporation | Stress controlled dielectric integrated circuit fabrication |
| US6765279B2 (en) | 1992-04-08 | 2004-07-20 | Elm Technology Corporation | Membrane 3D IC fabrication |
| US7615837B2 (en) | 1992-04-08 | 2009-11-10 | Taiwan Semiconductor Manufacturing Company | Lithography device for semiconductor circuit pattern generation |
| US7176545B2 (en) | 1992-04-08 | 2007-02-13 | Elm Technology Corporation | Apparatus and methods for maskless pattern generation |
| EP1233444A3 (en) * | 1992-04-08 | 2002-12-11 | LEEDY, Glenn J. | Membrane dielectric isolation ic fabrication |
| US7223696B2 (en) | 1992-04-08 | 2007-05-29 | Elm Technology Corporation | Methods for maskless lithography |
| US7242012B2 (en) | 1992-04-08 | 2007-07-10 | Elm Technology Corporation | Lithography device for semiconductor circuit pattern generator |
| US7550805B2 (en) | 1992-04-08 | 2009-06-23 | Elm Technology Corporation | Stress-controlled dielectric integrated circuit |
| US6682981B2 (en) | 1992-04-08 | 2004-01-27 | Elm Technology Corporation | Stress controlled dielectric integrated circuit fabrication |
| US7385835B2 (en) | 1992-04-08 | 2008-06-10 | Elm Technology Corporation | Membrane 3D IC fabrication |
| US7485571B2 (en) | 1992-04-08 | 2009-02-03 | Elm Technology Corporation | Method of making an integrated circuit |
| US7193239B2 (en) | 1997-04-04 | 2007-03-20 | Elm Technology Corporation | Three dimensional structure integrated circuit |
| US7474004B2 (en) | 1997-04-04 | 2009-01-06 | Elm Technology Corporation | Three dimensional structure memory |
| US7504732B2 (en) | 1997-04-04 | 2009-03-17 | Elm Technology Corporation | Three dimensional structure memory |
| US7138295B2 (en) | 1997-04-04 | 2006-11-21 | Elm Technology Corporation | Method of information processing using three dimensional integrated circuits |
| US8928119B2 (en) | 1997-04-04 | 2015-01-06 | Glenn J. Leedy | Three dimensional structure memory |
| US8933570B2 (en) | 1997-04-04 | 2015-01-13 | Elm Technology Corp. | Three dimensional structure memory |
| US9401183B2 (en) | 1997-04-04 | 2016-07-26 | Glenn J. Leedy | Stacked integrated memory device |
| US7302982B2 (en) | 2001-04-11 | 2007-12-04 | Avery Dennison Corporation | Label applicator and system |
| US7402897B2 (en) | 2002-08-08 | 2008-07-22 | Elm Technology Corporation | Vertical system integration |
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