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JP2001177049A - Semiconductor device and IC card - Google Patents

Semiconductor device and IC card

Info

Publication number
JP2001177049A
JP2001177049A JP36100099A JP36100099A JP2001177049A JP 2001177049 A JP2001177049 A JP 2001177049A JP 36100099 A JP36100099 A JP 36100099A JP 36100099 A JP36100099 A JP 36100099A JP 2001177049 A JP2001177049 A JP 2001177049A
Authority
JP
Japan
Prior art keywords
electrode pad
wiring board
wiring
chip
pad group
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP36100099A
Other languages
Japanese (ja)
Inventor
Hidekazu Hosomi
英一 細美
Akira Arita
亮 有田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Fukuoka Toshiba Electronics Co Ltd
Original Assignee
Toshiba Corp
Fukuoka Toshiba Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Fukuoka Toshiba Electronics Co Ltd filed Critical Toshiba Corp
Priority to JP36100099A priority Critical patent/JP2001177049A/en
Publication of JP2001177049A publication Critical patent/JP2001177049A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device on which a plurality of chips are mounted in the same wiring board for easily combining chips having different functions, and for assembling chips having the same function without the inversion (mirror state) of the circuit configuration. SOLUTION: A wiring board 1 on one face of which a wiring layer is formed is provided with a first electrode pad ground and a second electrode pad group formed on a wiring layer 3 on the wiring board, a through-hole 11 formed in the wiring board just under the second electrode pad, a first chip 2 connected with the first electrode pad group, and a second chip 2' connected with the second electrode pad group. In this case, the first electrode pad group and the second electrode pad group are arranged so as to be shifted from each other on the face on which the wiring layer is formed of the wiring board. Thus, it is possible to easily combine chips having different functions in the same wiring board, and to assembly the chips having the same function without the inversion (mirror state) of the circuit configuration.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、２個以上の半導体
チップを同一配線基板内に搭載した半導体装置及びこれ
を用いたＩＣカードに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having two or more semiconductor chips mounted on the same wiring board and an IC card using the same.

【０００２】[0002]

【従来の技術】近年、半導体チップ（以下、チップとい
う）を３次元的に積層することにより、実装面積はその
ままでありながら高密度で高性能な半導体装置を形成す
る技術が開発されている。例えば、同一のメモリを２つ
積層することにより２倍の容量のメモリを構成できる。
あるいは異種のメモリ（フラッシュメモリとＳＲＡＭ）
あるいはロジックとメモリなど異なる機能のチップを組
み合わせることにより、システムに適した半導体装置を
構成することが可能となる。図１２及び図１３は、従来
の複数のチップを配線基板に搭載させた半導体装置の１
例を示したものである。図１２において、リードフレー
ムの素子搭載部（ベッド）１０２の両面にシリコン半導
体などからなるチップ１００、１００′が接着剤１０
４、１０４′によりマウントされている。各チップ１０
０、１００′上のパッド（図示しない）とリードフレー
ムを構成するリード１０１の先端（インナーリード部）
とがＡｕなどからなるボンディングワイヤ１０３、１０
３′により接続されている。2. Description of the Related Art In recent years, a technique for forming a high-density and high-performance semiconductor device by three-dimensionally stacking semiconductor chips (hereinafter referred to as chips) while maintaining the mounting area has been developed. For example, by stacking two identical memories, a memory having twice the capacity can be configured.
Or different types of memory (flash memory and SRAM)
Alternatively, a semiconductor device suitable for the system can be configured by combining chips having different functions such as a logic and a memory. FIGS. 12 and 13 show a conventional semiconductor device having a plurality of chips mounted on a wiring board.
This is an example. In FIG. 12, chips 100 and 100 ′ made of a silicon semiconductor or the like are attached to both sides of an element mounting portion (bed) 102 of a lead frame by an adhesive 10.
4, 104 '. Each chip 10
Pads (not shown) on 0 and 100 'and tips of leads 101 constituting a lead frame (inner lead portion)
Are bonding wires 103, 10 made of Au or the like.
3 '.

【０００３】素子搭載部１０２、ボンディングワイヤ１
０３及びインナーリードは、エポキシ樹脂などの樹脂封
止体１０５により樹脂封止されている。また、図１３に
おいて、配線基板の両面には配線１１２、１１２′が形
成されており、それぞれの面にチップ１１０、１１０′
がフリップチップ接続されている。すなわち、チップ１
１０、１１０′に形成された接続電極上の金などのバン
プ１１３、１１３′が配線１１２、１１２′に接合され
ている。そして、チップ１１０、１１０′及び配線基板
１１１の間には樹脂封止体（アンダーフィル）が形成さ
れている。[0003] Element mounting portion 102, bonding wire 1
03 and the inner leads are resin-sealed by a resin sealing body 105 such as an epoxy resin. In FIG. 13, wirings 112 and 112 'are formed on both surfaces of the wiring board, and chips 110 and 110' are formed on the respective surfaces.
Are flip-chip connected. That is, chip 1
Bumps 113, 113 'made of gold or the like on connection electrodes formed on 10, 110' are joined to wirings 112, 112 '. A resin sealing body (underfill) is formed between the chips 110 and 110 'and the wiring board 111.

【０００４】[0004]

【発明が解決しようとする課題】例えば、図１２に示す
半導体装置では、半導体装置の各電極がともに共通の端
子に接続されているため、異なる機能をもつチップを組
み合わせるのは困難である。また同一機能をもった場合
でも、チップが向かい合わせになっているので、回路が
反転（ミラー状態）されていないと組み立てるのが難し
い。また、図１３に示す半導体装置では、配線基板の両
面に独立した配線が形成されているので、図１２の半導
体装置とは異なり、異なる機能をもつチップを積層する
ことができる。しかし、配線層が２層以上の基板が必要
となるため、基板コストが上昇し、半導体装置全体のコ
ストアップを招いてしまう。本発明は、このような事情
によりなされたものであり、異なる機能をもつチップを
容易に組み合わせることができ、また同一機能をもった
チップを回路構成が反転（ミラー状態）されないで組み
立てることができる複数のチップを同一配線基板内に搭
載した半導体装置及びこれを用いたＩＣカードを提供す
る。For example, in the semiconductor device shown in FIG. 12, since each electrode of the semiconductor device is connected to a common terminal, it is difficult to combine chips having different functions. Also, even in the case of having the same function, since the chips are faced to each other, it is difficult to assemble unless the circuit is inverted (mirror state). Further, in the semiconductor device shown in FIG. 13, since independent wiring is formed on both surfaces of the wiring board, chips having different functions can be stacked unlike the semiconductor device of FIG. However, since a substrate having two or more wiring layers is required, the cost of the substrate increases and the cost of the entire semiconductor device increases. The present invention has been made under such circumstances, and chips having different functions can be easily combined, and chips having the same function can be assembled without inverting the circuit configuration (mirror state). Provided are a semiconductor device having a plurality of chips mounted on the same wiring board and an IC card using the same.

【０００５】[0005]

【課題を解決するための手段】本発明は、片面に配線層
が形成された配線基板と、配線基板上の配線層に形成さ
れた第１の電極パッド群及び第２の電極パッド群と、第
２の電極パッド群の直下の配線基板中に形成されたスル
ーホールと、第１の電極パッド群に接続される第１のチ
ップと、第２の電極パッド群に接続される第２のチップ
とを備え、第１の電極パッド群と第２の電極パッド群と
が配線基板の配線層が形成されている面において互いに
ずれて配置形成されていることを特徴としている。同一
配線基板内に異なる機能をもつチップを容易に組み合わ
せることができ、また、同一機能をもったチップを回路
構成が反転（ミラー状態）されないで組み立てることが
できる。According to the present invention, there is provided a wiring board having a wiring layer formed on one surface, a first electrode pad group and a second electrode pad group formed on the wiring layer on the wiring board, A through hole formed in the wiring board immediately below the second electrode pad group, a first chip connected to the first electrode pad group, and a second chip connected to the second electrode pad group Wherein the first electrode pad group and the second electrode pad group are arranged so as to be shifted from each other on the surface of the wiring substrate on which the wiring layer is formed. Chips having different functions can be easily combined in the same wiring board, and chips having the same function can be assembled without inverting (mirror state) the circuit configuration.

【０００６】すなわち、本発明の半導体装置は、配線基
板と、前記配線基板の第１の主面に形成された配線層
と、前記第１の主面に形成された配線層に電気的に接続
するように形成された第１及び第２の電極パッド群と、
前記配線基板の前記第２の電極パッド群の各電極パッド
の直下に形成されたスルーホールと、前記第１の電極パ
ッド群の各電極パッドに接続電極が電気的に接続され、
且つ前記第１の主面に配置された第１のチップと、前記
第２の電極パッド群の各電極パッドに接続電極が前記ス
ルーホールに埋め込まれた接続配線を介して電気的に接
続され、且つ前記配線基板の第２の主面に配置された第
２のチップとを備えたことを特徴としている。前記第１
及び第２の電極パッド群は、それぞれ整列されており、
これらの電極パッド群は、前記第１の主面内において互
いにずれて配置形成されているようにしても良い。前記
第１及び第２のチップは、前記配線基板上にフリップチ
ップ接続されているようにしても良い。前記スルーホー
ルには、前記接続配線として導電物質が充填されている
ようにしても良い。上記半導体装置に用いられた第１及
び第２のチップが取り付けられた配線基板を複数枚用意
し、これらを垂直方向に積層し、且つこれらの配線基板
間を電気的に接続するようにしても良い。前記前記第１
及び第２のチップを絶縁性物質で封止しても良い。前記
前記第１及び第２のチップを絶縁性物質で封止した半導
体装置は、厚さが０．７６ｍｍ以下であるようにしても
良い。前記前記第１及び第２のチップを絶縁性物質で封
止し、厚さが０．７６ｍｍ以下である半導体装置は、Ｉ
Ｃカードとして用いることが可能である。That is, in the semiconductor device of the present invention, a wiring substrate, a wiring layer formed on a first main surface of the wiring substrate, and a wiring layer formed on the first main surface are electrically connected. First and second electrode pad groups formed so as to perform
A connection electrode is electrically connected to a through hole formed directly below each electrode pad of the second electrode pad group of the wiring substrate and each electrode pad of the first electrode pad group;
A connection electrode is electrically connected to a first chip disposed on the first main surface and to each electrode pad of the second electrode pad group via a connection wiring embedded in the through hole; And a second chip disposed on a second main surface of the wiring board. The first
And the second electrode pad group are respectively aligned,
These electrode pad groups may be formed so as to be shifted from each other in the first main surface. The first and second chips may be flip-chip connected on the wiring board. The through hole may be filled with a conductive material as the connection wiring. A plurality of wiring boards to which the first and second chips used in the semiconductor device are attached are prepared, stacked vertically, and these wiring boards are electrically connected. good. The first
Alternatively, the second chip may be sealed with an insulating material. The semiconductor device in which the first and second chips are sealed with an insulating material may have a thickness of 0.76 mm or less. The semiconductor device, wherein the first and second chips are sealed with an insulating material and have a thickness of 0.76 mm or less,
It can be used as a C card.

【０００７】[0007]

【発明の実施の形態】以下、図面を参照して発明の実施
の形態を説明する。まず、図１及び図２を参照して第１
の実施例を説明する。図１は、半導体装置の断面図、図
２は、図１に示す半導体装置に使用されている配線基板
の第１のチップ側（配線基板の上側）からみた平面図で
ある。ポリイミド樹脂絶縁板、エポキシ樹脂含浸ガラス
繊維積層板などから構成された配線基板１には、片側の
面（第１の面）のみに銅などの金属層からなる配線層３
が形成され、その配線層３に接続されるように第１の電
極パッド群７、７′（）と第２の電極パッド群８、
８′（）が形成されている。そして、この配線層３に
接続して外部接続端子９、１０が形成されている。第２
の電極パッド群の直下にはスルーホール１１が形成され
ている。シリコン半導体などからなる第１のチップ２
は、接続用の金バンプ４を備え、この金バンプ４によっ
て、第１の電極パッド群７、７′に接合されている。第
２のチップ２′は、配線基板１の第２の面（裏面）にお
いて、スルーホール１１に埋め込まれた接続配線５に接
続されている。接続配線５は、第２の電極パッド群８、
８′に接続されている。第１の電極パッド群７、７′と
第２の電極パッド群８、８′とは配線基板１の第１の面
内において水平方向に位置がずれている。Embodiments of the present invention will be described below with reference to the drawings. First, referring to FIG. 1 and FIG.
An example will be described. 1 is a cross-sectional view of the semiconductor device, and FIG. 2 is a plan view of a wiring board used in the semiconductor device shown in FIG. 1 as viewed from a first chip side (upper side of the wiring board). A wiring board 1 made of a polyimide resin insulating plate, an epoxy resin impregnated glass fiber laminate, or the like has a wiring layer 3 made of a metal layer such as copper on only one surface (first surface).
Are formed, and the first electrode pad groups 7, 7 '() and the second electrode pad groups 8,
8 '() is formed. External connection terminals 9 and 10 are formed so as to be connected to the wiring layer 3. Second
A through hole 11 is formed directly below the electrode pad group. First chip 2 made of silicon semiconductor or the like
Have gold bumps 4 for connection, and are connected to the first electrode pad groups 7 and 7 ′ by the gold bumps 4. The second chip 2 ′ is connected to the connection wiring 5 embedded in the through hole 11 on the second surface (back surface) of the wiring board 1. The connection wiring 5 includes a second electrode pad group 8,
8 '. The first electrode pad groups 7, 7 'and the second electrode pad groups 8, 8' are displaced horizontally in the first plane of the wiring board 1.

【０００８】２つの第１の電極パッド群７、７′は、２
列に並列され、これと同じ間隔で２つの第２の電極パッ
ド群８、８′が少しずれて２列に並列されている。図２
の左側において、第２の電極パッド群８から引き出され
た配線３は、第１の電極パッド群７の間を通って外部接
続端子９から外に引き出される。また、図２の右側にお
いて、第１の電極パッド群７′から引き出された配線３
は、第２の電極パッド群８′の間を通って引き出され
る。スルーホール１１内は、接続電極５を構成する導電
性材料で埋め込まれている。導電性材料としては、銅の
ような金属、半田のような低融点金属、導電性樹脂など
が使用される。第１のチップ２と第１の電極パッド群
７、７′とはフリップチップ接続されている。フリップ
チップ接続の方法としては、金属接合による接合法（半
田接続、金−半田接続）あるいは異方性導電膜（ＡＣ
Ｆ）や異方性導電ペースト（ＡＣＰ）などを用いた方法
がある。第２のチップ２′は、スルーホール１１を介し
て第２の電極パッド群８、８′に接続される。スルーホ
ール１１と第２のチップ２′との接続方法についても、
第１のチップ２と第１の電極パッド群７、７′の場合と
同様、フリップチップ接続により行われる。このフリッ
プチップ接続に関しても、第１のチップ２の場合と同様
の手法を取ることができる。[0008] The two first electrode pad groups 7, 7 '
The two second electrode pad groups 8, 8 'are arranged in parallel in two rows with a slight shift at the same interval. FIG.
On the left side, the wiring 3 drawn out from the second electrode pad group 8 is drawn out from the external connection terminal 9 through the space between the first electrode pad groups 7. Also, on the right side of FIG. 2, the wiring 3 drawn from the first electrode pad group 7 '
Is drawn out between the second electrode pad groups 8 '. The inside of the through hole 11 is filled with a conductive material forming the connection electrode 5. As the conductive material, a metal such as copper, a low melting point metal such as solder, a conductive resin, or the like is used. The first chip 2 and the first electrode pad groups 7, 7 'are flip-chip connected. As a method of flip-chip connection, a bonding method by metal bonding (solder connection, gold-solder connection) or an anisotropic conductive film (AC
F) or a method using an anisotropic conductive paste (ACP). The second chip 2 'is connected to the second electrode pad groups 8, 8' via the through holes 11. Regarding the connection method between the through hole 11 and the second chip 2 ′,
As in the case of the first chip 2 and the first electrode pad group 7, 7 ', the connection is performed by flip chip connection. For the flip chip connection, the same method as in the case of the first chip 2 can be employed.

【０００９】以上のように、この実施例では、配線基板
上の配線層に形成され、第１のチップに接続される第１
の電極パッド群及び第２のチップに接続される第２の電
極パッド群と、第２の電極パッド群の直下の配線基板中
に形成されたスルーホールとを備え、第１の電極パッド
群と第２の電極パッド群とが配線基板の配線層が形成さ
れている面において互いにずれて配置形成されているの
で、同一機能をもったチップを回路構成が反転（ミラー
状態）されないで容易に組み立てることができる。ま
た、同一配線基板内に異なる機能をもつチップを容易に
組み合わせることができる。As described above, in this embodiment, the first chip formed on the wiring layer on the wiring board and connected to the first chip is formed.
A second electrode pad group connected to the second electrode pad group and the second chip, and a through-hole formed in the wiring board immediately below the second electrode pad group. Since the second electrode pad group and the second electrode pad group are formed so as to be shifted from each other on the surface of the wiring substrate on which the wiring layer is formed, chips having the same function can be easily assembled without inverting the circuit configuration (mirror state). be able to. Further, chips having different functions can be easily combined in the same wiring board.

【００１０】次に、図３を参照して第２の実施例を説明
する。図３は、本発明の半導体装置に使用されている配
線基板の第１のチップ側（配線基板の上側）からみた平
面図である。第１の実施例は、第１の電極パッド群と第
２の電極パッド群とが縦横に格子状に配置されている
が、この実施例では、第１の電極パッド群と第２の電極
パッド群とが千鳥状に配置されている。配線基板２１に
は、片側の面（第１の面）のみに銅などの金属層からな
る配線層２３が形成され、その配線層２３に接続される
ように第１の電極パッド群２７、２７′（）と第２の
電極パッド群２８、２８′（）が形成されている。そ
して、この配線層２３に接続して外部接続端子２９、２
０が形成されている。第２の電極パッド群２８、２８′
の直下にはスルーホールが形成されている。シリコン半
導体などからなる第１のチップは、接続用の金バンプを
備え、この金バンプによって、第１の電極パッド群２
７、２７′に接合されている。第２のチップは、配線基
板２１の第２の面（裏面）において、スルーホールに埋
め込まれた接続配線に接続されている。Next, a second embodiment will be described with reference to FIG. FIG. 3 is a plan view of the wiring board used in the semiconductor device of the present invention as viewed from the first chip side (upper side of the wiring board). In the first embodiment, the first electrode pad group and the second electrode pad group are arranged vertically and horizontally in a lattice shape. In this embodiment, the first electrode pad group and the second electrode pad group are arranged. Groups are arranged in a zigzag pattern. On the wiring board 21, a wiring layer 23 made of a metal layer such as copper is formed only on one surface (first surface), and the first electrode pad groups 27, 27 are connected to the wiring layer 23. () And the second electrode pad group 28, 28 '(). Then, by connecting to the wiring layer 23, the external connection terminals 29, 2
0 is formed. Second electrode pad group 28, 28 '
A through hole is formed immediately below the hole. The first chip made of a silicon semiconductor or the like includes gold bumps for connection, and the gold bumps are used to form the first electrode pad group 2.
7, 27 '. The second chip is connected to the connection wiring embedded in the through hole on the second surface (back surface) of the wiring board 21.

【００１１】接続配線は、第２の電極パッド群２８、２
８′に接続されている。第１の電極パッド群２７、２
７′と第２の電極パッド群２８、２８′とは配線基板２
１の第１の面内において水平方向に位置がずれている。
２つの第１の電極パッド群２７、２７′は、２列に並列
され、これと同じ間隔で２つの第２の電極パッド群２
８、２８′が少しずれて２列並列されている。図３の左
側において、第２の電極パッド群２８から引き出された
配線２３は、第１の電極パッド群２７の間を通って外部
接続端子２９から外に引き出される。また、図３の右側
において、第１の電極パッド群２７′から引き出された
配線２３は、第２の電極パッド群２８′の間を通って引
き出される。第２のチップは、スルーホールを介して第
２の電極パッド群２８、２８′に接続される。スルーホ
ールと第２のチップとの接続方法についても、第１のチ
ップと第１の電極パッド群２７、２７′の場合と同様、
フリップチップ接続により行われる。The connection wiring is made up of the second electrode pad groups 28, 2
8 '. First electrode pad group 27, 2
7 'and the second electrode pad group 28, 28'
The position is shifted in the horizontal direction in the first plane of the first.
The two first electrode pad groups 27, 27 'are arranged in two rows in parallel, and at the same interval, the two second electrode pad groups 2
8, 28 'are arranged in two rows with a slight shift. On the left side of FIG. 3, the wiring 23 drawn out from the second electrode pad group 28 is drawn out from the external connection terminal 29 through the space between the first electrode pad groups 27. In addition, on the right side of FIG. 3, the wiring 23 drawn from the first electrode pad group 27 'is drawn through between the second electrode pad groups 28'. The second chip is connected to the second electrode pad groups 28, 28 'via through holes. The connection method between the through hole and the second chip is also the same as in the case of the first chip and the first electrode pad group 27, 27 '.
This is performed by flip chip connection.

【００１２】以上のように、この実施例では、配線基板
上の配線層に形成され、第１のチップに接続される第１
の電極パッド群及び第２のチップに接続される第２の電
極パッド群と、第２の電極パッド群の直下の配線基板中
に形成されたスルーホールとを備え、第１の電極パッド
群と第２の電極パッド群とが配線基板の配線層が形成さ
れている面において互いにずれて配置形成されているの
で、同一機能をもったチップを回路構成が反転（ミラー
状態）されないで容易に組み立てることができる。ま
た、同一配線基板内に異なる機能をもつチップを容易に
組み合わせることができる。電極パッドを高密度になる
ように配線をパターニングできる。As described above, in this embodiment, the first chip formed on the wiring layer on the wiring board and connected to the first chip is provided.
A second electrode pad group connected to the second electrode pad group and the second chip, and a through-hole formed in the wiring board immediately below the second electrode pad group. Since the second electrode pad group and the second electrode pad group are formed so as to be shifted from each other on the surface of the wiring substrate on which the wiring layer is formed, chips having the same function can be easily assembled without inverting the circuit configuration (mirror state). be able to. Further, chips having different functions can be easily combined in the same wiring board. The wiring can be patterned so that the electrode pads have a high density.

【００１３】次に、図４を参照して第３の実施例を説明
する。図４は、半導体装置の断面図である。ポリイミド
樹脂絶縁板、エポキシ樹脂含浸ガラス繊維積層板などか
ら構成された配線基板３１には、片側の面（第１の面）
のみにアルミニウムなどの金属層からなる配線層３３が
形成され、その配線層３３に接続されるように第１の電
極パッド群３７、３７′と第２の電極パッド群３８、３
８′が形成されている。各電極パッド群は、それぞれ２
列で構成されているので、電極パッド群は、８列からな
っている。そして、この配線層３３に接続して外部接続
端子３９、４０が形成されている。第２の電極パッド群
３８、３８′の直下にはスルーホールが形成されてい
る。シリコン半導体などからなる第１のチップ３２は、
接続用の金バンプ３４を備え、この金バンプ３４によっ
て、第１の電極パッド群３７、３７′に接合されてい
る。第２のチップ３２′は、配線基板３１の第２の面
（裏面）において、スルーホールに埋め込まれた接続配
線３５に接続されている。接続配線３５は、第２の電極
パッド群３８、３８′に接続されている。第１の電極パ
ッド群３７、３７′と第２の電極パッド群３８、３８′
とは配線基板３１の第１の面内において水平方向に位置
がずれている。２つの第１の電極パッド群３７、３７′
は、２列に並列され、これと同じ間隔で２つの第２の電
極パッド群３８、３８′が少しずれて２列に並列されて
いる。Next, a third embodiment will be described with reference to FIG. FIG. 4 is a cross-sectional view of the semiconductor device. The wiring board 31 composed of a polyimide resin insulating plate, an epoxy resin impregnated glass fiber laminate, or the like has one surface (first surface).
A wiring layer 33 made of a metal layer such as aluminum is formed only on the first electrode pad groups 37 and 37 ′ and the second electrode pad groups 38 and 3 so as to be connected to the wiring layer 33.
8 'is formed. Each electrode pad group has 2
Since the electrode pad group is composed of rows, the electrode pad group is composed of eight rows. External connection terminals 39 and 40 are formed so as to be connected to the wiring layer 33. A through hole is formed immediately below the second electrode pad group 38, 38 '. The first chip 32 made of a silicon semiconductor or the like
A gold bump 34 for connection is provided, and the gold bump 34 is connected to the first electrode pad group 37, 37 '. The second chip 32 ′ is connected to the connection wiring 35 embedded in the through hole on the second surface (back surface) of the wiring board 31. The connection wiring 35 is connected to the second electrode pad groups 38 and 38 '. A first electrode pad group 37, 37 'and a second electrode pad group 38, 38'
Is shifted horizontally in the first plane of the wiring board 31. Two first electrode pad groups 37, 37 '
Are arranged in two rows, and two second electrode pad groups 38 and 38 'are arranged in two rows at the same interval with a slight shift.

【００１４】第２の電極パッド群３８から引き出された
配線３３は、外部接続端子３９から外に引き出される。
また、第１の電極パッド群３７′から引き出された配線
３３は、外部接続端子４０から外に引き出される。スル
ーホール内は、接続電極３５を構成する導電性材料で埋
め込まれている。導電性材料としては、銅のような金
属、半田のような低融点金属、導電性樹脂などが使用さ
れる。第１のチップ３２と第１の電極パッド群３７、３
７′とはフリップチップ接続されている。フリップチッ
プ接続の方法としては、金属接合による接合法（半田接
続、金−半田接続）あるいは異方性導電膜（ＡＣＦ）や
異方性導電ペースト（ＡＣＰ）などを用いた方法があ
る。第２のチップ３２′は、スルーホールを介して第２
の電極パッド群３８、３８′に接続される。スルーホー
ルと第２のチップ３２′との接続方法についても、第１
のチップ３２と第１の電極パッド群３７、３７′の場合
と同様、フリップチップ接続により行われる。このフリ
ップチップ接続に関しても、第１のチップ３２の場合と
同様の手法を取ることができる。第１及び第２のチップ
３２、３２′と配線基板３１との間には樹脂封止体（ア
ンダーフィル）３６、３６′が施されている。The wiring 33 drawn out from the second electrode pad group 38 is drawn out from the external connection terminal 39.
Further, the wiring 33 drawn out from the first electrode pad group 37 ′ is drawn out from the external connection terminal 40. The inside of the through hole is filled with a conductive material constituting the connection electrode 35. As the conductive material, a metal such as copper, a low melting point metal such as solder, a conductive resin, or the like is used. The first chip 32 and the first electrode pad group 37,3
7 'is flip-chip connected. As a method of flip chip connection, there is a bonding method by metal bonding (solder connection, gold-solder connection), or a method using an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP). The second chip 32 'is connected to the second chip 32' through a through hole.
Are connected to the electrode pad groups 38, 38 '. Regarding the connection method between the through hole and the second chip 32 ′,
As in the case of the chip 32 and the first electrode pad groups 37 and 37 ', the connection is performed by flip chip connection. Regarding this flip-chip connection, the same method as in the case of the first chip 32 can be used. Resin sealing bodies (underfill) 36, 36 'are provided between the first and second chips 32, 32' and the wiring board 31.

【００１５】以上のように、この実施例では、配線基板
上の配線層に形成され、第１のチップに接続される第１
の電極パッド群及び第２のチップに接続される第２の電
極パッド群と、第２の電極パッド群の直下の配線基板中
に形成されたスルーホールとを備え、第１の電極パッド
群と第２の電極パッド群とが配線基板の配線層が形成さ
れている面において互いにずれて配置形成されているの
で、同一機能をもったチップを回路構成が反転（ミラー
状態）されないで容易に組み立てることができる。ま
た、同一配線基板内に異なる機能をもつチップを容易に
組み合わせることができる。この実施例において電極パ
ッド群は、２列配置になっているが、３列以上にするこ
とも可能である。As described above, in this embodiment, the first chip formed on the wiring layer on the wiring board and connected to the first chip is provided.
A second electrode pad group connected to the second electrode pad group and the second chip, and a through-hole formed in the wiring board immediately below the second electrode pad group. Since the second electrode pad group and the second electrode pad group are formed so as to be shifted from each other on the surface of the wiring substrate on which the wiring layer is formed, chips having the same function can be easily assembled without inverting the circuit configuration (mirror state). be able to. Further, chips having different functions can be easily combined in the same wiring board. In this embodiment, the electrode pad groups are arranged in two rows, but may be arranged in three or more rows.

【００１６】次に、図５乃至図７を参照して第４の実施
例を説明する。図５は、半導体装置の断面図、図６は、
図５に示す半導体装置に使用されている配線基板の第１
のチップ側（配線基板の上側）からみた平面図、図７
は、図５に示す半導体装置に使用されている配線基板の
第１のチップ側（配線基板の上側）からみた平面図であ
る。配線基板４１には、片側の面（第１の面）のみに銅
などの配線層４３が形成され、その配線層４３に接続さ
れるように第１の電極パッド群４７、４７′と第２の電
極パッド群４８、４８′が形成されている。そして、こ
の配線層４３に接続して外部接続端子４９、５０が形成
されている。第２の電極パッド群４７′、の直下にはス
ルーホールが形成されている。シリコン半導体などから
なる第１のチップ４２は、接続用の金バンプ４４を備
え、この金バンプ４４によって、第１の電極パッド群４
７、４７′に接合されている。第２のチップ２′は、配
線基板４１の第２の面（裏面）において、スルーホール
に埋め込まれた接続配線４５に接続されている。接続配
線４５は、第２の電極パッド群４８、４８′に接続され
ている。第１の電極パッド群４７、４７′と第２の電極
パッド群４８、４８′とは配線基板４１の第１の面内に
おいて水平方向に位置がずれている。２つの第１の電極
パッド群４７、４７′は、２列に並列され、この２列の
脇に近接して同じ間隔で２つの第２の電極パッド群４
８、４８′が２列並んでいる。Next, a fourth embodiment will be described with reference to FIGS. FIG. 5 is a cross-sectional view of the semiconductor device, and FIG.
The first of the wiring boards used in the semiconductor device shown in FIG.
FIG. 7 is a plan view from the chip side (upper side of the wiring board) of FIG.
FIG. 6 is a plan view of the wiring board used in the semiconductor device shown in FIG. 5 as viewed from the first chip side (above the wiring board). A wiring layer 43 made of copper or the like is formed only on one surface (first surface) of the wiring board 41, and the first electrode pad groups 47 and 47 ′ and the second Electrode pad groups 48 and 48 'are formed. External connection terminals 49 and 50 are formed so as to be connected to the wiring layer 43. A through hole is formed immediately below the second electrode pad group 47 '. The first chip 42 made of a silicon semiconductor or the like includes a gold bump 44 for connection, and the gold bump 44 allows the first electrode pad group 4
7, 47 '. The second chip 2 ′ is connected to the connection wiring 45 embedded in the through hole on the second surface (back surface) of the wiring board 41. The connection wiring 45 is connected to the second electrode pad groups 48 and 48 '. The first electrode pad groups 47 and 47 'and the second electrode pad groups 48 and 48' are displaced horizontally in the first plane of the wiring board 41. The two first electrode pad groups 47 and 47 ′ are arranged in two rows, and are arranged adjacent to the two rows at equal intervals.
8, 48 'are arranged in two rows.

【００１７】図２の左側において、第２の電極パッド群
４８から引き出された配線４３は、第１の電極パッド群
４７、４７′の間を通って外部接続端子４９から外に引
き出される。また、図２の右側において、第１の電極パ
ッド群４７′から引き出された配線４３は、第２の電極
パッド群４８、４８′の間を通って引き出される。スル
ーホール内は、接続電極４５を構成する導電性材料で埋
め込まれている。第１のチップ４２と第１の電極パッド
群４７、４７′とはフリップチップ接続されている。第
２のチップ４２′は、スルーホールを介して第２の電極
パッド群４８、４８′に接続される。スルーホールと第
２のチップ４２′との接続方法についても、第１のチッ
プ４２と第１の電極パッド群４７、４７′の場合と同
様、フリップチップ接続により行われる。On the left side of FIG. 2, the wiring 43 drawn from the second electrode pad group 48 is drawn out of the external connection terminal 49 through the space between the first electrode pad groups 47 and 47 '. In addition, on the right side of FIG. 2, the wiring 43 drawn out from the first electrode pad group 47 'is drawn out between the second electrode pad groups 48 and 48'. The inside of the through hole is filled with a conductive material constituting the connection electrode 45. The first chip 42 and the first electrode pad groups 47 and 47 'are flip-chip connected. The second chip 42 'is connected to the second electrode pad groups 48, 48' via through holes. The connection method between the through hole and the second chip 42 'is also made by flip chip connection as in the case of the first chip 42 and the first electrode pad group 47, 47'.

【００１８】以上のように、この実施例では、配線基板
上の配線層に形成され、第１のチップに接続される第１
の電極パッド群及び第２のチップに接続される第２の電
極パッド群と、第２の電極パッド群の直下の配線基板中
に形成されたスルーホールとを備え、第１の電極パッド
群と第２の電極パッド群とが配線基板の配線層が形成さ
れている面において互いにずれて配置形成されているの
で、同一機能をもったチップを回路構成が反転（ミラー
状態）されないで容易に組み立てることができる。ま
た、同一配線基板内に異なる機能をもつチップを容易に
組み合わせることができる。この実施例では、電極パッ
ドがチップ中央よりに配置されている。配線基板上の配
線は、第１のチップに接続される電極パッドからの配線
が、図６の左右両方向に延伸し、その一部は第２のチッ
プに接続されるパッドの間を通っている。しかし、図７
に示すように、第１のチップ４２に接続される第１の電
極パッド群４７、４７′からの配線はすべて図の左方向
へ、第２のチップ４２′に接続される第２の電極パッド
４８、４８′からの配線はすべて図の右方向へというよ
うに、別々の方向へ配線が延伸されるようにすることも
可能である。As described above, in this embodiment, the first chip formed on the wiring layer on the wiring board and connected to the first chip is formed.
A second electrode pad group connected to the second electrode pad group and the second chip, and a through-hole formed in the wiring board immediately below the second electrode pad group. Since the second electrode pad group and the second electrode pad group are formed so as to be shifted from each other on the surface of the wiring substrate on which the wiring layer is formed, chips having the same function can be easily assembled without inverting the circuit configuration (mirror state). be able to. Further, chips having different functions can be easily combined in the same wiring board. In this embodiment, the electrode pads are arranged near the center of the chip. In the wiring on the wiring board, the wiring from the electrode pad connected to the first chip extends in both the left and right directions in FIG. 6, and a part of the wiring passes between the pads connected to the second chip. . However, FIG.
As shown in the figure, the wirings from the first electrode pad groups 47 and 47 'connected to the first chip 42 are all directed to the left in the figure, and the second electrode pads connected to the second chip 42' It is also possible for the wires from 48 and 48 'to extend in different directions, such as to the right in the figure.

【００１９】次に、図８を参照して第５の実施例を説明
する。図８は、半導体装置の断面図である。この実施例
では、前述の実施例で用いた配線基板を複数個積層した
ことに特徴がある。ポリイミド樹脂絶縁板、エポキシ樹
脂含浸ガラス繊維積層板などから構成された第１の配線
基板５１には、片側の面（第１の面）のみに銅などの金
属層からなる配線層５３が形成され、その配線層５３に
接続されるように第１の電極パッド群５７、５７′と第
２の電極パッド群５８、５８′が形成されている。そし
て、この配線層５３に接続して外部接続端子５９、６０
が形成されている。第２の電極パッド群５８、５８′の
直下にはスルーホールが形成されている。シリコン半導
体などからなる第１のチップ５２は、接続用の金バンプ
５４を備え、この金バンプ５４によって、第１の電極パ
ッド群５７、５７′に接合されている。第２のチップ５
２′は、第１の配線基板５１の第２の面（裏面）におい
て、スルーホールに埋め込まれた接続配線５５に接続さ
れている。接続配線５５は、第２の電極パッド群５８、
５８′に接続されている。第１の電極パッド群５７、５
７′と第２の電極パッド群５８、５８′とは第１の配線
基板５１の第１の面内において水平方向に位置がずれて
いる。２つの第１の電極パッド群５７、５７′は、２列
に並列され、これと同じ間隔で２つの第２の電極パッド
群５８、５８′が少しずれて２列に並列されている。Next, a fifth embodiment will be described with reference to FIG. FIG. 8 is a cross-sectional view of the semiconductor device. This embodiment is characterized in that a plurality of wiring boards used in the above-described embodiment are stacked. On a first wiring board 51 made of a polyimide resin insulating plate, an epoxy resin impregnated glass fiber laminate, or the like, a wiring layer 53 made of a metal layer such as copper is formed only on one surface (first surface). A first electrode pad group 57, 57 'and a second electrode pad group 58, 58' are formed so as to be connected to the wiring layer 53. Then, the external connection terminals 59 and 60 are connected to the wiring layer 53.
Are formed. A through hole is formed immediately below the second electrode pad groups 58 and 58 '. The first chip 52 made of a silicon semiconductor or the like has a gold bump 54 for connection, and is connected to the first electrode pad group 57, 57 'by the gold bump 54. Second chip 5
2 'is connected to the connection wiring 55 embedded in the through hole on the second surface (back surface) of the first wiring board 51. The connection wiring 55 includes a second electrode pad group 58,
58 '. First electrode pad group 57, 5
7 ′ and the second electrode pad groups 58, 58 ′ are horizontally displaced in the first plane of the first wiring board 51. The two first electrode pad groups 57, 57 'are arranged in two rows, and the two second electrode pad groups 58, 58' are arranged in two rows at the same interval with a slight shift.

【００２０】第１のチップ５２と第１の電極パッド群５
７、５７′とはフリップチップ接続されている。第２の
チップ５２′は、スルーホールを介して第２の電極パッ
ド群５８、５８′に接続される。スルーホールと第２の
チップ５２′との接続方法についても、第１のチップ５
２と第１の電極パッド群５７、５７′の場合と同様、フ
リップチップ接続により行われる。第２の配線基板５
１′は、配線基板も搭載するチップも同じものを用い
る。しかし、本発明ではそれぞれ異なるものを用いるこ
とが可能である。第１の配線基板５１の外部接続端子５
９、６０の直下にスルーホールが形成され、この中に接
続配線５９′、６０′となる導電物質が埋め込まれてい
る。そして、第１の配線基板５１の第２の面（裏面）に
は接続配線５９′、６０′に電気的に接続されるように
金属柱などの外部端子６２が取り付けられている。この
外部端子６２が第２の配線基板５１′の外部接続端子に
接合されて両者が積層されることになる。第２の配線基
板５１′の外部端子６２′は、さらに第３の配線基板に
接続されるか、あるいは実装基板に接合される。First chip 52 and first electrode pad group 5
7, 57 'are flip-chip connected. The second chip 52 'is connected to the second electrode pad groups 58, 58' via through holes. Regarding the connection method between the through hole and the second chip 52 ′, the first chip 5
As in the case of the second and first electrode pad groups 57 and 57 ', the connection is performed by flip chip connection. Second wiring board 5
1 'uses the same wiring board and the same chip. However, different ones can be used in the present invention. External connection terminal 5 of first wiring board 51
A through-hole is formed directly below 9, 60, and a conductive material serving as connection wirings 59 ', 60' is buried therein. External terminals 62 such as metal columns are attached to the second surface (back surface) of the first wiring board 51 so as to be electrically connected to the connection wirings 59 'and 60'. The external terminals 62 are joined to the external connection terminals of the second wiring board 51 ', and both are laminated. The external terminals 62 'of the second wiring board 51' are further connected to a third wiring board or joined to a mounting board.

【００２１】以上のように、この実施例では、各配線基
板上の配線層に形成され、第１のチップに接続される第
１の電極パッド群及び第２のチップに接続される第２の
電極パッド群と、第２の電極パッド群の直下の配線基板
中に形成されたスルーホールとを備え、第１の電極パッ
ド群と第２の電極パッド群とが配線基板の配線層が形成
されている面において互いにずれて配置形成されている
ので、同一機能をもったチップを回路構成が反転（ミラ
ー状態）されないで容易に組み立てることができる。ま
た、同一配線基板内に異なる機能をもつチップを容易に
組み合わせることができる。この実施例において、第１
及び第２のチップの厚さをそれぞれ５０μｍ、それぞれ
のチップの基板から接続高さを同じく５０μｍとした場
合、金属柱の高さは２００μｍ以上あればよい。金属柱
としてははんだのような低融点金属あるいは銅のような
配線材料を使用することが可能である。As described above, in this embodiment, the first electrode pad group formed on the wiring layer on each wiring board and connected to the first chip and the second electrode pad group connected to the second chip are formed. An electrode pad group; and a through hole formed in the wiring board immediately below the second electrode pad group, wherein the first electrode pad group and the second electrode pad group form a wiring layer of the wiring board. The chips having the same function can be easily assembled without reversing the circuit configuration (mirror state). Further, chips having different functions can be easily combined in the same wiring board. In this embodiment, the first
When the thickness of each of the second chip and the second chip is 50 μm, and the connection height from the substrate of each chip is also 50 μm, the height of the metal pillar may be 200 μm or more. As the metal pillar, a low melting point metal such as solder or a wiring material such as copper can be used.

【００２２】次に、図９を参照して第６の実施例を説明
する。図９は、半導体装置の断面図である。この実施例
では、配線基板の積層構造にに特徴がある。ここに説明
する配線基板及びこれに搭載されるチップは、第５の実
施例と同じものを用いている。第１の配線基板７０の第
１の面に形成され、配線層に接続された外部接続端子７
１の直下にスルーホールが形成され、この中に接続配線
７２となる導電物質が埋め込まれている。同様に、第２
の配線基板７０′の第１の面に形成され、配線層に接続
された外部接続端子７１′の直下にスルーホールが形成
され、この中に接続配線７２′となる導電物質が埋め込
まれている。第１の配線基板７０と第２の配線基板７
０′との間にはスペーサ７３がそれぞれ外部端子７
５′、７５″を介して挿入されている。スペーサ７３内
には導通を取るためのスルーホールが形成されており、
このなかに接続配線７４となる導電物質が埋め込まれて
いる。スペーサ７３に形成された接続配線７４は、第１
の配線基板７０の外部接続端子７１と第２の配線基板７
０′の外部接続端子７１′とを電気的に接続する。第２
の配線基板７０′の第２の面（裏面）には外部端子７５
が取り付けられており、外部端子７５は、更に第３の配
線基板に接続されるか、あるいは実装基板に接合され
る。Next, a sixth embodiment will be described with reference to FIG. FIG. 9 is a cross-sectional view of the semiconductor device. This embodiment is characterized by the laminated structure of the wiring board. The wiring board and the chip mounted thereon used here are the same as those in the fifth embodiment. External connection terminals 7 formed on the first surface of first wiring board 70 and connected to the wiring layer
A through-hole is formed immediately below 1, and a conductive material serving as the connection wiring 72 is buried in the through-hole. Similarly, the second
Is formed on the first surface of the wiring board 70 ', and a through-hole is formed immediately below the external connection terminal 71' connected to the wiring layer, and a conductive material serving as the connection wiring 72 'is embedded therein. . First wiring board 70 and second wiring board 7
0 ′ are connected to the external terminals 7 respectively.
5 ', 75 ". Through holes are formed in the spacer 73 to establish conduction.
A conductive material serving as the connection wiring 74 is buried therein. The connection wiring 74 formed in the spacer 73 is the first wiring.
External connection terminals 71 of the wiring board 70 and the second wiring board 7
0 'is externally connected to the external connection terminal 71'. Second
The external terminals 75 are provided on the second surface (back surface) of the wiring board 70 ′.
Are attached, and the external terminals 75 are further connected to a third wiring board or joined to a mounting board.

【００２３】以上のように、この実施例では、各配線基
板上の配線層に形成され、第１のチップに接続される第
１の電極パッド群及び第２のチップに接続される第２の
電極パッド群と、第２の電極パッド群の直下の配線基板
中に形成されたスルーホールとを備え、第１の電極パッ
ド群と第２の電極パッド群とが配線基板の配線層が形成
されている面において互いにずれて配置形成されている
ので、同一機能をもったチップを回路構成が反転（ミラ
ー状態）されないで容易に組み立てることができる。ま
た、同一配線基板内に異なる機能をもつチップを容易に
組み合わせることができる。第１の配線基板と第２の配
線基板との間隙を大きく取れるため、チップ厚さを厚く
することができる。またスペーサに多層基板を用いるこ
とにより、電気的特性の向上を図ることも可能となる。As described above, in this embodiment, the first electrode pad group connected to the first chip and the second electrode pad group connected to the second chip are formed on the wiring layer on each wiring board. An electrode pad group; and a through hole formed in the wiring board immediately below the second electrode pad group, wherein the first electrode pad group and the second electrode pad group form a wiring layer of the wiring board. The chips having the same function can be easily assembled without reversing the circuit configuration (mirror state). Further, chips having different functions can be easily combined in the same wiring board. Since a large gap is provided between the first wiring board and the second wiring board, the chip thickness can be increased. In addition, by using a multilayer substrate for the spacer, it is possible to improve electrical characteristics.

【００２４】次に、図１０を参照して第７の実施例を説
明する。図１０は、半導体装置の断面図である。この実
施例では、第１の実施例で用いた配線基板及びチップを
用いる。ポリイミド樹脂絶縁板、エポキシ樹脂含浸ガラ
ス繊維積層板などから構成された配線基板７６には、片
側の面（第１の面）のみに銅などの金属層からなる配線
層７７が形成されその配線層７７に接続されるように第
１の電極パッド群と第２の電極パッド群が形成されてい
る。そして、この配線層７７に接続して外部接続端子が
形成されている。第２の電極パッド群の直下にはスルー
ホールが形成されている。シリコン半導体などからなる
第１のチップ７８は、金バンプによって、第１の電極パ
ッド群に接合されている。第２のチップ７８′は、配線
基板７６の第２の面（裏面）において、スルーホールに
埋め込まれた接続配線に接続されている。接続配線は、
第２の電極パッド群に接続されている。第１の電極パッ
ド群と第２の電極パッド群とは第１の配線基板７６の第
１の面内において水平方向に位置がずれている。２つの
第１の電極パッド群は、２列に並列され、また２つの第
２の電極パッド群が少しずれて２列に並列されている。Next, a seventh embodiment will be described with reference to FIG. FIG. 10 is a cross-sectional view of the semiconductor device. In this embodiment, the wiring board and the chip used in the first embodiment are used. On a wiring board 76 composed of a polyimide resin insulating board, an epoxy resin impregnated glass fiber laminated board or the like, a wiring layer 77 made of a metal layer such as copper is formed only on one surface (first surface). A first electrode pad group and a second electrode pad group are formed so as to be connected to 77. An external connection terminal is formed by connecting to the wiring layer 77. A through hole is formed immediately below the second electrode pad group. The first chip 78 made of a silicon semiconductor or the like is joined to the first electrode pad group by gold bumps. The second chip 78 ′ is connected to the connection wiring embedded in the through hole on the second surface (back surface) of the wiring board 76. Connection wiring
It is connected to the second electrode pad group. The first electrode pad group and the second electrode pad group are horizontally displaced in the first plane of the first wiring board 76. The two first electrode pad groups are arranged in two rows, and the two second electrode pad groups are arranged in two rows with a slight shift.

【００２５】第１及び第２のチップ７８、７８′が搭載
された配線基板７６の両面にポリイミドなどの絶縁性樹
脂膜７９が形成され、チップを含む配線基板７６全体を
保護している。例えば、第１及び第２のチップの厚さを
それぞれ５０μｍ、第１及び第２のチップと配線基板と
の間隙をそれぞれ１５μｍ、配線基板の厚さを５０μｍ
とすると、半導体装置の厚さは１８０μｍとなる。従っ
て、チップの両面にそれぞれ１００μｍの保護樹脂を形
成したとしても、全体の厚さは４００μｍを下回る。こ
れはＩＣカードの規格である７６０μｍよりも薄い。従
ってこの実施例の半導体装置は耐環境性及び薄さの双方
が要求されるＩＣカードなどに適用することが可能であ
る。An insulating resin film 79 such as polyimide is formed on both surfaces of the wiring board 76 on which the first and second chips 78 and 78 'are mounted, and protects the entire wiring board 76 including the chips. For example, the thickness of each of the first and second chips is 50 μm, the gap between the first and second chips and the wiring board is 15 μm, and the thickness of the wiring board is 50 μm.
Then, the thickness of the semiconductor device becomes 180 μm. Therefore, even if a protective resin of 100 μm is formed on both surfaces of the chip, the overall thickness is less than 400 μm. This is thinner than the standard of 760 μm of the IC card. Therefore, the semiconductor device of this embodiment can be applied to an IC card or the like that requires both environmental resistance and thinness.

【００２６】次に、図１１を参照して第８の実施例を説
明する。図１１は、半導体装置の断面図である。この実
施例では、配線基板に異種のチップを搭載させることに
特徴がある。ポリイミド樹脂絶縁板、エポキシ樹脂含浸
ガラス繊維積層板などから構成された配線基板８０に
は、片側の面（第１の面）のみに銅などの金属層からな
る配線層８３が形成されその配線層８３に接続されるよ
うに第１の電極パッド群８７、８７′と第２の電極パッ
ド群８８、８８′が形成されている。そして、この配線
層８３に接続して外部接続端子が形成されている。第２
の電極パッド群８８、８８′の直下にはスルーホールが
形成されている。シリコン半導体などからなる第１のチ
ップ８１は、接着剤８９によって配線基板８０に接着さ
れ、ボンディングワイヤによって、第１の電極パッド群
８７、８７′に接合されている。この第１のチップ８１
は樹脂封止体８５により封止されている。第２のチップ
８２は、配線基板８０の第２の面（裏面）において、ス
ルーホールに埋め込まれた接続配線８６にバンプを介し
て接続されている。接続配線８６は、第１の面の第２の
電極パッド群８８、８８′に接続されている。第１の電
極パッド群８７と第２の電極パッド群８８、８８′とは
第１の配線基板８０の第１の面内において水平方向に位
置がずれている。２つの第１の電極パッド群は、２列に
並列され、２つの第２の電極パッド群が少しずれて２列
に並列されている。Next, an eighth embodiment will be described with reference to FIG. FIG. 11 is a cross-sectional view of the semiconductor device. This embodiment is characterized in that different kinds of chips are mounted on a wiring board. On a wiring board 80 composed of a polyimide resin insulating plate, an epoxy resin impregnated glass fiber laminate, or the like, a wiring layer 83 made of a metal layer such as copper is formed only on one surface (first surface). A first electrode pad group 87, 87 'and a second electrode pad group 88, 88' are formed so as to be connected to 83. An external connection terminal is formed by connecting to the wiring layer 83. Second
Through holes are formed directly below the electrode pad groups 88 and 88 '. The first chip 81 made of a silicon semiconductor or the like is adhered to the wiring board 80 by an adhesive 89 and joined to the first electrode pad groups 87 and 87 'by bonding wires. This first chip 81
Is sealed by a resin sealing body 85. The second chip 82 is connected to the connection wiring 86 embedded in the through hole via a bump on the second surface (back surface) of the wiring board 80. The connection wiring 86 is connected to the second electrode pad groups 88 and 88 'on the first surface. The first electrode pad group 87 and the second electrode pad groups 88 and 88 ′ are horizontally displaced in the first plane of the first wiring board 80. The two first electrode pad groups are arranged in two rows, and the two second electrode pad groups are arranged in two rows with a slight shift.

【００２７】以上のように、この実施例では、各配線基
板上の配線層に形成され、第１のチップに接続される第
１の電極パッド群及び第２のチップに接続される第２の
電極パッド群と、第２の電極パッド群の直下の配線基板
中に形成されたスルーホールとを備え、第１の電極パッ
ド群と第２の電極パッド群とが配線基板の配線層が形成
されている面において互いにずれて配置形成されている
ので、同一機能をもったチップを回路構成が反転（ミラ
ー状態）されないで容易に組み立てることができる。し
かし、この実施例では、同一配線基板内に異なる機能を
もつチップを組み合わている。例えば、第１のチップ８
１は、コントローラであり、第２のチップ８２は、メモ
リである。この半導体装置は、メモリカードに用いられ
る。As described above, in this embodiment, the first electrode pad group connected to the first chip and the second electrode pad group connected to the second chip are formed on the wiring layer on each wiring board. An electrode pad group; and a through hole formed in the wiring board immediately below the second electrode pad group, wherein the first electrode pad group and the second electrode pad group form a wiring layer of the wiring board. The chips having the same function can be easily assembled without reversing the circuit configuration (mirror state). However, in this embodiment, chips having different functions are combined in the same wiring board. For example, the first chip 8
1 is a controller, and the second chip 82 is a memory. This semiconductor device is used for a memory card.

【００２８】[0028]

【発明の効果】本発明は以上の構成により、同一配線基
板内に異なる機能をもつ複数のチップを容易に組み合わ
せることができ、また、同一機能をもったチップを回路
構成が反転（ミラー状態）されないで容易に組み立てる
ことができる。According to the present invention, a plurality of chips having different functions can be easily combined in the same wiring board, and a chip having the same function can be inverted (mirror state). Can be easily assembled without being done.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の半導体装置の断面図。FIG. 1 is a cross-sectional view of a semiconductor device of the present invention.

【図２】図１の半導体装置に用いる配線基板の平面図。FIG. 2 is a plan view of a wiring board used in the semiconductor device of FIG. 1;

【図３】本発明の半導体装置に用いる配線基板の平面
図。FIG. 3 is a plan view of a wiring board used for the semiconductor device of the present invention.

【図４】本発明の半導体装置の断面図。FIG. 4 is a cross-sectional view of the semiconductor device of the present invention.

【図５】本発明の半導体装置の断面図。FIG. 5 is a cross-sectional view of a semiconductor device of the present invention.

【図６】図５の半導体装置に用いる配線基板の平面図。FIG. 6 is a plan view of a wiring board used in the semiconductor device of FIG. 5;

【図７】図５の半導体装置に用いる配線基板の平面図。FIG. 7 is a plan view of a wiring board used in the semiconductor device of FIG. 5;

【図８】本発明の半導体装置の断面図。FIG. 8 is a cross-sectional view of a semiconductor device of the present invention.

【図９】本発明の半導体装置の断面図。FIG. 9 is a cross-sectional view of a semiconductor device of the present invention.

【図１０】本発明の半導体装置の断面図。FIG. 10 is a cross-sectional view of a semiconductor device of the present invention.

【図１１】本発明の半導体装置の断面図。FIG. 11 is a cross-sectional view of a semiconductor device of the present invention.

【図１２】従来の半導体装置の断面図。FIG. 12 is a cross-sectional view of a conventional semiconductor device.

【図１３】従来の半導体装置の断面図。FIG. 13 is a cross-sectional view of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１、３１、４１、５１、５１′、７０、７０′、７６、
８０、１１１・・・配線基板、 ２、２′、３２、３２′、４２、４２′、５２、５
２′、７８、７８′、８１、８２、１００、１００′、
１１０、１１０′・・・チップ、 ３、３３、４３、５３、７７、８３、１１２、１１２′
・・・配線層、 ４、４′、３４、３４′、４４、４４′、５４、５
４′、１１３、１１３′・・・バンプ、 ５、３５、４５、５５、５９′、６０′、７２、７
２′、７４、８６・・・接続配線、 ６、６′、３６、３６′、４６、４６′、５６、５
６′、８５、１１４、１１４′・・・樹脂封止体、 ７、７′、２７、２７′、３７、３７′、４７、４
７′、５７、５７′、８７、８７′・・・・第１の電極
パッド群、 ８、８′、２８、２８′、３８、３８′、４８、４
８′、５８、５８′、８８、８８′・・・第２の電極パ
ッド群、 ９、１０、３９、４０、４９、５０、５９、６０、７
１、７１′、７７・・・外部接続端子、 １１・・・スルーホール、 ６２、６２′、７５、７５′、７５″・・・外部端子、 ７３・・・スペーサ、 ７９・・・絶縁膜、 ８４、１０３、１０３′・・・ボンディングワイヤ、 ８９、１０４、１０４′・・・接着剤、 １０１・・・リードフレームのリード、 １０２・・・リードフレームの素子搭載部。1, 31, 41, 51, 51 ', 70, 70', 76,
80, 111 ... wiring board, 2, 2 ', 32, 32', 42, 42 ', 52, 5
2 ', 78, 78', 81, 82, 100, 100 ',
110, 110 '... chip, 3, 33, 43, 53, 77, 83, 112, 112'
... Wiring layers, 4, 4 ', 34, 34', 44, 44 ', 54, 5
4 ', 113, 113' ... bump, 5, 35, 45, 55, 59 ', 60', 72, 7
2 ', 74, 86 ... connection wiring, 6, 6', 36, 36 ', 46, 46', 56, 5
6 ', 85, 114, 114' ... resin sealing body, 7, 7 ', 27, 27', 37, 37 ', 47, 4
7 ', 57, 57', 87, 87 '... first electrode pad group, 8, 8', 28, 28 ', 38, 38', 48, 4
8 ', 58, 58', 88, 88 '... second electrode pad group 9, 10, 39, 40, 49, 50, 59, 60, 7
1, 71 ', 77 ... external connection terminal, 11 ... through hole, 62, 62', 75, 75 ', 75 "... external terminal, 73 ... spacer, 79 ... insulating film 84, 103, 103 ': bonding wire, 89, 104, 104': adhesive, 101: lead of lead frame, 102: element mounting portion of lead frame.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 有田 亮 福岡県鞍手郡宮田町大字上大隅476番地の １ 福岡東芝エレクトロニクス株式会社内 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Ryo Arita 1 at 476 Kami-Osumi, Ota, Miyata-cho, Kurate-gun, Fukuoka 1 Fukuoka Toshiba Electronics Corporation

Claims (8)

【特許請求の範囲】[Claims] 【請求項１】 配線基板と、 前記配線基板の第１の主面に形成された配線層と、 前記第１の主面に形成された配線層に電気的に接続する
ように形成された第１及び第２の電極パッド群と、 前記配線基板の前記第２の電極パッド群の各電極パッド
の直下に形成されたスルーホールと、 前記第１の電極パッド群の各電極パッドに接続電極が電
気的に接続され、且つ前記第１の主面に配置された第１
の半導体チップと、 前記第２の電極パッド群の各電極パッドに接続電極が前
記スルーホールに埋め込まれた接続配線を介して電気的
に接続され、且つ前記配線基板の第２の主面に配置され
た第２の半導体チップとを備えたことを特徴とする半導
体装置。A wiring board formed on a first main surface of the wiring board; and a wiring layer formed on the first main surface so as to be electrically connected to the wiring layer formed on the first main surface. A first and a second electrode pad group; a through-hole formed directly below each electrode pad of the second electrode pad group on the wiring board; and a connection electrode on each electrode pad of the first electrode pad group. A first electrode electrically connected to the first main surface;
A connection electrode is electrically connected to each of the electrode pads of the second electrode pad group via connection wiring embedded in the through-hole, and is disposed on a second main surface of the wiring substrate. A semiconductor device comprising: a second semiconductor chip according to claim 1. 【請求項２】 前記第１及び第２の電極パッド群は、そ
れぞれ整列されており、これらの電極パッド群は、前記
第１の主面内において互いにずれて配置形成されている
ことを特徴とする請求項１に記載の半導体装置。2. The method according to claim 1, wherein the first and second electrode pad groups are aligned, and the electrode pad groups are formed so as to be shifted from each other in the first main surface. The semiconductor device according to claim 1. 【請求項３】 前記第１及び第２の半導体チップは、前
記配線基板上にフリップチップ接続されていることを特
徴とする前記請求項１又は請求項２記載に半導体装置。3. The semiconductor device according to claim 1, wherein the first and second semiconductor chips are flip-chip connected on the wiring board. 【請求項４】 前記スルーホールには、前記接続配線と
して導電物質が充填されていることを特徴とする請求項
１乃至請求項３にいずれかに記載の半導体装置。4. The semiconductor device according to claim 1, wherein said through hole is filled with a conductive material as said connection wiring. 【請求項５】 請求項１乃至請求項４のいずれかに記載
の半導体装置に用いられた前記第１及び第２の半導体チ
ップが取り付けられた前記配線基板を複数枚用意し、こ
れらを垂直方向に積層し、且つこれらの配線基板間を電
気的に接続したことを特徴とする半導体装置。5. A plurality of the wiring boards to which the first and second semiconductor chips used in the semiconductor device according to claim 1 are attached are prepared, and these are mounted in a vertical direction. A semiconductor device, wherein the wiring substrates are electrically connected to each other. 【請求項６】 前記前記第１及び第２の半導体チップを
絶縁性物質で封止したことを特徴とする請求項１乃至請
求項４のいずれかに記載の半導体装置。6. The semiconductor device according to claim 1, wherein said first and second semiconductor chips are sealed with an insulating material. 【請求項７】 厚さが０．７６ｍｍ以下であることを特
徴とする請求項６に記載の半導体装置。7. The semiconductor device according to claim 6, wherein the thickness is 0.76 mm or less. 【請求項８】 請求項７に記載の半導体装置を用いたこ
とを特徴とするＩＣカード。8. An IC card using the semiconductor device according to claim 7.
JP36100099A 1999-12-20 1999-12-20 Semiconductor device and IC card Pending JP2001177049A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP36100099A JP2001177049A (en) 1999-12-20 1999-12-20 Semiconductor device and IC card

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP36100099A JP2001177049A (en) 1999-12-20 1999-12-20 Semiconductor device and IC card

Publications (1)

Publication Number Publication Date
JP2001177049A true JP2001177049A (en) 2001-06-29

Family

ID=18471777

Family Applications (1)

Application Number Title Priority Date Filing Date
JP36100099A Pending JP2001177049A (en) 1999-12-20 1999-12-20 Semiconductor device and IC card

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Country Link
JP (1) JP2001177049A (en)

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US7122400B2 (en) * 2003-09-17 2006-10-17 Infineon Technologies Ag Method of fabricating an interconnection for chip sandwich arrangements
US8541874B2 (en) 2004-06-30 2013-09-24 Renesas Electronics Corporation Semiconductor device
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